Simulation Results and Layout

Figure 4-22 Power spectrum of the second-order sigma-delta modulator

Figure 4-23 SNDR versus input amplitude

(SS) peak SNDR=51.84 dB (SF) peak SNDR=51.45 dB

(FF) peak SNDR=47.8324 dB (FS) peak SNDR=47.8613 dB Figure 4-24 Simulations results of SS, SF, FF, FS cases

Figure 4-25 The layout of the second-order sigma-delta modulator

The layout shown in Figure 4-25 is divided into analog and digital parts. The left part of the layout is the digital blocks which includes a clock generator and four-phase voltage boosters. The right part is the analog part which contains two amplifiers, two analog switch arrays, two capacitor arrays, and a bias circuit. The switch array is made up of 5x5 switches. The unit capacitance of the cap1 is 300fF. The unit capacitance of the cap2 is 500fF. The rest area of the layout are filled with PMOS capacitors which are used as decoupling capacitors. The decoupling capacitors are connected to the power plane.

Cap1 Cap2

Bias

OTA1 OTA2 Clock

Double Voltage

SW

Table 4-1 The summary of the performance

Specification Performance Value Unit

Signal Bandwidth 50 Hz

Sampling Frequency 6.4 kHz

Input Range ±300 f Farad

Dynamic Range 52.39 dB

Peak SNDR 52.75 dB

Supply Voltage 1 V

Power Consumption 1.5 µW

Chip / Core area 0.86x0.73/0.63x0.37 mm²

Technology 0.18 µm (TSMC)

The simulation results show that peak SNDR is 52.7517dB, ENOB is 8.48-bit, and dynamic range is 52.39dB with OSR of 64 for the application in humidity sensors (signal bandwidth is 50 Hz). The chip area is 0.86x0.73 mm².

Chapter 5 Conclusions

5.1 Conclusions

This thesis presents an ultra low-power sigma-delta modulator for humidity sensors. It consumes only 1.5µW with single-loop double-feedback architecture.

According to paper survey, the lower power modulators are single-loop due to less circuit components and matching requirements. The switch-capacitor integrator provides a more accurate integrators and higher power efficiency. Therefore, this thesis achieves a peak SNDR of 52.75 dB, and DR of 52.39 dB at a sampling rate 6.4 kHz and a signal bandwidth of 50 Hz.

The proposed modulator is implemented under a single 1-V supply voltage.

Many low-voltage design techniques are used to solve the switch-driving problem, and enhance the gain of an amplifier. The correlated double sampling technique is used to eliminate the offset voltage and attenuate the noise floor. The ultra low-power modulator with only 1.5µW power consumption greatly extends battery life time. This meets the requirement for the application of environmental monitoring.

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