Summary - Fundamentals of Sigma-Delta Modulator

Chapter 2 Fundamentals of Sigma-Delta Modulator

2.5 Summary

The sampling rate of Nyquist A/D converters is only twice of the signal band.

However, it is difficult to achieve high resolution A/D conversion due to requirements of accurate anti-aliasing filters. The oversampling technique is a good approach to achieve high resolution A/D converters. The sigma-delta modulator is the most used architecture in the oversampling A/D converters. For the area of sensors, a low power high resolution A/D converter is necessary. The sigma-delta modulators which combined with the front-end circuits for sensors are preferred because it can reduce the power consumption. In order to achieve a higher resolution, the non-linear effects due to the imperfection of the circuits should be taken into account. Another important issue is the tonal behavior which can degrade the SNR should also be taken into consideration. Some practical solutions that can reduce the non-linear phenomenon described in the previous sections should be added into the circuit-level

implementation.

Chapter 3 The Proposed

Low-Voltage Low-Power Sigma-Delta Modulator for Humidity Sensors

3.1 Introduction

In this chapter, the structure of the proposed sigma-delta modulator is presented.

We introduce the proposed first-order sigma-delta modulator for humidity sensors in Section 3.2. In Section 3.3, the proposed second-order sigma-delta modulator is introduced. The oversampling ratio and the effect of finite-gain amplifier are simulated by MATLAB. In Section 3.4, the tonal behavior of both first-order and second-order sigma-delta modulators are discussed. The methods to reduce the tonal behavior are also presented.

3.2 The First-Order Sigma-Delta Modulator

3.2.1 Circuit Architecture

Figure 3-1 shows the structure utilizing a sigma-delta technique for humidity

sensors[16][17][18]. Based on the sigma-delta technique, the first-order sigma-delta modulator detects the capacitance change and provides the digital readout with good accuracy. The structure consists of a SC integrator, a comparator, and a simple 1-bit feedback DAC.

Figure 3-1 The first-order sigma-delta modulator

In the proposed circuit, C₁ is the sensor capacitor, C₂ is the reference capacitor, and C_R is used for the feedback DAC.The basic idea of the proposed sigma-delta modulator is based on the two types of parasitic insensitive integrators shown in Figure 3-2. The parasitic insensitive integrator is a critical component in high-accuracy switched-capacitor integrated circuits. The first one shown in Figure 3-2(a) is a noninverting SC integrator. The transfer function is found to be

( ) ( )

The second one shown in Figure 3-2(b) is a delay-free integrator. It has the transfer function as

By combining the two types of SC integrators[2][3], we can implement a front-end circuit which can detect the capacitance difference of the sensor. So in our design, a capacitance-to-voltage converter is not needed. The power consumption in our design is reduced comparing to other approaches.

quantizer

(a)

(b)

Figure 3-2 (a) Noninverting SC integrator (b) Delay-free SC integrator

In order to understand the operation of the proposed circuit, how the circuit works at each phase is shown in Figure 3-3 and 3-4. Figure 3-3 illustrates the operation when output y=1 at each phase. Figure 3-4 illustrates the operation when output y=0 at each phase.

φ1 φ1

φ2 φ2

C

Vout φ1

φ1 φ2 φ2

C

Vout Vin

Vin

Figure 3-3 Operation when output y=1

At phase 2φ , total charge transferring into integrator capacitor C_f causes

( )

¹ ^REF ² ^REF ^{R REF}

From the same mechanism when y=0 as shown in Figure 3-4, the output voltage of the integrator is given by number of the cycles when y=0. Combine both equations (3.3) and (3.4)and base on the concept of the sigma-delta technique, we obtain the relation between input and

output as follows:

Figure 3-4 Operation when y=0

From equation (3.5) derived above, ∆C is the difference between sensor capacitor and reference capacitor. After K clock cycles, the circuit provides digital output according to the capacitance change.

3.2.2 Determine OSR and finite gain of the operational amplifier

As discussed in Section 2.4.2, choosing an appropriate OSR is important in the

quantizer

design of sigma-delta modulator. In this section, our goal is to determine an OSR for the system to achieve 10-bit resolution. The analysis is done by the MATLAB simulation based on the z-domain linear model. We construct the system in SIMULINK as shown in Figure 3-5. By changing different OSR of the simulated system, we obtain the result in Table 3-1. Table 3-1 shows the relationship between OSR and peak SNR. We know that doubling OSR increases peak SNR approximately by 9dB. The outcome is the same as shown in section 2.2.2. According to Table 3-1, we choose OSR >128 to meet our requirement.

Figure 3-5 Z-domain linear model by MATLAB simulation

OSR SNR ENOB

By replacing the ideal integrator by a leaky integrator due to the finite gain of the amplifier, we analyze the effect of leaky integrator and obtain the minimum requirement of the DC gain of the amplifier. We choose OSR to be 256 in this analysis.

The simulation result from SIMULINK is shown in Figure 3-6. It shows the obtained SNR versus the amplifier gains in the proposed structure. The minimum gain requirement for amplifier is 40dB to ensure over 70dB SNR of the first-order modulator. The gain requirement is only determined by the noise shaping consideration. If the distortion of the circuit should be taken into consideration, a higher amplifier gain should be achieved to ensure a better distortion performance.

Figure 3-6 SNR versus amplifier gain

3.2.3 SNR Prediction

In this section, we derive the mathematical equation to predict the SNR accurately. The derivation utilizes the linear model shown in Figure 3-7. The model includes the integrator leakage. This means that the factor β is less than 1. ∆Cis the capacitance change of the sensor, E is the quantization noise, and Y is the output of the modulator.

Figure 3-7 Linear model of the proposed structure

The signal transfer function is found to be

( )

¹ ¹

( )

The noise transfer function is given by

The quantization noise power is calculated as

( ) ( ) ( )

By equation (3.8) and (3.9), peak SNR of the first-order modulator is given by

( ) ( )

Figure 3-8 plots the SNR calculated by equation (3.10) and the SNR simulated by SIMULINK.

Figure 3-8 SNR versus input amplitude

The simulation results in Figure 3-8 show that the SNR of the first-order system degrades heavily. Since the results from the ideal equation do not include harmonics, the SNR decreases due to idle tones. This shows that the quantization noise is not white when the input is small.

3.3 The Second-Order Sigma-Delta Modulator

3.3.1 Circuit Architecture

In this section, a second-order sigma-delta modulator is introduced. A higher order structure can cancel the pattern noise of the first-order sigma-delta modulator and reduce the measurement time. Figure 3-9 shows the proposed second-order sigma-delta modulator. The second-order modulator is obtained by including a second stage which has the transfer function[17]

( )

⁴ ³ ⁴ ²

Figure 3-9 Proposed second-order sigma-delta modulator

In order to determine the coefficients of the second stage, we do the performance simulation by SIMULINK. The block diagram constructed in SIMULINK is shown in Figure 3-10. At the beginning of the simulation, we set the coefficient K₁ to be 1 and OSR to be 64. This is because the output of the second stage is connected to the quantizer. The gain of the second stage is not the key factor that affects the overall performance of the modulator. Table 3-2 shows the simulated result with coefficient

K2 varying from 0.1 to 0.9. According to table 3-2, the coefficient K₂ is set to be 0.6 to achieve the best performance of the modulator. The other coefficient K₁ will be adjusted according to the need of the circuit implementation.

Figure 3-10 Z-domain linear model by MATLAB simulation

K2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

SNR[dB] 46.05 52.55 59.84 65.17 69.91 70.16 69.41 66.57 60.57 Table 3-2 Coefficient K₂ versus SNR

3.3.2 Determine OSR and finite gain of the operational amplifier

The same step as in Section 3.2.2 is to choose an appropriate OSR for the second-order sigma-delta modulator. Our goal is to determine an OSR for the system to achieve 10-bit resolution. The analysis is done by the MATLAB simulation based on the z-domain linear model. We consider only the quantization noise shaping. By varying the different values of OSR of the system, the result in Table 3-3 is obtained.

We know that doubling OSR increases the peak SNR approximately by 15dB from Table 3-3. According to the simulation results, we choose OSR to be 64 to have 10-bit resolution. Table 3-3 OSR versus SNR and ENOB

Another important parameter we have to decide is the DC gain of the operational amplifier used in the modulator. We use the same way to analyze the minimum gain requirement of the amplifier. All ideal integrators are replaced by leakage integrators in our analysis. The OSR is set to be 64 for our analysis. Figure 3-11 shows the obtained SNR versus the gain. The minimum gain requirement is 30dB to ensure an peak SNR over 70dB.

Figure 3-11 SNR versus amplifier gain

3.3.3 SNR Prediction

The SNR versus input amplitude is plotted in Figure 3-12. The curve is obtained by SIMULINK. The full-scale of the input is from 0 to 300 fento Farad, and the feedback capacitor C_R is set to be 300 fento Farad. The peak SNR is measured approximately 71dB. When the input amplitude is large, the overload of the quantizer greatly degrades the SNR. Figure 3-13 shows the power spectrum of the second-order sigma-delta modulator when input amplitude is 200 fF.

Amplifier Gain[dB]

SNR[dB]

Figure 3-12 SNR versus input amplitude

Figure 3-13 Power spectrum

3.4 Tonal Behavior

3.4.1 Tonal behavior of first-order sigma-delta modulator

It is well understood that first-order sigma-delta modulators produces tones. In our analysis in SIMULINK, we obtain the three power spectrums shown in Figure

SNR[dB]

( )

∆C fF

3-14, 3-15, and 3-16. We know that idle tones becomes large when the input is small.

This kind of idle tone is input-dependent. This is because when the input amplitude is small, the quantization noise power spectrum is not white. The only way to solve this problem is to utilize a higher-order sigma-delta modulator. There are many factors that affecting the tonal behavior includes DC input level, initial condition of the loop filter, finite amplifier gain, and switch charge injection. In order to eliminate the tonal behavior, we should take all these parameters into considerations in our design.

Figure 3-14 When the input amplitude is 200fF

Figure 3-15 When the input amplitude is 50fF

Figure 3-16 When the input amplitude is 10fF

3.4.2 Tonal behavior of second-order sigma-delta modulator

As the analysis in first-order sigma-delta modulator, we obtain the power spectrum of different input amplitude in Figure 3-17, 3-18, and 3-19. The three figures shows that when the input becomes large, the overload effect of the comparator is obvious. The quantization noise is not white when the input amplitude is large, so the harmonic tones degrades the performance of the second-order sigma-delta drastically.

In our practical design, the phenomenon should be taken into considerations.

Figure 3-17 Input amplitude is 200fF

Figure 3-18 Input amplitude is 250fF

Figure 3-19 Input amplitude is 300fF

3.4.3 Methods for tone decorrelation

In this section, we discuss the methods for tone decorrelation. The methods are introduced as follows [5]:

1. Dithering: this method increases the noise floor but reduce the power of the harmonic tones.

2. Chaos: moving one or more noise transfer function zeros outside the unit circles.

3. Adding an out-of-band sine or square wave: it is typically common to use a frequency that is a submultiple of the oversampling clock.

4. Adding a DC offset to the input of the modulator: this pushes the idle channel noise spectral to higher frequencies outside the baseband.

5. Adding a small amount of random noise to the input: the small inherent thermal noise in an analog implementation will suffice as an appropriate dither.

6. Using analog sources of noise within the modulator: this technique has the potential of producing a result similar to that of noise-shape dither, but only if the

noise magnitude is sufficient and predictable in the actual hardware implementation.

7. Using high-order modulators: the quantization noise becomes white when the higher modulator is used.

All the methods described above are used to randomize the quantization noise. As long as the quantization noise is not white, the tonal behavior becomes obvious and degrades the SNR heavily. As the simulation results shown in section 3.4, the tonal behavior is more serious in the first-order modulator than in the second-order one.

The second-order modulator is adopted in our design in order to reduce the idle tones.

3.5 Summary

There are many system parameters which need to be determined in sigma-delta modulator, such as OSR, sampling clock, and DC gain of the amplifier. In Section 3.2, the oversampling ratio is determined to be 256, and DC gain of the amplifier should be larger than 40dB for the first-order sigma-delta modulator to achieve over 10-bit resolution. The OSR is set to be 64 for the second-order sigma-delta modulator, and the DC gain of the amplifier should be larger than 30 dB. By comparing the first-order and second-order modulators, the second-order modulator will consume less power than the first-order one due to the decrease of OSR. From Section 3.4, it shows that the tonal behavior of first-order sigma-delta modulator is more obvious than the second-order one. According to the analysis done by MATLAB, we decide to implement the second-order sigma-delta modulator proposed in section 3.3. The low voltage techniques for the design of the sigma-delta modulator will be introduced in Chapter 4.

Chapter 4 A 1.5 µ W Switched-Capacitor Sigma-Delta Modulator For Humidity Sensors

4.1 Introduction

In this chapter, the second-order sigma-delta modulator is implemented with low voltage low power techniques described in the following sections. We develop a design flow which is suitable for the design of the amplifier operating in weak inversion in Section 4.2. In Section 4.3, the basic blocks used for the modulator is presented, including a bias circuit, amplifier, and integrators. The design of a 1-bit quantizer is discussed in section 4.4. The structure of the non-overlapping clock generator is shown in section 4.5.

4.2 Circuits Design in Weak Inversion

4.2.1 Introduction to MOS Operating in Weak Inversion

In the past thirty years, the characteristics of MOS operating in weak inversion have been studied by many authors. It is well known that when the gate-to-source voltage of a MOS transistor is reduced below the threshold voltage defined in the strong inversion, the channel current decreases exponentially. There are many demands for the design of low power analog integrated circuits in recent years, such as pacemakers, hearing aids, and neural networks. In our system, the humidity sensor is used to detect the humidity in the living environment. So a long life time of battery is needed in our sensor system. The system presented in Chapter 3 is designed in weak inversion. A very simple model which is suitable for circuit design is discussed in next section.

Figure 4-1 Operating region of a MOS transistor

4.2.2 Simple Model in Weak Inversion

The simple model discussed in this section is based on the following assumptions[10].

1. The channel is sufficient long so that gradual channel approximation can be used and channel-length modulation is negligible.

2. Generation currents in the drain, channel, and source depletion regions are negligible; source and drain currents are then equal.

3. The density of fast surface states and the fluctuations of surface potential are negligible.

The equation of the drain current in weak inversion are derived as weak inversion

moderate inversion

strong inversion

GS th

V −V 20mV 80 200mV−

/ ( ( / ) / )

The upper limit of the drain current in weak inversion is _D 2 W _T2

I nK U

< L (4.3)

From equation (4.2), the transconductance, g_m, of MOS transistor in weak inversion is given by

The channel length modulation effect is essentially the same for MOS transistors in weak inversion and strong inversion. The output resistance, r_ds, is given by

ds 1

r ⁼λI ^, λ is the channel length modulation factor (4.5)

4.2.3 Design Flow of Low Power Operational Amplifiers

In order to simplify the design of operational amplifier operating in weak inversion, we must develop a useful design flow to determine the small-signal parameters given in the previous section. The design methodology we proposed in this section is based on g_m I_D method [14]. The methodology is suitable for the design of CMOS analog circuits operating in all regions of operation. It is especially suited for the design of low power analog circuits operating in weak inversion because it provides a good compromise between speed and power consumption. The g_m I_D method is chosen for the following three reasons.

1. It is strongly related to the performance of analog circuits.

2. It gives an indication of the device operating region.

3. It provides a tool for calculating the transistors dimensions.

Figure 4-2 shows the design flow of low power operational amplifiers. In the

design of operational amplifiers, the two parameters, transconductance and slew rate, are taken into considerations first. The transconductance of the input differential pair is obtained according to the requirement of unit-gain bandwidth. The output current is determined by the slew rate and output loading. According to the relation of g_m I_D and ID

(

W L

)

, we can determine the aspect ratio of each transistor with obtained transconductance and DC current. After choosing the aspect ratio of each transistor, take them into HSPICE simulation. Adjust the aspect ratio iteratively and make sure all the requirements are satisfied. Figure 4-3 is the plot of g_m I_D versus

( )

ID W L of n-MOS transistors, and Figure 4-4 is for p-MOS transistors.

Figure 4-2 Design flow

W L

Set DC bias point for suitable ICMR and output swing.

Figure 4-3 g_m I_D versus ^I_D

(

^{W L}

)

^{of NMOS}

W L

Figure 4-4 g_m I_D versus ID

(

W L

)

of PMOS

4.3 Implementation of Integrators

4.3.1 Low Voltage Low Power Operational Amplifier

The amplifier is the main building block of the sigma-delta modulator. It determines the total power consumption of the modulator. According to the comparison in [21], a single-stage amplifier is more power efficient than two-stage amplifier. So the current-mirror amplifier proposed in [21] is preferred, and all transistors are operated in weak inversion to meet the ultra low power requirement.

The minimum gain requirement for the amplifier is 40dB to ensure 10-bit resolution from Section 3.3.2. The architecture of the current mirror amplifier is shown in Figure 4-5. The B factor is the current gain from the diode-connected transistor to the transistor connected to the output node. Transistors M3a and M4a are added to enhance the DC gain without extra power consumption. The unit-gain bandwidth of the proposed topology is derived as

1 The above equation shows that unit-gain bandwidth will be multiplied by B. The DC gain of the current mirror amplifier is obtain by

(

¹¹ ³

)

The parameter k is between 0 and 1, and k should be appropriately determined to

m D

g I

maintain a safe phase margin. In our design, the current mirror amplifier has DC gain of 60dB and unit-gain bandwidth of 68 kHz. The simulation result in different corner is shown in Figure 4-6.

Figure 4-5 Proposed low power operational amplifier

Figure 4-6 Frequency response in different cases

4.3.2 Bias Circuit in Weak Inversion

The disadvantage of analog blocks operating in weak inversion is the high sensitivity to temperature variation. In order to reduce the effect of temperature variation, the bias circuit shown in Figure 4-7 generates a constant current, IREF, irrelative to temperature. The bias circuit is composed of a PTAT current source and a VEB referenced current source. The PTAT current source, I1, is formed by transistors M1, M2, M3, M4, and R1.The PTAT current source, I1, is given by

current source I₂ is given by

2 2

VEB

I = R . (4.9)

Since the temperature coefficient of I₁ is positive, and the temperature coefficient of I2 is negative, the reference current, I_REF , can be temperature independent by appropriately adjusting K₁ and K₂. The bias circuit consumes less power than many other bias circuits used for analog circuits operating in weak inversion. In our

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