Thesis Organization - 橫向擴散的射頻金氧半場效電晶體之特性分析與模型建立

Chapter 1 Introduction

1.5 Thesis Organization

The content in this thesis includes the following parts.

Chapter 1 introduces the LDMOS for RF applications and the motivation of this thesis.

Chapter 2 presents the DC, high-frequency and RF power performances of LDMOS with different layout structures. In addition, the small-signal model parameters were extracted to investigate their effects on fT and fmax.

In chapter 3, the DC, high-frequency and RF power performances of square LDMOS with various channel widths were analyzed. Also, the small-signal model parameters were extracted to investigate their effects on fT and fmax.

Chapter 4 presents the unusual capacitance behavior of RF LDMOS with fishbone, square and circle structures. Capacitance versus gate voltages with different drain voltage was investigated.

Chapter 5 presents the modified MM20 modeling for RF LDMOS.

Finally, the conclusions of this thesis are summarized in Chapter 6.

Chapter 2 Characterization of RF LDMOS with Different Layout Designs

2.1 Introduction

In high-power applications, the RF transistors are usually implemented in a “fishbone”

structure, as shown in Fig. 2.1(a). All the gate fingers are divided into several subcells, in each of which, 2-10 gate fingers are grouped together. For RF performance concern, multi-finger layouts are used to design wide MOSFETs for reducing the gate resistance and source/drain junction capacitance. Since the gate resistance would limit the power gain attainable at a certain frequency and thus fmax [14-18]. The drain resistance which includes accumulation layer resistance and JFET resistance are the main component in LDMOS to have influence on the on-resistance. Here, in order to achieve lower on-resistance, we adopted a “square”

structure which is different from the “fishbone” in the LDMOS layout design (see Fig. 2.1(b)).

However, in our previous study, we found that the square structure has higher gate capacitances compared to that of fishbone structure, owing to the corner effect [19]. In order to reduce the corner effect, we modified the square ring structures to octagon and circle rings (see Fig. 2.1(c)) in this work. Then we investigated the DC, high-frequency, and RF power characteristics of the devices with different layout structures.

2.2 Device Structures

RF LDMOS transistors were fabricated using a 0.5 μm LDMOS process. The schematic cross section of the device is shown in Fig. 2.2. The drain region was extended under the gate oxide and consisted of a lightly doped N-well drift region and an N^- region with higher doses for on-resistance control. The source region and the p-body were tied together to eliminate extra surface bond wires to reduce the source inductance and improve the RF performance in a power amplifier configuration [20]. The gate oxide thickness was 135 Å and the mask

channel length (LCH) was 0.5μm. The drift length (LDrift=LOV+LFOX) was 2.4μm. The fishbone structure used in this study had 10 cells which each cell had 4 fingers with finger width LF=10μm. For the other structures, the width of each gate ring was 40μm and each cell was arranged as a 5x2 array in one device. The source region was surrounded by the drain region, while the gate was located between the source and the drain (see Fig. 2.1). To compare the performance of all structures fairly, the total channel width is the same (W= 400μm).

2.2.1 DC Characteristics

The I–V characteristics of the LDMOS with different layout structures are shown in Fig.

2.3. For ring structures, the circle device shows the highest drain current and transconductance than others, and the square device shows the worst performance. Because the square structure has additional four corners, where the drain current density is lower than that in edges, the effective drain resistance would be higher than that in octagon and circle structures. It results a lower drain current compared to that in other structures. The dc characteristics of fishbone device are also shown in Fig. 2.3. The drain current and transconductance are not lower than the ring structures in low- and medium-bias regions, but in high-bias region the drain current would be suppressed more due to the quasi-saturation effect. Because the fishbone structure has higher resistance in the drift region, a larger voltage drop in drift region will exist than that of ring structures. As a result, the carriers in the drift region of the fishbone device will enter the velocity saturation earlier than ring structures.

When the velocity saturation in the drift region occurs, the device will operate in

“quasi-saturation”, where the intrinsic MOS is still in linear operation. This effect is generally observed at high gate voltages. As the device enter the quasi-saturation, the gate control ability decreases which limits the drain current level and delays the transition between linear and saturation regime. So when the device operates at high power condition, the ring structure has a better performance due to reduced quasi-saturation effect.

From the output I–V characteristics of the fishbone structure, we observe a negative output resistance in the high-current region. With high current density in the transistor, the rise in device temperature resulted from the dissipated power becomes significant. The increased device temperature reduces the carrier mobility and saturation velocity [21]. Fig. 2.4 shows the thermal resistance (Rth) of three different layout structures. The fishbone device has higher thermal resistance compared to ring devices. Due to compact layout area, the self-heating effect in the fishbone structure is significant. The device self-heating can be improved by increasing the distance between each cell of fishbone.

The drain-source on-resistance is an important parameter for describing the performance of LDMOS transistors. The on-resistance (Ron) is extracted from the linear forward I–V characteristics at gate voltage VGS = 2.5 V, since it is predominated by the drift region under such a condition (see Table 2-1). Ron is related to the drain current and is dependent on the drain resistance. Among the ring structures, the Ron is lowest in the circle device, and it is interpreted as being due to a lowest drain resistance, In Table 2-1, we also observe that the Ron in fishbone device is lower than that in ring devices due to lower channel resistance. This result is limited by standard processing. In addition, another important parameter is breakdown voltage for LDMOS. We obtain that the four devices have the similar breakdown voltage (VBD≅ 41-43V).

2.2.2 High-frequency Characteristics

To characterize the high-frequency performance, the S-parameters were measured on-wafer from 0.1 to 30 GHz using an HP8510 network analyzer and then de-embedded by subtracting the OPEN dummy. Fig. 2.5 shows the high-frequency characteristics of circle structure. The maximum stable gain/maximum available gain (MSG/MAG) and short-circuit current gain (h21) were calculated from S parameters. The cutoff frequency (fT) and maximum oscillation frequency (fmax) were determined as the frequency where the current gain was 0 dB

and the frequency where MAG was 0 dB, respectively. The transistors were measured at drain voltage VDS=20 V with different gate voltages. From Fig. 2.6, fT had maximum values at VGS=2.5 V, where the transconductance showed a peak. With increasing the gate voltage, both fT and fmax decreased owing to the mobility degradation and quasi-saturation effects.

The cutoff frequency and maximum oscillation frequency for the LDMOS with different layout structures are compared in Fig. 2.6. The transistors were biased at VGS=2.5 V and VDS=20 V to obtain the maximum value of fT. It is observed that the values of fT in these layout structures are circle > octagon > square > fishbone and the values of fmax are square >

circle > octagon > fishbone.

By analyzing a MOSFET small-signal equivalent circuit, we can determine the effect of device parameters on high-frequency characteristics more clearly. We adopted a simple model (shown in Fig. 2.7) and extracted the equivalent circuit parameters of the LDMOS by the method described in ref. 22. After de-embedding the extrinsic parasitic resistances and the substrate-related parameters, the intrinsic components could be directly extracted from intrinsic Y-parameters (Yi) by the following equations [23]:

,12

Using extracted parameters from the existing device and altering one parameter at the time, the effect of model parameters on the cutoff frequency and maximum oscillation frequency can be visualized. The influences of model parameters on fT and fmax are shown in Fig. 2.8. The x-axis showed the parameter value departure from the initial value in percent.

The y-axis showed the change in frequency in percent. Parameters not shown in the figure had approximately the same value for the ring and fishbone structures or had a minor influence on fT and fmax. As shown in Fig. 2.8(a), the intrinsic transconductance (gm), gate-source capacitance (Cgs) and gate-drain capacitance (Cgd) have large effect on fT. The cutoff frequency can be expressed in a simple way of fT = gm/ 2π (Cgs+ Cgd) which is related to the gm and input intrinsic capacitances (Cin= Cgs+ Cgd). The extracted model parameters that affect the fT more significantly are listed in Table 2-2. For ring structures, we find that the slight increase of fT in circle device is mainly due to the slight increase of gm. When gm increases from 34.58 mA/V to 35.92 mA/V and 36.7 mA/V for octagon and circle respectively contrasting with square structure, fT is improved by about 3.7% and 5.9% (see Table 2-3). The gate capacitances are nearly unchanged. For fishbone device, however, the drain resistance (Rd) is large and its effect on fT cannot be ignored. Rd represents the drain contact resistance and part of the drift region. As compared to square device, Rd has been increased from 2.6 Ω to 9.05 Ω for fishbone device, and thus fT becomes worse about -3.9%. In addition, the lower Cgd and higher Cgs in the fishbone structure cause about 3.7% and -7.2% changes in fT due to different layout design. Otherwise the intrinsic gm of fishbone is the biggest among four structures and makes fT increase about 6.5%. As illustrated in Fig. 2.8(b), in addition to the intrinsic parameters, the Rd, gate resistance (Rg), drain-source capacitance (Cds) and drain-substrate junction capacitance (Cjdb) have apparent effects on fmax [24]. The extracted model parameters that affect fmax more significantly are listed in Table 2-4. The square structure has the highest fmax due to lower parasitic drain junction capacitance (Cjdb) and gate to source capacitance (Cgs). The Cjdb can be separated into two parts; one is between P-body

and DNW, another is between DNW and substrate (see Fig. 2.9), and then the Cjdb is relative to area of DNW. Because the square structure has small area, the DNW area and thus the Cjdb

are small (see Table 2-6). Contrary to square, the fishbone structure has the lowest fmax due to higher Rd and Cgs in addition to lower fT. Comparing to the square structure, the octagon and circle structures have lower fmax due to larger Cjdb and drain to source capacitance (Cds).A part element of Cds represents the overlap of metal conducting wires. Although fmax should be improved with the gm increasing, the other parameters will also affect the fmax. For ring structures, the Cds increases from 97.62 fF to 119.9 fF and 119.8 fF for octagon and circle respectively contrasting with square structure, both fmax become worse about -2.9% (see Table 2-5). In addition, the Cjdb increase from 52.13 fF to 129.9 fF and 132.3 fF, the fmax also become worse about -7.6% and -7.8%. For fishbone structure, we are easy to find the Rd has a great impact on fmax and becomes important. As compared to square device, Rd has been increased from 2.6 Ω to 9.05 Ω for fishbone device, and thus fmax becomes worse about -23.8%. In addition, the lower Cgd and higher Cgs in the fishbone structure cause about 8.6%

and -6.9% changes in fmax due to different layout design. Otherwise the extrinsic parameters (Rg and Cds) also make fmax increase about 5.7% and 6.8% respectively. Consequently, the fmax

for circle structure is lower than the one for square structure by about -3.5% (fmax was 14.74 GHz for the square structure and 14.22 GHz for the circle structure). The fmax for octagon structure is lower than the one for square structure by about -10.7% (fmax was 14.74 GHz for the square structure and 13.16 GHz for the circle structure). The fmax for fishbone structure is lower than the one for square structure by about -11.2% (fmax was 14.74 GHz for the square structure and 13.09 GHz for the fishbone structure).

2.2.3 RF Power and Linearity

As well as the high-frequency characteristics, the microwave power characteristics are also investigated using the load-pull measurement. In our study, the source and load

impedances were tuned for maximum power gain and maximum output power, respectively.

The power tune is setup at 2 dBm before the power gain starts to degrade. For having the value of fmax in the range from 13 GHz to 15 GHz, the devices were measured at 1.8 GHz with gate bias VGS=2.5 V and drain bias VDS=20 V. Figure 2.10 shows the output power, power gain and power added efficiency (PAE) with different layout designs. There are only three layout structures of LDMOS: fishbone, square and circle, because the octagon structure is similar to circle structure.

The power gain is related to fmax. The square device has largest power gain and the fishbone device has smallest power gain (see Fig. 2.10). We find that the power gain of square structure degrades earlier than others when input power goes beyond 1-dB compression point (P1dB). The main reason for gain compression is attributed to the clipping effect. The border of output I-V curve will cause output waveform to be clipped for MESFET, PHEMT and HBT [25-27]. The clipping effect can also been found in LDMOS. Figure 2.11 shows the drain current versus gate voltage with input and output waveform for different layout designs. Part of the AC-signals on the drain current would be cut off as the input power becomes larger enough. At this condition, the average drain current increased with the increasing input power (see Fig. 2.12) and the power gain has been compressed. This is because the dynamic load line exceeds the border of DC I-V. For the square structure, the drain current makes the negative duty cycle of output waveform enter the cutoff region earlier. This indicates that the average drain current started to increase earlier (see Fig. 2.12) and the gain compression occurs prior. And another two structures have the similar characteristics that the gain compression occurs lately. Generally the device operating range is before P1dB point, so the circle has wider operating range than square. Consequently, although the square structure shows higher value of output power, power gain and PAE, the operating range is narrower slightly. Since the DC behaviors were changed, the linearity would also be affected with different layout designs. The input and output third-order intercept points (IIP3 and OIP3) for

three structures are listed in Table 2-7. As measuring IM3, the output impedance is tuned at maximum gain. The IIP3 and OIP3 are different in three structures due to different load impedance (as shown in Fig. 2.13).

2.3 Summary

LDMOS with different structures for RF applications are investigated. The ring structure has a better performance than the fishbone structure, without altering the process flow. The quasi-saturation effect is suppressed in the LDMOS with the ring structure due to lower drain parasitic resistance. In addition, the fT and fmax are also enhanced for the ring structure due to the lower drain parasitic resistance. The distance of each cell for ring structure can be reduced to improve RF performance because the self-heating effect for ring device is smaller than one for fishbone device. The circle device can improve the disadvantage of square device on DC performance due to uniform current density that reduces the drain resistance. Although the square structure shows higher value of output power, power gain and PAE, the operating range and linearity are worse than circle. Our results suggested that, using a circle structure, both better DC and RF characteristics can be achieved.

Table 2-1 Extracted Ron and VBD for four different layout structures.

Ron (Ω-㎜) VBD (V) Fishbone 22.95 41

Square 24.59 42 Octagon 23.57 43

Circle 23.05 41

Table 2-2 Extracted gm, Rd Cgd and Cgs to see their effects on fT for different layout structures.

gm (mA/V) Rd (Ω) Cgd (fF) Cgs (fF) fT (GHz) Fishbone 36.9 9.05 147.2 1080 4.67

Square 34.58 2.6 185.4 986 4.71 Octagon 35.92 2.48 193.4 998.2 4.81

Circle 36.7 2.2 194.6 1013 4.87

Table 2-3 Individual effects of the model parameters on fT. The square device is as a reference.

gm Rd Cgd Cgs

Fishbone 6.5 -3.9 3.7 -7.2

Octagon 3.7 0.1 -0.7 -1.1

Circle

fT Difference

(%) 5.9 0.2 -0.9 -2.2

Table 2-4 Extracted Rg, Rd, Cgd, Cgs, Cds and Cjdb to see their effects on fmax for different layout structures.

Rg (Ω)

Rd (Ω)

Cgd (fF)

Cgs (fF)

Cds (fF)

Cjdb

(fF)

fmax

(GHz) Fishbone 1.91 9.05 147.2 1080 53.97 39.87 13.09

Square 2.43 2.6 185.4 986 97.62 52.13 14.74 Octagon 2.48 2.48 193.4 998.2 119.9 129.9 13.16

Circle 2.71 2.2 194.6 1013 119.8 132.3 14.22

Table 2-5 Individual effects of the model parameters on fmax. The square device is as a reference.

gm Rg Rd Cgd Cgs Cds Cjdb

Fishbone 5.9 5.7 -23.8 8.6 -6.9 6.8 2.5

Octagon 3.4 -0.7 0.8 -1.8 -1 -2.9 -7.6

Circle

fmax

Difference

(%) 5.4 -2.9 3 -2 -2.1 -2.9 -7.8

Table 2-6 Cjdb and DNW area for four different layout structures.

Cjdb (fF) DNW area (um²)

Fishbone 39.87 8617.1

Square 52.13 8867.4

Octagon 129.9 10145.4

Circle 132.3 10570.3

Table 2-7 IIP3 and OIP3 for four different layout structures.

IIP3 (dBm) OIP3 (dBm)

Fishbone 15.04 31.03 Square 12.92 30.58

Circle 15.52 32.38

(a) (b) (c)

Fig. 2.1 LDMOS layout structures: (a) fishbone, (b) square and (c) circle.

Fig. 2.2 Schematic cross section of an LDMOS transistor.

(a)

Fig. 2.3 (a) Subthreshold and (b) output characteristics of LDMOS transistors with different layout designs.

0.0 0.2 0.4 0.6 0.8 1.0 0

10 20 30 40 50 60 70

R_TH=55.59

(

^oC/W

)

Fig. 2.4 RTH of LDMOS transistors with different layout design.

R_TH=54.81

(

^oC/W

)

R_TH=78.81

(

^oC/W

)

V_DS=20V V_GS=3.5V

T_C= 25+R_THP_D

Fishbone Square Circle

Tc-Ta (o C)

Power Dissipation (W)

(a)

Fig. 2.5 Dependence of (a) |h21| and (b) MSG/MAG on frequency obtained from S-parameter measurements.

1.5 2.0 2.5 3.0 3.5

Fig. 2.6 (a) fT and (b) fmax versus gate voltage with different layout design.

R

C

_gs

R

sub

R

=1/g

_ds

C

sub

C

jdb

g

V

G D

S

exp( )

m m

g = g − j ωτ

Vgs

+ _

Fig. 2.7 A simple equivalent circuit model of the LDMOS.

-50 -40 -30 -20 -10 0 10 20 30 40 50

Fig. 2.9 The drain to body junction capacitance

-20 -15 -10 -5 0 5 10 -5

0 5 10 15 20 25

Output Power (dBm) & Power Gain (dB)

Input Power (dBm)

Fishbone Square Circle Gain

P_out

PAE V_GS = 2.5V, V_DS = 20V

freq = 1.8GHz

PAE (%)

Fig. 2.10 Output power, power gain and PAE versus input power with different layout designs.

Fig. 2.11 Drain current versus gate voltage with different layout designs. The input signal was biased at VGS=2.5V and the negative duty cycle of output signal was clipped by the cutoff region.

-20 -15 -10 -5 0 5 10

Fig. 2.12 Average drain current as a function of the input power with different layout designs.

-20 -15 -10 -5 0 5 10 15 20

Fig. 2.13 Output power and third-order intermodulation power versus input power with different layout designs.

Chapter 3 Characterization of RF LDMOS with Different Channel Widths

3.1 Introduction

The corner effect of square structure is described in chapter 2. Under fixing the drift length, we studied the corner effect by changing the channel width of a cell. Different ratios of corner areas to edge area would result in different drain parasitic resistances and capacitances [19].

Square structures with different channel widths for DC, high-frequency, and RF power characteristics are investigated.

3.2 RF LDMOS with Square Structure

The square device used in this study had different channel widths per a cell (Wch=20μm, 40μm and 100μm). For making a fair comparison, these devices had the same total channel width (W=400μm). Therefore, the cells in the these devices were arranged as 10x2, 5x2 and 2x2 arrays, respectively. These devices are named as “square_20x20”, “square_10x40” and

“square_4x100”, respectively.

3.2.1 DC Characteristics

Fig. 3.1 shows the I–V characteristics of the LDMOS with different channel widths. The device with larger Wch shows a lower drain current and transconductance. Also with a larger Wch, the higher resistance in the drift region leads to the quasi-saturation effect occurs earlier.

The extracted on-resistance and breakdown voltage with various channel widths per a cell are shown in Table 3-1. The Ron is extracted from the linear forward I-V characteristics at gate voltage VGS=2.5 V and normalized to the total width. As indicated in Table 3-1, the devices with different channel widths have similar breakdown voltage. In addition, we find that, as the

channel width increases, the Ron increases due to the increase of drain series resistance. By fixing the drift length, the ratio of corner area to side area will be reduced with increasing Wch. Therefore, the device with large Wch has smaller equivalent drift width compared to the device with small Wch, leading to higher drain resistance.

From the output I–V characteristics, we observe a negative output resistance in the high-current region. With high current density in the transistor, the rise in device temperature

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