Results and Discussion

The model parameters of fishbone and circle devices were extracted from their I-V and C-V curves. The measured and simulated I-V curves are shown in Figs. 5.5 and 5.6. The simulated results show excellent consistency with the measured data for two structures except at high drain voltages. At high drain voltages, the drain current is influenced by self-heating and weak avalanche effects, which have been ignored in our model. Fig. 5.7 shows the simulated and measured Cgs+ Cgb and Cgd versus gate voltage with different drain voltages.

The simulated capacitance characteristics also show consistency with the measured data for two structures. Some extracted model parameters are listed in Table 5-1. For circle structure, the electron mobility in the drift region (μdr) is larger than fishbone structure due to lower drain parasitic resistance. The parameter Rdr in the circle structure is lower and enhances the drift region current. In the chapter 2, we also know the fishbone structure having high RD

which is extracted from small signal circuit model causes to the device enter the quasi-saturation earlier. In addition, the θ3dr is similar because effective drift length (Ldr)is longer for circle structure. From the C-V curves, we find that the flat band voltage occurs at

VG= -1.7~-2V and is smaller for circle structure. This is similar as the extracted model parameter VFB. Mover, the electron mobility in the channel region (μch) is lager for fishbone structure due to lower channel resistance. So, the fishbone device has larger transconductor and these performances are agreement with chapter 2.

5.5 Summary

The device models have been obtained for fishbone and circle structures by using the modified MM20. The quasi-saturation effect dominated in the drift region is also considered.

From I-V and capacitance characteristics, this model shows an accurate description in all operating regimes, and provides a good agreement between simulated and measured data. In addition, we confirm the device enters the quasi-saturation earlier due to higher drain parasitic resistance and the drain parasitic resistance is lower for circle structure. Consequently, the extracted model parameters have been analyzed and present the similar information as chapter 2.

Table 5-1 Extracted VFB, μch, μdr, θ3dr, Rdr and LD from modified MM20 for different layout structures.

VFB μch μdr θ3dr Rdr LD

Fishbone -1.832 194.6m 694.2u 330m 86.54 270n Circle -1.85 181.5m 782.7u 332.6m 76.31 280n

Fig. 5.1 The right figure shows the space charge distribution of LDMOS at Vg= 2.5V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

Fig. 5.2 The right figure shows the space charge distribution of LDMOS at Vg= 10V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

Fig. 5.3 The right figure shows the space charge distribution of LDMOS at Vg= 2.5V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

Fig. 5.4 The right figure shows the space charge distribution of LDMOS at Vg= 10V and Vd= 10V and the left figure shows the electric field along the channel region to drift region.

(a)

Fig. 5.5 Measured (mark) and simulated (line) drain current IDS versus gate voltage at different drain biases for the (a) fishbone and (b) circle structures.

0 5 10 15 20 25 30 35

Fig. 5.6 Measured (mark) and simulated (line) drain current IDS versus drain voltage at different gate biases for the (a) fishbone and (b) circle structures.

-4 -2 0 2 4 6

Fig. 5.7 Measured (mark) and simulated (line) CGS+CGB and CGD versus gate voltage at different drain biases for the (a) fishbone and (b) circle structures.

Chapter 6

Conclusions and Suggestion

6.1 Conclusion

We have investigated the DC, AC, high-frequency, RF power characteristics and DC model of LDMOS transistors with different layout designs. Based on the same distance of each cell, we find that the cutoff frequency, maximum oscillation frequency and power performance were improved using the ring structures. In the traditional design, the ring (also called enclosed, edgeless, or donut in other literatures) structures were used to lower the parasitic capacitances for more linear and faster devices [43-44]. For MOSFET, the conventional parasitic drain capacitance refers to the n+ drain to p-substrate junction capacitance. Hence, the drain was always surrounded by the transistor channel and source to reduce the area. In LDMOS, however, the parasitic drain capacitance refers to the deep n-well (DNW) to p-substrate junction capacitance. Therefore, drain outside or inside for ring structure has no impact on drain capacitance. Since larger area for output terminal could reduce the parasitic drain resistance, ring structures with drain outside layout would be the better choice for the LDMOS. This layout design can improve the performance without altering the process flow. In addition, we also find that the transconductance, on-resistance, cutoff frequency and linearity were improved except maximum oscillation frequency and power performance by using the circle structure. It is obvious that the circle structure success to compress the corner effect in the square structure and improve the DC performance. Finally, the modified MM20 shows an accurate description on DC and capacitance characteristics.

And the results are agreement with above descriptions.

In chapter 2 fishbone, square, octagon and circle structure were investigated. Fishbone and ring structures were compared. The fishbone structure has better on-resistance and

linearity due to lower channel resistance but it has larger RTH. The RF performance like fT, fmax and power were improved for the ring structures due to the lower drain parasitic resistance. If reducing the distance of each cell in the ring structure, the RF performance will be enhanced much due to decrease the parasitic capacitance and maintain the same DC performance as fishbone. In addition, square and circle structures were also compared. The DC performance like drain current and transconductance were enhanced for the circle structure due to lower drain parasitic resistance and uniform drain current density contributed by canceling the corner of drift region.

In chapter 3 square devices with various channel width were investigated. The device with larger Wch has better fT, fmax, RF power and linearity due to lower drain parasitic capacitance, but it also has larger on-resistance due to larger drain parasitic resistance. It shows a trade-off between the DC performance and the RF performance.

Capacitance characteristics were analyzed completely in chapter 4. For having a non-uniform doping channel, CGD exhibits a peak at the threshold voltage. For existence of the drift region, CGS+ CGB and CGD show a peak at the onset of quasi-saturation. In the square structure, the second peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. Moreover, the circle structure only has the first peaks in a capacitance-voltage curve just like as fishbone.

In chapter 5 the modified MM20 is used to simulate the LDMOS with different layout design. This model provides an accurate description in all operating regimes, ranging from subthreshold to superthreshold, in both the linear and saturation regime and includes physical effects like mobility reduction, velocity saturation, drain-induced barrier lowering, static feedback and channel length modulation. A comparison with DC and capacitance measurements on LDMOS device shows a very good agreement. In addition, the extracted model parameters have been analyzed and show an agreement with chapter 2.

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