High-frequency Characteristics

The dependences of the cutoff frequency and maximum oscillation frequency on the channel width for the LDMOS are compared in Fig. 3.3. The transistors are biased at VGS=2.5 V and VDS=20 V to obtain the maximum value of fT. It is obvious that fT and fmax both decrease with decreasing Wch due to lower parasitic capacitance. On the other word, the both values of fT and fmax in these layout devices are square_4x100 > square_10x40 >

square_20x20.

By analyzing a MOSFET small-signal equivalent circuit, we can determine the effect of device parameters on high-frequency characteristics more clearly. Using extracted parameters from the existing device and altering one parameter at the time, the effect of model parameters on the cutoff frequency and maximum oscillation frequency can be visualized.

The influences of model parameters on fT and fmax are shown in Fig. 3.4. The x-axis showed the parameter value departure from the initial value in percent. The y-axis showed the change in frequency in percent. Parameters not shown in the figure had approximately the same value for the square structures or had a minor influence on fT and fmax. As shown in Fig. 3.4(a), the

intrinsic transconductance (gm), gate-source capacitance (Cgs) and gate-drain capacitance (Cgd) have large effect on fT. The cutoff frequency can be expressed in a simple way of fT = gm/ 2π (Cgs+ Cgd) which is related to the gm and input intrinsic capacitances (Cin= Cgs+ Cgd). The extracted model parameters that affect the fT more significantly are listed in Table 3-2.

According to above equation, we know that the fT is proportional to gm,but the measured data we obtained is reverse proportional to gm. So we confirm that the fT is relative to Cin and Cin

increases with increasing the extra area of drift region. In addition, the fmax has the similar appearance. Comparing to square_10x40, as Cgd is changed from 185.4 fF to 275.7fF and 130.4 fF for square_20x20 and square_4x100, fT vary about -7.6% and 5.4% respectively (see Table 3-3). Similarly, Cgs is also changed from 986 fF to 971 fF and 994 fF for square_20x20 and square_4x100 and makes fT about 1.3% and -0.7% changes respectively. Therefore, it is obvious that the Cgd has a great effect on fT for these devices. The increasing area of drift region led to Cgd rise, and decreasing area of source led to Cgs reduce for square device. As illustrated in Fig. 3.4(b), in addition to the intrinsic parameters, the Rd, gate resistance (Rg), drain-source capacitance (Cds) and drain-substrate junction capacitance (Cjdb) have apparent effects on fmax. The extracted model parameters that affect fmax more significantly are listed in Table 3-4. The transistor has larger value of fmax with increasing channel width due to smaller Cds and Cgd. The former is relative to the overlapped area of metal conducting wires and the later is relative to the drift region area. In addition, one reason results the lowest fmax for square_20x20 is larger Cjdb. The value of Cjdb is relative to the DNW area and device area.

Comparing to square_10x40, Cgd varies from 185.4 fF to 275.7 fF and 130.4 fF for the square_20x20 and square_4x100, and make fmax about -17.1% and 12.4% changes respectively (see Table 3-5). Another parameter affects fmax more is Cds. As Cds is changed from 97.62 fF to 149.9 fF and 58.32 fF for the square_20x20 and square_4x100, the fmax vary about -6.3% and 6.1% respectively. In addition, the square_20x20 and square_4x100 both have smaller Rg and cause fmax about 8.4% and 7% changes due to different cell arrangement.

The Rd also has a little effect and makes fmax about 4.7% and -5.9% changes for the square_20x20 and square_4x100. Otherwise, the larger Cjdb just in square_20x20 decreases fmax about -8.6% contrasting with square_10x40. Consequently, Comparing to square_10x40, using the square_20x20, we estimate that fmax become worse by about -16.1% (fmax was 12.37 GHz for the square_20x20 and 14.74 GHz for the square_10x40) and using the square_4x100, we estimated that fmax become better by about 6.4% (fmax was 15.68 GHz for the square_4x100 and 14.74 GHz for the square_10x40). Therefore, Cgd is the key factor for improving fT and fmax by using the square structure.

3.2.3 RF Power and Linearity

The load-pull measurement uses the same setup as chapter 2. Figure 3.5 shows the output power, power gain and power added efficiency (PAE) for square device with different channel widths. The power gain characteristic is related to fmax. The transistor with llarge Wch has larger power gain and out power but they degrade earlier when input power was larger than 1-dB compression point (P1db) (see Fig. 3.5). The main reason for gain compression is attributed to the clipping effect that is explained in chapter 2. As the channel width increase, the lower drain current makes the negative duty cycle of output waveform enter the cutoff region earlier (see Fig. 3.6). This indicates that the average drain current started to increase earlier (see Fig. 3.7) and the gain compression occurs prior. The transistor with large channel width has wider operating range that is before P1dB point. Consequently, although the square device with large channel width shows higher value of output power, power gain and PAE, the operating range is narrow slightly. Since the DC behaviors were changed, the linearity would also be affected with various channel widths. The input and output third-order intercept points (IIP3 and OIP3) for three channel widths are listed in Table 3-6. The IIP3 and OIP3 are similar for different channel widths (as shown in Fig. 3.8).

3.3 Summary

The square devices with various channel widths for RF applications are investigated. The transistor with large W^ch has better fT, fmax, and RF power due to lower drain parasitic capacitance, but it also has larger on-resistance and narrower operating range due to larger drain parasitic resistance. It shows a trade-off between the DC performance and the RF performance. In addition, the area of square device with large W^ch is smaller than one with small W^ch, leading to more serious self-heating effect. It also shows a trade-off between the area of device and the self-heating effect.

Table 3-1 Extracted Ron and VBD for square device with different channel widths.

Ron (Ω-㎜) VBD (V) Square_20x20 23.75 41 Square_10x40 24.59 42 Square_4x100 25.14 42

Table 3-2 Extracted gm, Rd Cgd and Cgs to see their effects on fT for square device with different channel widths.

gm (mA/V) Rd (Ω) Cgd (fF) Cgs (fF) fT (GHz)

Square_20x20 34.97 1.97 275.7 971 4.47

Square_10x40 34.58 2.6 185.4 986 4.71

Square_4x100 34.1 3.58 130.4 994 4.86

Table 3-3 Individual effects of the model parameters on fT. The square_10x40 is as a reference.

gm Rd Cgd Cgs

Square_20x20 1.1 0.4 -7.6 1.3

Square_4x100

fT Difference

(%) -1.3 -0.7 5.4 -0.7

Table 3-4 Extracted Rg, Rd, Cgd, Cgs, Cds and Cjdb to see their effects on fmax for square device with different channel widths.

Rg (Ω)

Rd (Ω)

Cgd (fF)

Cgs (fF)

Cds (fF)

Cjdb

(fF)

fmax

(GHz)

Square_20x20 1.69 1.97 275.7 971 149.9 149.3 12.37

Square_10x40 2.43 2.6 185.4 986 97.62 52.13 14.74

Square_4x100 1.8 3.58 130.4 994 58.32 42.86 15.68

Table 3-5 Individual effects of the model parameters on fmax. The square_10x40 is as a reference.

gm Rg Rd Cgd Cgs Cds Cjdb

Square_20x20 0.9 8.4 4.7 -17.1 1.2 -6.3 -8.6

Square_4x100

fmax Difference

(%) -1.2 7 -5.9 12.4 -0.7 6.1 1.8

Table 3-6 IIP3 and OIP3 for square device with different channel widths.

IIP3 (dBm) OIP3 (dBm) Square_10x40 15.78 30.24 Square_20x20 16.43 33.14 Square_4x100 24.18 41.35

0 1 2 3 4

Fig. 3.1 (a) Subthreshold and (b) output characteristics of LDMOS transistors with different channel widths.

0.0 0.2 0.4 0.6 0.8 1.0 0

10 20 30 40 50 60 70

Fig. 3.2 RTH of LDMOS transistors for square structure with different channel widths.

R_TH=54.81 (^oC/W)

R_TH=56.28 (^oC/W)

R_TH=49.47 (^oC/W) T_C= 25+R_THP_D

V_DS=20V V_GS=3.5V

Square_20x20 Square_10x40 Square_4x100

Tc-Ta (o C)

Power Dissipation (W)

1.5 2.0 2.5 3.0 3.5

Fig. 3.3 (a) fT and (b) fmax versus gate voltage for square structure with different channel widths.

-50 -40 -30 -20 -10 0 10 20 30 40 50

-20 -15 -10 -5 0 5 10

Output Power (dBm) & Power Gain (dB)

Input Power (dBm)

Fig. 3.5 Output power, power gain and PAE versus input power with different channel widths.

Fig. 3.6 Drain current versus gate voltage with different channel widths. The input signal was biased at VGS=2.5V and the negative duty cycle of output signal was clipped by the cutoff region.

-20 -15 -10 -5 0 5 10

Fig. 3.7 Average drain current as a function of the input power with different channel widths.

-20 -15 -10 -5 0 5 10 15 20

Fig. 3.8 Output power and third-order intermodulation power versus input power with different channel widths.

Chapter 4

Capacitance Characteristics of RF LDMOS with Different Layout Designs

4.1 Introduction

Because the device capacitances influence the input, output and feedback capacitances, which are important in the dynamic operation, and have large impact on device high-frequency performance, the capacitance characterization and modeling of LDMOS transistors have been studied widely [28]-[31]. As compared to the conventional MOSFET, a non-uniform doping channel and a drift region in LDMOS result in the unusual behavior in capacitances [32]-[33]. And the characteristics of ring structure are different from traditional RF LDMOS (fishbone). Therefore we are interested to know the effect of layout design on the capacitance characteristics of LDMOS transistors.

4.2 Capacitances versus V_GS for Fishbone LDMOS

The capacitances we analyzed in this chapter were extracted form the S-parameters.

Using an HP8510 network analyzer, S-parameters were measured on-wafer from 0.1 to 5GHz for different temperatures and then de-embedded by subtracting the OPEN dummy. Different control biases were applied from an HP4142B source measure unit to sweep from accumulation to strong inversion. The gate-to-source/body capacitance (CGS+ CGB) and gate-to-drain capacitance (CGD) and drain-to- gate capacitance (CDG) has been extracted from the de-embedded S-parameters at low frequency range by the formula described in chapter 2.

In order to improve the RF performance, the source and P-body have been tied together to the RF ground. Therefore, the extracted gate-to-source capacitance (CGS) and gate-to-body

capacitance (CGB) cannot be separated.

For fishbone structure, the extracted CGS+ CGB and CGD as functions of gate voltage (VGS) for drain voltage VDS=0.1, 1, 5, 10 and 20V at room temperature are shown in Fig. 4.1. At low drain bias (VDS=0.1 V), the CGS+ CGB presents a similar behavior to the conventional MOSFET. For the lateral non-uniformly doped channel in LDMOS, the doping concentration was lower at the drain side than the source side. Hence, the drain end will be inverted prior to the source end, resulting in a peak in CGD [31]. As the drain end was inverted, the accumulation electron charge sheet in N-type drift region will cause CGD to increase as gate voltage (VGS) increases. Once the VGS exceeds the threshold voltage (i.e. source end was inverted), the CGD starts to fall as the electron charge sheet is no longer connected only to the drain.

By increasing the drain voltage (VDS>1 V), both CGS+CGB and CGD present peaks.

Because the inversion charges may be injected from the intrinsic MOSFET to the depleted area of the drift, the CGD and CGS+CGB increase with increasing gate voltages and the CGS+CGB even rises over the limit of inversion [29]. In LDMOS, existed drift region resulting in the effect of quasi-saturation. Before the device entered the quasi-saturation regime, the drain side channel voltage (Vch) increased as the VGS increased just like in the conventional MOSFET. Then, Vch decreased as the VGS increased after the device enters the quasi-saturation regime [34]. Therefore, the CGS+CGB could exceed the value of total gate oxide capacitance due to change in surface potential in the drift goes negative where the change in gate voltage was still positive [35]. In the quasi-saturation regime, the surface potential variation becomes small gradually leads to the fall of the CGS+CGB and CGD. Accordingly, the CGS+CGB and CGD reach maximum at the onset of quasi-saturation. In Fig.

4.1, the corresponding drain currents at drain voltages VDS=1, 10 and 20 V were also presented. Because the higher drain voltage leads to a higher gate voltage at the onset of quasi-saturation, the peaks shift to higher gate voltages. In addition, the peak value increases

in CGS+CGB and decreases in CGD as the VDS increases as shown in Fig. 4.1. It attributed to the charge partitioning under the gate when varying the drain voltage.

4.3 Capacitances versus V_GS for Different Layout Structures

For the square structure, however, second peak in CGS+CGB and CGD are observed when biasing at high drain voltage (VDS=10 and 20 V) (see Fig. 4.2). But there are no additional peaks in CGS+CGB and CGD for circle structure that has ring shape like square structure. The same phenomenon is shown in Fig. 4.3, the CDG falls slowly at high drain voltages for square structure as gate voltage increases. From Fig. 4.3, the CDG almost equals to each other for three structures before the device entered the quasi-saturation regime. When gate voltage exceeds threshold voltage, the CDG starts to increase quickly due to the channel region is inverted to attract charges. As shown in Fig. 4.4, the currents flow from drain to source with uniform distribution in the full region of the fishbone and circle structures. However, in the square structure, the corner region of the drift shows lower current density than the edge region [36], [37], and thus it is needed higher gate voltage to enter quasi-saturation. At the first peak, although the edge of the square ring is operated in quasi-saturation region, the corner is still in pre-quasi-saturation. By keeping increasing the gate voltage, the current in the corner region is high enough to make the velocity of electrons in the drift saturated.

Therefore, the corner region operates in quasi-saturation and second peaks are generated in the CGS+CGB and CGD.

4.4 Summary

In this chapter, the capacitance characteristics of RF LDMOS transistors with different layout structures are studied. Since LDMOS transistor has a lateral non-uniform doping channel and a drift region, peaks in CGS+CGB and CGD have been observed. For the ring

structure, two peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. Besides, the circle structure has the same capacitance characteristics as the fishbone structure that indicates only one peak in the capacitance curve.

We have to consider these parameters like the threshold voltage, quasi-saturation current and drift depletion capacitance that affect the capacitance in the LDMOS capacitance model.

0.0

Fig. 4.1 Extracted CGS+CGB, CGD and the drain current versus gate voltage at different drain biases for the fishbone structure.

-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8

Fig. 4.2 Extracted CGS+CGB and CGD versus gate voltage at different drain biases for the (a) square and (b) circle structure.

-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 40.0f

80.0f 120.0f 160.0f 200.0f 240.0f 280.0f 320.0f 360.0f

V_DS (V) 0.1 1 5 Capacitance (F) 20

Gate Voltage (V) Fishbone

Square Circle

C_dg

Fig. 4.3 Extracted CDG versus gate voltage at different drain biases for the fishbone, square and circle structure.

(a) (b) (c)

Fig. 4.4 Schematic view of layout structure and current distribution: (a) fishbone structure, (b) square structure and (c) circle structure.

Chapter 5

Modified MOS Model 20 (MM20) for LDMOS

5.1 Introduction

The MOS Model 20 (MM20) is a compact MOSFET model focusing on DC characteristics. It has been developed to describe the electrical behavior of the region under the thin gate oxide of a high-voltage MOS device, like an LDMOS device. MM20 combines MOS Model 9 (MM9) for the channel region and MOS Model 31 (MM31) for the drift region under the thin gate oxide. This model calculates the equations that are describing transistor electrical characteristics in surface-potential formulations. In order to improve the convergence behavior during circuit simulation, it uses an internal voltage at the transition (node Di) from the channel region to the drift region to calculate the surface potentials [38].

The surface potential as a function of the terminal voltages is obtained by the explicit expression as derived in ref. 39. Using these equations can describe the all operation regimes (accumulation, depletion, and inversion in both the channel region and the drift region). In addition, the MM20 also include several important physical effects like mobility reduction, velocity saturation, drain-induced barrier lowering, static feedback, channel length modulation, and weak avalanche (or impact ionization). If transistors have an additional thick field oxide, this model can be used in series with a separate model for the drift region under the thick field oxide. Consequently, the MM20 provides an accurate description in all operating regimes, ranging from subthreshold to superthreshold, in both the linear and saturation regime [40].

5.2 T-CAD Simulation

We simulate the quasi-saturation effect in the LDMOS by using the T-CAD simulation

software. The structure is built on measured device in 2D dimension, and we do our best to make the simulation factor as the same as real phenomenon. Fig. 5.1 shows the simulated structures showing lateral electric field and the depletion region at Vg = 2.5 V and Vd = 10 V.

The maximum lateral electric field occurs at the pinch-off region near the gate edge and the drift region under the FOX is inversion. At this condition, the device does not yet enter quasi-saturation and channel current still increases with increasing gate voltage. Under Vg = 10 V and Vd = 10 V, the space-charge distribution changes, and the maximum lateral electric field shifts toward the drain and occurs in the drift region (see Fig. 5.2). Additionally, the lateral electric field decreases near the gate edge and the drift region under the FOX becomes accumulation. At this condition, the drain current is dominated by drift region and the device enters quasi-saturation [41]. Above described device have the poly gate covering on FOX and this poly gate is called field plate. Next, we discuss the device only have poly gate on the channel region. Fig. 5.3 shows the device does not enter quasi-saturation and is biased at Vg = 2.5 V and Vd = 10 V. It is the same as Fig. 5.1 that the maximum lateral electric field occurs at the pinch-off region near the gate edge and the drift region under the FOX is inversion. As device is bias at Vg = 10 V and Vd = 10 V, the maximum lateral electric field still occurs in the channel region (see Fig. 5.4). In addition, the space-charge distribution does not change much and the most drift region under the FOX is still inversion. Therefore, the device with field plate can make the drift region transfer its type from inversion to accumulation and make the lateral electric field distribute uniformly. So, it would increase the device breakdown voltage.

5.3 Modeling Strategy

For simplicity, some physical effects like self-heating and weak avalanche are not concluded in the modified model. Besides, based on the T-CAD simulation results, we have modified the drift region current for better fitting our measured I-V and C-V curves.

The device DC model would be developed with analysis of carrier transport in the channel and drift regions. The drain current is separated from two elements, one is through the intrinsic MOS channel (Ich) and the other is through the drift region (Idrift), and the two currents are formulated respectively in terms of the external bias VG, VD, VS, VB and the unknown voltage VDi. Then, VDi is solved automatically by equating Ich to Idrift. Therefore, the drain current is expressed explicitly by the external terminal voltage. The channel current is expressed as follow: thin-gate-oxide capacitance per unit area, Vinv0 represents the inversion charge Qinv per unit area at the source side, and θ3 = μch / (Lchvsat) represents velocity saturation in the channel region, with μch the zero-field electron mobility in the channel region and vsat the saturated drift velocity of electrons. The factor ξ = (∂Qinv/ ∂ψs)/ Cox reflects the variation of inversion charge with surface potential, and is taken as ξ = [1+ (1/ 2 · γ0)] /√(V1 + ψs0) , where γ0 is the body factor at the source, V1 = 1 V, and ψs0 is the surface potential at the source. From Fig.

5.2 & Fig. 5.4, as the device enter quasi-saturation, the voltage drop in the drift region increases led to the maximum electric felid occurs in the drift region and drain current is dominated by drift region. The effective electron mobility ( ) is used to describes this effect. As electric felid increase in the drift region, the carrier velocity will enter saturation regime and θ

dr

μeff

3dr (=μ_eff^dr/ (Ldrvsat)) can describes this effect. When device without field plate is biased gate voltage from 2.5 V to 10 V, the current have to pass through a depletion region under Fox. Therefore, the high resistance (Rdr) limits the current in the drift region when device enter quasi-saturation. In addition, the device with field plate has different

performance. As VG= 2.5V, the drift region under Fox is depletion region and like general performance (see Fig. 5.3 & 5.4). As VG= 10V, the drift region under Fox becomes electrons accumulated layer and the drain resistance is lower to enhance current (see Fig. 5.1& 5.2).

performance. As VG= 2.5V, the drift region under Fox is depletion region and like general performance (see Fig. 5.3 & 5.4). As VG= 10V, the drift region under Fox becomes electrons accumulated layer and the drain resistance is lower to enhance current (see Fig. 5.1& 5.2).