Chapter 1 Introduction
1.4 Thesis Organization
In chapter 1, a brief overview of PV energy and thin film pc-Si solar cells were shown. An overview of crystallization processes of a-Si were generally described in the subsequent section. The motivations of this thesis were subsequently explained to introduce this thesis.
In chapter 2, practical experimental details were carried out. First, an overall process overview was shown as an introduction for the whole thin film pc-Si solar cell process. Benefits of the two step process to form the thin film pc-Si layer were emphasized here. Next, the substrate preparation was described to show how we chose our substrates. Then the seed layer formation process was introduced, including SPC and AIC methods. Also, the epitaxial growth and the solar cell fabrication process, including hydrogenation, emitter formation, and contact formation, were shown in this chapter.
In chapter 3, some results from this work were introduced and further discussed. A general introduction about the results was introduced as the beginning. Next, various seed layers were investigated, including SPC seed layers prepared by e-gun evaporation, SPC seed layers prepared by PECVD, and AIC seed layers. Both crystallographic properties and electrical properties were investigated in this work for all the seed layers.
The crystallographic characterization results, including X-ray diffraction (XRD),
transmission electronic microscope (TEM), and optical microscope were shown here.
And the electrical characterization results, including resistivity versus temperature and Hall affect measurement were also shown in this chapter. After the seed layers characterization, some results of epitaxial layers were also introduced. Then the final results of solar cells were also shown in the last section of this chapter.
Last but not least, summary and conclusions were given in chapter 4.
Chapter 2
Fabrication of Thin Film Polycrystalline Silicon Solar Cells
2.1 Process Overview
Different technologies of fabricating a thin film pc-Si solar cell are investigated.
The challenge is to obtain a high quality pc-Si layer on non silicon substrates. The electrical quality of a pc-Si can be improved by increasing grain size/decreasing number of grain boundaries. Direct deposition of silicon on non silicon substrate results in small grained material. To obtain larger grains, a seed layer + epitaxial growth two step process to form the pc-Si absorber layer can be used. By using the seed layer, we can grow larger grain size and solely control our crystalline property without considering the effect of doping concentration which is needed in the absorption layer of solar cell.
Fig. 2-1 shows the general process flow of a two step pc-Si solar cell. A brief overview of the whole process and each step is discussed in detail as follows.
(a) Foreign substrate
The pc-Si solar cells use silicon layer of 2–6 μm thick. This pc-Si layer is not self-supporting and therefore, a foreign substrate is used to enhance its mechanical strength. An appropriate substrate is chosen and it needs to fulfill certain requirements like thermal stability, matched CTE to be compatible with the deposition process and to be economical compatible [19].
(b) Seed layer formation
The seed layer here is a thin (~200nm) layer of pc-Si as a starting point for the next epitaxial step. By using the seed layer, we can grow larger grain size and solely control our crystalline property without considering the effect of doping concentration which is needed in the absorption layer of solar cell. Different technologies exist to prepare a thin pc-Si layer as mentioned in chapter 1. Thus, this seed layer can be obtained through several crystallization methods, namely SPC, MIC, and laser crystallization. In this work, we mainly focus on AIC and SPC. Low aspect-ratio grains are possible to obtain.
The experimental description of these two processes is detailed in section 2.2, and the results will be shown in Chapter 3.
(c) Epitaxial growth
The seed layer is epitaxially thickened by atmospheric pressure CVD. The grown pc-Si is the back surface field and base or absorber layer of the solar cell. Since the crystalline structure are already determined by the seed layer, here we can control the layer thickness and doping type and doping level without concerning the dopants will effect crystallization process. The final grain diameter is determined by the seed layer.
Epitaxial growth is possible with different techniques and a wide temperature range. In this work, high temperature CVD is used as will be described in section 2.3.
(d) Solar cell fabrication
We prepare solar cells on the deposited pc-Si layer. It involves several steps.
Hydrogenation is the first step after the pc-Si formation. After hydrogenation, the n-type emitter was deposited since we have a p-type poly-Si absorption layer. As a final processing step, metal contacts are created to deliver the generated power to the external world. Each of these steps will be described in detail in section 2.4.
2.2 Substrate Preparation
Thermal stability: the substrate must be stable towards the at temperatures of the deposition (~ 1130 ºC). Standard inexpensive glasses used for amorphous and microcrystalline Si solar cells, such as soda lime glass, cannot be used at these deposition temperatures due to their too low softening temperature (~ 575 ºC).
Even the more stable borosilicate glasses used in solid phase crystallization cannot be used because of thermal stability problems (softening temperature ~ 820 ºC).
Optical properties: Thin-film crystalline solar cells allow in principle to maintain high efficiencies while using very thin active layers. However, this is only possible if efficient light confinement is applied. This requires a good light reflection at the interface between the Si layer and the substrate on one hand and a scheme to give light rays an oblique path on the other hand.
Impurity content: It is well documented that many impurities have detrimental effect on the performance of Si solar cells. In particular, most metallic impurities start to be harmful already at trace concentrations. When we deposit Si at high temperature on a foreign material, an important concern therefore is the possible contamination of the layer by solid state diffusion of impurities from the substrate.
These contaminants can either be elements from the main components of the substrate material or other species present as impurities in the material. The need for a barrier layer or clean step therefore has to be reassessed for each newly developed material.
Coefficient of Thermal Expansion(CTE): After epitaxial deposition, the substrate needs to cool down from deposition temperature to room temperature. During cooling down, the substrate and the silicon layer contract and mechanical stress develops due to CTE mismatch. This results in deteroitaion of the films.
Therefore, the second requirement is that the thermal expansion coefficient of the substrate is as close as possible to the one of silicon (~ 4.2×10-6 K-1). Metal substrates such as stainless steel can be cost-effective, however their thermal expansion coefficients is usually much higher (thermal expansion coefficient of stainless steel ~ 12×10-6 K-1).
Economically cheap substrate: The third and most important requirement is the economical compatibility of the substrates. This means, the substrates should be produced in large amounts at a low cost.
Oxidized silicon wafers are used as a model for a foreign substrate in this work.
They are obtained by wet oxidation of a monocrystalline silicon wafer. The oxide layers are typically around 1.5 μm thick. They are not considered as suitable for industrial production, since they are expensive bulk silicon wafers. However for practical reasons they were used for fast depositions of pc-Si to optimize the process in this work.
2.3 Seed Layer Formation
Direct deposition of pc-Si layers have the advantage of simple processing step but suffer from the small grain size resulting in a large number of defects, where recombination between minority and majority carriers can occur. An obvious strategy to reduce the number of defects in the pc-Si layers is to enlarge the grain size of the material. Due to a larger grain size, less grain boundaries are obtained and one can expect a better electronic quality of the material with less carrier recombination at the grain boundaries. In this work, SPC and AIC are used to form the seed layer on foreign substrate as described as follows.
2.3.1 Solid Phase Crystallization
As previously shown in Fig. 2-1 the first process step is obtaining a pc-Si seed layer. Fig. 2-2 shows schematically the various steps to obtain a seed layer based on SPC.
(a) a-Si deposition: An a-Si layer of 200-480 nm thick is deposited on top of the
oxidized wafer as shown in Fig. 2-2 (a, b). The thick layer is used only for easier measurement. Two different deposition techniques, high vacuum e-gun evaporator and Plasma Enhanced Chemical Vapor Deposition PECVD were used in this work.
The a-Si layer deposited by e-gun system is regarded as a dirty one since there are some metal contaminations. This Si target is in contact with a metal target holder which might possibly cause contamination. On the other hand, since there is no such metal contamination when applying PECVD deposition technique, a-Si samples deposited by PECVD are regarded as clean sample.
E-gun: The system Pfeiffer PLS550 is used. All e-gun depositions are done at room temperature. The base pressure in the chamber was around 1.0 x 10-6 mbar.
Both intrinsic and p+ type of layers were deposited at a rate of 4A/sec using a e-gun power of10 keV. P-type target were made by crushing a p+ (100) mono-crystalline silicon wafer with boron doping of 1019/cm3 into small pieces.
PECVD: The system Oxford Plasma Lab is used. PECVD deposition was carried out at two different deposition temperatures, which are 200°C and 300°C respectively. Intrinsic, p-type, and n-type a-Si layers are deposited at both deposition temperatures. Intrinsic a-Si layer was deposited by using 100sccm SiH4. 100sccm:100sccm of PH3 to SiH4 was using for n-type a-Si deposition. The ratio of BF2 to SiH4 was also 100sccm:100sccm for p-type a-Si deposition.
(b) Annealing: As illustrated in Fig. 2-2 (b & c), the deposited a-Si layers are crystallized by annealing under N2 ambient at different annealing temperatures and
times. Annealing temperature and time ranging from 550°C to 700°C, and 12 to 96 hours By X-ray diffraction we can find out that during annealing the a-Si crystallized into grains with orientations of (111) (220) and (311) direction in both deposition techniques, and most grain sizes were smaller than 1 um.
2.3.2 Aluminum Induced Crystallization
Fig. 2-3 shows schematically another alternative to make a pc-Si seed layer, this time via the AIC process.
(a) Al and a-Si deposition: As illustrated in Fig. 2-3 (a), an Aluminum (Al) layer of ~ 200 nm thick is evaporated on top of the substrate in a high vacuum e-gun evaporator. After the deposition, the Al layer is exposed to air for 2 minutes and results in a thin native oxide layer [19]. Like in the case of silicon the oxidation of aluminum is self-limited meaning that the oxide layer prevents further oxidation.
After the thin oxide layer was formed, an a-Si layer (~ 200 nm thick) is evaporated on top of the Al in the same system.
(b) Annealing: The Al/a-Si layer stack is annealed for 5 hours in a tube furnace at 500°C in a nitrogen atmosphere. During the annealing, a layer-exchange takes place between the Al and the Si, and the a-Si crystallizes into pc-Si of large grains as illustrated in Fig. 2-3 (b). The oxide layer remains in the position throughout the annealing process by separating top and bottom layer during exchange phenomena and controls the diffusion process. The final results were a pc-Si layer with on top the aluminum layer.
(c) Al removal: After annealing, the Al layer is etched selectively by means of a chemical mixture containing phosphoric acid. Thus, the pc-Si seed layer on foreign substrate is obtained as shown in Fig. 2-3 (c) which can be used as seed layer for further epitaxial growth.
2.4 Epitaxial Growth
A stack of highly Boron doped p+ and a moderately Boron doped p-type pc-Si layer is epitaxially grown on the pc-Si seed layers. The growth mechanism involves thermal decomposition of a silicon precursor on the surface. CVD is possible over a wide range of temperature. The use of high temperatures results in a higher quality potential, but also a higher cost compared with low temperature techniques. Currently, the high temperature route was investigated for solar cell applications at IMEC.
Heat-activated CVD system Epsilon2000 is used in this work. This is a Rapid Thermal Chemical Vapor Deposition (RTCVD) system.
The Epsilon2000 is a commercial thermal CVD system designed by ASM. The reactor works at atmospheric pressure and high temperatures (950-1250°C), deposition rates up to 10 mm / min is possible with very low defect density [21]. In this work, the deposition temperature was 1130°C with growth rate 1.4 um / min. Trichlorosilan (SiHCl3) diluted in hydrogen was used as precursor gas, the overall reaction can be written as follows [22]:
SiHCl3+H2 Si+3HCl
In-situ doping was made through the addition of diborane (B2H6). Following
sequences were typically grown on the seed layers a 0.5 μm layer with p+ doping of 3x1019 cm-3 followed by a 1.5 μm layer with p-type doping of 1016 cm-3. The thin p+ layer acts as a Back Surface Field (BSF) which Limits the recombination of minority carriers at the rear side and also provides a conductive path to the contacts for the collection of majority carriers. In the moderately doped layers, also called base, most of the photons are absorbed here and collected by the junction after converted into carriers.
The growth process is consisted of several steps as flowing:
(1) Loading the sample at 250°C in N2 gas and heating up to 500°C. Draining and introduction of H2 gas followed by rapid heating up to 1130°C in 92 seconds.
(2) Deposition of the p+ layer followed by a 10 to 30 second free step growth in H2 gas.
(3) The p layer deposition followed by cool down to 250°C under H2 gas.
Fine-grained pc-Si: Direct deposition of pc-Si on foreign substrate by CVD was also done in this work. Since the grain size is usually around 100 nm [23], the pc-Si done by direct deposition is regarded as fine-grained sample. This fine-grained pc-Si is prepared by direct sending substrates into exact the same epitaxial procedure as mentioned above but without forming a seed layer. The same oxidized Si substrate we used for seed layer formation is also used here for fine-grained pc-Si. A lot of nuclei are formed simultaneously during deposition, thus the resulting material has a very small grain size.
2.5 Solar Cell Fabrication
2.5.1 Hydrogenation
After the absorber layer was formed by epitaxial growth, a hydrogenation passivation step was introduced. The high density of defects at grain boundaries of poly-Si can be expected, especially the dangling bonds, which can trap carriers generated in the absorption layer. Enlarge the grain size of poly-Si may reduce such problem, but the fact is it cannot be unlimited enlarged. Therefore, together with enlarging the grain size, a defect passivition step is applied.
The passivation is carried out by direct plasma hydrogenation in PECVD system at a temperature of 400°C [23]. Just before loading, the samples are subjected to an HF (2%) dip to remove the native oxide. This oxide layer prevents the H-atoms to penetrate in the layer and might lead to a poor passivation. After loading of samples, the system is evacuated and the temperature is stabilized for about 10 minutes in flowing hydrogen. The plasma is ignited at 77 mW/cm2 and 2 Torr after which the power and the pressure are immediately lowered to 62 mW/ cm2 and 1 Torr. The hydrogenation plasma temperature is around 400 °C at which the hydrogen ions are relatively mobile. To avoid out-diffusion of hydrogen during sample unloading, the layers are cooled down in the while the plasma kept switched on. After cooling down, the plasma is switched off and the samples are unloaded.
2.5.2 Emitter Formation
After the passivation step, an n-type emitter is formed. The emitter in the semiconductor solar cell can create an internal electric field in order to separate the minority carriers and majority carriers created after absorption of solar energy. Since our absorption layer is formed by p-type poly-Si, the emitter can be formed by creating an
n-type area. In this work a heterojucntion with intrinsic thin layer (HIT) emitter is used.
An intrinsic layer and an n+ a-Si layer were deposited by PECVD system in a raw.
Just before loading, the samples get an HF dip (2%) to remove the native oxide and resulting in a hydrophobic pc-Si surface. After pumping down the chamber, its temperature is stabilized during 10 minutes. Then SiH4 (100 sccm) is introduced and the gas flow is stabilized during another minute. After this conditioning of the chamber and the samples, the plasma is ignited at 37 mW/cm2, and the power is lowered to the deposition power which is in the range of 15 to 25 mW/cm2. When the intrinsic layer is deposited, the power is switched off and 100 sccm of diluted phosphine (1% PH3 in H2) is added to the gas flow to deposit the n+ a-Si:H layer using the same plasma sequence as for the intrinsic a-Si:H layer. In order to give high absorption ability in emitter, the thickness was limited to only 15nm. Subsequently, 80 nm of Indium Tin Oxide (ITO) was deposited. This ITO serves as electrical conductor and also anti-reflection coating for the cell. The deposition of ITO was done at room temperature by RF sputtering.
In this work, the passivation was done before emitter forming in order to avoid crystallization or modification of the a-Si:H due to the temperature was around 400˚C while the a-Si:H deposition is done at temperature below 200˚C.
2.5.3 Contact Formation
As a final step, the n- and the p-type layer are contacted to extract current from and to apply a forward bias across the photovoltaic device. Since insulating substrates are used, both the emitter and the base contact are on the same side of the device (on top of
the silicon layer).
Two configurations can be used for the thin-film solar cells. In a superstrate configuration, the light enters the cell through the support onto which the active layer has been deposited. In a substrate configuration, the light penetrates through the other surface. Due to convenience at this stage of research, the pc-Si layers studied in this work have a substrate configuration with both contacts at the front side. Due to one-side contacting, the holes need to diffuse over a larger distance than in the conventional two-side contacted cells. Holes generated in the p-type layer need to travel vertically, down to the p+ layer, then horizontally towards the nearest contact and finally vertically to the contact itself. The horizontal distance determines the resistance and is the main contributor to the final series resistance of the cell. To limit losses in thin film polycrystalline solar cells, a careful design of the contact pattern is needed.
An interdigitated contact process is used in this work [23]. Here both emitter and base contacts consist of fingers and a busbar on top of the cell. Fig. 2-4 (a) shows the cross section schematic picture of interdigitated contact, and Fig. 2-4 (b) indicates the top view of a unit cell.
The generated electrons are collected through contact on emitter side as the white arrow shown in Fig. 2-4 (a). And the generated holes are collected through the base contact indicated by the black arrows in Fig. 2-4 (a). Since the actual vertical distance is
The generated electrons are collected through contact on emitter side as the white arrow shown in Fig. 2-4 (a). And the generated holes are collected through the base contact indicated by the black arrows in Fig. 2-4 (a). Since the actual vertical distance is