SPC Seed Layers Prepared by E-gun Evaporation

3.2.1 P-type Doping Seed Layers

3.2.1.1 Crystallographic Properties

The annealing results for samples deposited by e-gun evaporation are listed in Table 3-1. These results are mainly based on X-ray diffraction examination. The thickness of pc-Si layer for examination here is around 480 nm, and we used Grazing Incidence XRD (GIXRD) mode to perform our measurement. The annealing summarize in Table 3-1 were carried out for 96 hours. As we can see from the Table 3-1, intrinsic a-Si deposited by electron beam evaporation cannot crystallize in 96 hours for annealing temperature lower than 600°C. On the other hand, the p-type a-Si layer starts to crystallize at the annealing temperature of 600°C. Both intrinsic and p-type a-Si were successfully crystallized at 650°C and 700°C.

Fig. 3-1 shows the X-ray diffraction graph of p-type samples annealing at 600°C (red line), 650°C (black line), and 700°C (green line) for 96 hours, and the blue line represents the as-deposited p-type a-Si layer. As we can see in the figure, the as-deposited layer has no peak in the 2θ range from 20° to 60°. Except the as-deposited layer, three typical peaks appear in the measured range for the annealed samples. These three peaks are located at 28.5°, 47° and 56° which represents the grain orientation of (111), (220), and (311) respectively.

However, the intensities of these peaks are different at different annealing temperatures. First, though the 600°C annealing sample has the peaks at the same detected angles as others, but its intensity is the smallest among them. As we increase

the annealing temperature from 600°C to 700°C, the intensity increases further. The intensity of X-ray diffraction graph can be regards as the amount of crystallization fraction [25]. The higher the intensity, the more fraction of the silicon film is crystallized.

A-Si has to gain enough energy to overcome the activation energy before transferring to pc-Si. Thus, there is an incubation time before crystallization happen during annealing process [26]. During this incubation time, no amorphous to crystal transfer happens but the a-Si keep absorbing thermal energy from the ambient. The incubation time related to the annealing temperature. When increasing the annealing temperature, the incubation time will decrease. This is due to higher annealing temperature provides more thermal energy, and thus it is more easily to transform into poly crystalline state. As a result, the crystallization fraction is higher when using higher annealing temperature for the same time. So we can see that 96 hours is not enough for the samples annealing at 600°C and 650°C. Thus the crystallization fraction is smaller and results in lower XRD intensity.

Besides the annealing temperature, control the annealing time may also let us see the progress of crystallization process. Fig. 3-2 shows X-ray diffraction graph of the boron doping sample annealing at 700°C for 24, 48, and 96 hours respectively. From the graph we can observe there is no peak when we only anneal for 24 hours, which can probably means that the crystallization process has not started yet. When we double the annealing time, the peak can be obviously observed from the graph. We further make the annealing time as long as 96 hours, and we can see the intensity of the peaks is further increased as expected. The very basic reason of time dependence phenomenon is actually the same as temperature dependence, the longer time you anneal the more

thermal energy you provide to the silicon layer. Thus the intensity will keep increasing and saturate when the whole layer is fully crystallized.

The TEM picture of Fig. 3-3 (a) shows a proof of not fully crystallized layer. The thickness of the as-deposited a-Si for examination was about 480nm, however, only 100nm ~ 110nm pc-Si were formed inside the whole silicon layer when annealing at 600°C for 96 hours, the other 375nm remained amorphous as we can see in the picture.

As a result, the intensity of X-ray diffraction is much smaller (the red line in Fig. 3-1).

Lots of planar defects are visible in boron doping e-gun deposited samples as illustrated in Fig. 3-3 (b).

From Fig. 3-4 (a), the TEM picture clearly shows that the whole a-Si layer of 480 nm was fully crystallized when annealing at 700°C for 96 hours. The surface was smooth and grains are cross the full layer thickness, which was what we want to further grow our epitaxial layer. Most grain sizes are several hundred nm but smaller than 1 μm.

Lots of planar defects such as stacking faults are visible in boron doping e-gun deposited samples as illustrated in Fig. 3-4 (b). By comparing TEM pictures of Fig. 3-3 and Fig. 3-4 we can observe the crystallization process occurred heterogeneously from the interface of SiO2 and a-Si rather than homogeneously inside the whole a-Si layer.

The crystallization preferentially start from the interface was observed ordinarily in previous works [27]-[29].This phenomenon is believed due to the release of stress induced by the thermal expansion difference between Si and SiO2 [29]. In Fig. 3-3, the surface of pc-Si shows rather rougher than those fully crystallized surface of pc-Si as in Fig. 3-4 is probably due to the crystallization process was not finished yet.

3.2.1.2 Electrical Properties

The electrical activation of the defects at the grain boundaries is studied by measuring the resistivity ρ of majority carriers in seed layers as a function of temperature (300 – 500°K) (Fig. 3-5). Here, three samples annealing at 600°C, 650°C, and 700°C for 96 hours are measured. The ρ vs. T measurements are carried out in a four point probe configuration (HP4156) with sintered Al patterns as contacts. The curves show a decrease of the resistivity with increasing temperature. Normally on mono-crystalline silicon, an increase of the resistivity is found with increasing temperature due to an enhanced phonon scattering. For pc-Si the situation is different.

Here, the resistivity of the pc-Si layers is the sum of the intra-grain resistivity and the resistivity of the grain boundaries, which is usually much larger and determines the total resistivity [30]. At a higher temperature more carriers can surmount the potential barrier (a higher thermionic current) and a lower resistivity is observed.

As can be seen in Fig. 3-5, increasing the annealing temperature lowers the resistivity with slopes are almost the same to each other. The slopes in the graph are related to the activation energy and could be further calculate by Setto’s [30] model to estimate the carrier trapping density at the grain boundary if the doping concentration is known. Probably the potential barrier at the grain boundaries are similar for all measured samples and independent of annealing temperature because it can be assumed that the activation energy is linked to the potential barrier. The resistivity decreases with increasing annealing temperature might caused by intra-grain resistivity and different crystallization fraction as concluded from X-ray graphs.

3.2.2 Intrinsic Seed Layers

3.2.2.1 Crystallographic Properties

X-ray diffraction graph of intrinsic Si isothermal annealed at 600°C, 650°C, and 700°C for 96 hours are shown in Fig. 3-6. The thickness of the layer is also around 480 nm. Same trend as p-type samples can be observed here, increasing the annealing temperature will also increase the intensity of each peaks. Contrary to the p-type layers, annealing at 600ºC for 96 hours was not sufficient for intrinsic a-Si layers deposited by e-gun evaporation. To investigate if the crystallization is impossible or not, one extra annealing was done for 173 hours. XRD measurement showed that only the samples annealed at 173 hours started to show the typical peaks as indicated in Fig. 3-7.

According to Van Vecheten et al. [31], the number of charged vacancies increases when the Fermi level moves up or down from the mid-gap position. As dangling bonds are more common defects than vacancies in a-Si, these dangling bonds may play a similar role in the crystallization mechanism. As mentioned in chapter 2, the dangling bonds at the interface of amorphous to crystalline silicon actually are only certain sites available for crystallization [32]. These dangling bonds diffuse from the bulk towards the amorphous to crystalline interface during annealing and the capture cross section at the interface depends on the charge state of the dangling bonds and modifies the crystallization process. The change of their charge states is responsible of the enhancement of crystallization process due to electrical activity [32].

Besides the dependence on temperature, Fig. 3-8 shows the dependence on annealing time for intrinsic samples. Like p-type doping samples, there is no crystallization can be observed after annealing for 24 hours, but after 48 hours annealing we can clearly see the three peaks which means it started to crystallize.

3.2.2.2 Electrical Properties

The ρ vs. T measurements was also done on intrinsic e-gun seed layers and are shown in Fig. 3-9. The difference of slopes between p-type (blue lines) and intrinsic (red lines) samples can be observed in Fig. 3-9. The slope is larger for intrinsic samples due to higher activation energy. Though we do not really know the doping level of our p-type sample, but we can see that the doping samples have lower resistivity which means they are in the second regime of Setto’s model [30]. This means that the doping concentration is at least more than the trapping density at the grain boundaries. Due to the high resistivity at room temperature, Hall effect measure was not possible to carry out on both types of samples.