Contact Formation

As a final step, the n- and the p-type layer are contacted to extract current from and to apply a forward bias across the photovoltaic device. Since insulating substrates are used, both the emitter and the base contact are on the same side of the device (on top of

the silicon layer).

Two configurations can be used for the thin-film solar cells. In a superstrate configuration, the light enters the cell through the support onto which the active layer has been deposited. In a substrate configuration, the light penetrates through the other surface. Due to convenience at this stage of research, the pc-Si layers studied in this work have a substrate configuration with both contacts at the front side. Due to one-side contacting, the holes need to diffuse over a larger distance than in the conventional two-side contacted cells. Holes generated in the p-type layer need to travel vertically, down to the p⁺ layer, then horizontally towards the nearest contact and finally vertically to the contact itself. The horizontal distance determines the resistance and is the main contributor to the final series resistance of the cell. To limit losses in thin film polycrystalline solar cells, a careful design of the contact pattern is needed.

An interdigitated contact process is used in this work [23]. Here both emitter and base contacts consist of fingers and a busbar on top of the cell. Fig. 2-4 (a) shows the cross section schematic picture of interdigitated contact, and Fig. 2-4 (b) indicates the top view of a unit cell.

The generated electrons are collected through contact on emitter side as the white arrow shown in Fig. 2-4 (a). And the generated holes are collected through the base contact indicated by the black arrows in Fig. 2-4 (a). Since the actual vertical distance is only of few um, the resistance of the holes is mainly determined by the distance between two base contacts. This concept can also be used for larger cell areas and for thinner p⁺ layers. The base contacts are formed by lift-off photolithography and wet chemical etching (HNO3/Buffer HF/H2O in volume ratios 40:1:16) of the n⁺ layer. After the lift-off the Al contacts only remain on the etched base area. In total there are 8 base

fingers connected to a busbar, and the distance between two base contacts is around 1 mm. The holes thus need to travel over only 0.3 mm on average to reach the nearest contact.

After the evaporation of the base fingers, the front grid fingers were evaporated through a shadow mask in such a way that there are two emitter fingers around each base finger as can be seen in Fig. 2-4. The front grid fingers were made from a stack of Ti (70 nm), Pd (50 nm) and Ag (2μm). The Ti serves as a barrier for metal diffusion into the silicon, the Pd serves as adhesion layer between Ti and Ag, and the Ag contact is the conducting metal for the electrons. The spacing between two emitter fingers is also around 1 mm. In a last step the cells were separated by a second lithography process, where small areas of 1 cm² are created after wet chemical etching. After etching, the final structure is annealed to ensure a good contact between metal contacts and silicon layer.

Chapter 3

Results and Discussion

3.1 Introduction

In this chapter, we will show the results of optimization and characterization of SPC seed layers. They will be discussed in different sections according to silicon deposition techniques and crystallization methods. We examine the crystallization results on our seed layers by several different methods, including X-ray diffraction (XRD), Transmission Electronic Microscope (TEM), Scanning Electron Microscope (SEM) and Optical Microscope. With these techniques it’s possible to determine the crystallization structure, crystalline fraction and grain properties, which is useful information for later correlation of the seed layer properties with the solar cell results.

Resistivity versus temperature and Hall measurement are also carried out to determine the electrical properties in order to further optimum our pc-Si seed layer.

3.2 SPC Seed Layers Prepared by E-gun Evaporation

3.2.1 P-type Doping Seed Layers

3.2.1.1 Crystallographic Properties

The annealing results for samples deposited by e-gun evaporation are listed in Table 3-1. These results are mainly based on X-ray diffraction examination. The thickness of pc-Si layer for examination here is around 480 nm, and we used Grazing Incidence XRD (GIXRD) mode to perform our measurement. The annealing summarize in Table 3-1 were carried out for 96 hours. As we can see from the Table 3-1, intrinsic a-Si deposited by electron beam evaporation cannot crystallize in 96 hours for annealing temperature lower than 600°C. On the other hand, the p-type a-Si layer starts to crystallize at the annealing temperature of 600°C. Both intrinsic and p-type a-Si were successfully crystallized at 650°C and 700°C.

Fig. 3-1 shows the X-ray diffraction graph of p-type samples annealing at 600°C (red line), 650°C (black line), and 700°C (green line) for 96 hours, and the blue line represents the as-deposited p-type a-Si layer. As we can see in the figure, the as-deposited layer has no peak in the 2θ range from 20° to 60°. Except the as-deposited layer, three typical peaks appear in the measured range for the annealed samples. These three peaks are located at 28.5°, 47° and 56° which represents the grain orientation of (111), (220), and (311) respectively.

However, the intensities of these peaks are different at different annealing temperatures. First, though the 600°C annealing sample has the peaks at the same detected angles as others, but its intensity is the smallest among them. As we increase

the annealing temperature from 600°C to 700°C, the intensity increases further. The intensity of X-ray diffraction graph can be regards as the amount of crystallization fraction [25]. The higher the intensity, the more fraction of the silicon film is crystallized.

A-Si has to gain enough energy to overcome the activation energy before transferring to pc-Si. Thus, there is an incubation time before crystallization happen during annealing process [26]. During this incubation time, no amorphous to crystal transfer happens but the a-Si keep absorbing thermal energy from the ambient. The incubation time related to the annealing temperature. When increasing the annealing temperature, the incubation time will decrease. This is due to higher annealing temperature provides more thermal energy, and thus it is more easily to transform into poly crystalline state. As a result, the crystallization fraction is higher when using higher annealing temperature for the same time. So we can see that 96 hours is not enough for the samples annealing at 600°C and 650°C. Thus the crystallization fraction is smaller and results in lower XRD intensity.

Besides the annealing temperature, control the annealing time may also let us see the progress of crystallization process. Fig. 3-2 shows X-ray diffraction graph of the boron doping sample annealing at 700°C for 24, 48, and 96 hours respectively. From the graph we can observe there is no peak when we only anneal for 24 hours, which can probably means that the crystallization process has not started yet. When we double the annealing time, the peak can be obviously observed from the graph. We further make the annealing time as long as 96 hours, and we can see the intensity of the peaks is further increased as expected. The very basic reason of time dependence phenomenon is actually the same as temperature dependence, the longer time you anneal the more

thermal energy you provide to the silicon layer. Thus the intensity will keep increasing and saturate when the whole layer is fully crystallized.

The TEM picture of Fig. 3-3 (a) shows a proof of not fully crystallized layer. The thickness of the as-deposited a-Si for examination was about 480nm, however, only 100nm ~ 110nm pc-Si were formed inside the whole silicon layer when annealing at 600°C for 96 hours, the other 375nm remained amorphous as we can see in the picture.

As a result, the intensity of X-ray diffraction is much smaller (the red line in Fig. 3-1).

Lots of planar defects are visible in boron doping e-gun deposited samples as illustrated in Fig. 3-3 (b).

From Fig. 3-4 (a), the TEM picture clearly shows that the whole a-Si layer of 480 nm was fully crystallized when annealing at 700°C for 96 hours. The surface was smooth and grains are cross the full layer thickness, which was what we want to further grow our epitaxial layer. Most grain sizes are several hundred nm but smaller than 1 μm.

Lots of planar defects such as stacking faults are visible in boron doping e-gun deposited samples as illustrated in Fig. 3-4 (b). By comparing TEM pictures of Fig. 3-3 and Fig. 3-4 we can observe the crystallization process occurred heterogeneously from the interface of SiO2 and a-Si rather than homogeneously inside the whole a-Si layer.

The crystallization preferentially start from the interface was observed ordinarily in previous works [27]-[29].This phenomenon is believed due to the release of stress induced by the thermal expansion difference between Si and SiO2 [29]. In Fig. 3-3, the surface of pc-Si shows rather rougher than those fully crystallized surface of pc-Si as in Fig. 3-4 is probably due to the crystallization process was not finished yet.

3.2.1.2 Electrical Properties

The electrical activation of the defects at the grain boundaries is studied by measuring the resistivity ρ of majority carriers in seed layers as a function of temperature (300 – 500°K) (Fig. 3-5). Here, three samples annealing at 600°C, 650°C, and 700°C for 96 hours are measured. The ρ vs. T measurements are carried out in a four point probe configuration (HP4156) with sintered Al patterns as contacts. The curves show a decrease of the resistivity with increasing temperature. Normally on mono-crystalline silicon, an increase of the resistivity is found with increasing temperature due to an enhanced phonon scattering. For pc-Si the situation is different.

Here, the resistivity of the pc-Si layers is the sum of the intra-grain resistivity and the resistivity of the grain boundaries, which is usually much larger and determines the total resistivity [30]. At a higher temperature more carriers can surmount the potential barrier (a higher thermionic current) and a lower resistivity is observed.

As can be seen in Fig. 3-5, increasing the annealing temperature lowers the resistivity with slopes are almost the same to each other. The slopes in the graph are related to the activation energy and could be further calculate by Setto’s [30] model to estimate the carrier trapping density at the grain boundary if the doping concentration is known. Probably the potential barrier at the grain boundaries are similar for all measured samples and independent of annealing temperature because it can be assumed that the activation energy is linked to the potential barrier. The resistivity decreases with increasing annealing temperature might caused by intra-grain resistivity and different crystallization fraction as concluded from X-ray graphs.

3.2.2 Intrinsic Seed Layers

3.2.2.1 Crystallographic Properties

X-ray diffraction graph of intrinsic Si isothermal annealed at 600°C, 650°C, and 700°C for 96 hours are shown in Fig. 3-6. The thickness of the layer is also around 480 nm. Same trend as p-type samples can be observed here, increasing the annealing temperature will also increase the intensity of each peaks. Contrary to the p-type layers, annealing at 600ºC for 96 hours was not sufficient for intrinsic a-Si layers deposited by e-gun evaporation. To investigate if the crystallization is impossible or not, one extra annealing was done for 173 hours. XRD measurement showed that only the samples annealed at 173 hours started to show the typical peaks as indicated in Fig. 3-7.

According to Van Vecheten et al. [31], the number of charged vacancies increases when the Fermi level moves up or down from the mid-gap position. As dangling bonds are more common defects than vacancies in a-Si, these dangling bonds may play a similar role in the crystallization mechanism. As mentioned in chapter 2, the dangling bonds at the interface of amorphous to crystalline silicon actually are only certain sites available for crystallization [32]. These dangling bonds diffuse from the bulk towards the amorphous to crystalline interface during annealing and the capture cross section at the interface depends on the charge state of the dangling bonds and modifies the crystallization process. The change of their charge states is responsible of the enhancement of crystallization process due to electrical activity [32].

Besides the dependence on temperature, Fig. 3-8 shows the dependence on annealing time for intrinsic samples. Like p-type doping samples, there is no crystallization can be observed after annealing for 24 hours, but after 48 hours annealing we can clearly see the three peaks which means it started to crystallize.

3.2.2.2 Electrical Properties

The ρ vs. T measurements was also done on intrinsic e-gun seed layers and are shown in Fig. 3-9. The difference of slopes between p-type (blue lines) and intrinsic (red lines) samples can be observed in Fig. 3-9. The slope is larger for intrinsic samples due to higher activation energy. Though we do not really know the doping level of our p-type sample, but we can see that the doping samples have lower resistivity which means they are in the second regime of Setto’s model [30]. This means that the doping concentration is at least more than the trapping density at the grain boundaries. Due to the high resistivity at room temperature, Hall effect measure was not possible to carry out on both types of samples.

3.3 SPC Seed Layers Prepared by PECVD

Samples prepared by PECVD method annealing at 600°C are listed in Table 3-2, the annealing time was as long as 96 hours. As mentioned in chapter 3, because of the n⁺ a-Si deposited at 300°C blistered right after deposition, we had no further investigation on it. Also due to the main purpose in this work is comparing SPC seed layers with AIC seed layers, which is heavily doped p-type pc-Si. Thus, we had more focus on p-type doping silicon.

Besides the three crystallized samples in Table 3-2, we can observe peeling off phenomenon happened after annealing. There were two samples, namely n-type and p-type doping ones deposited at 200°C, peeled off at 600°C. As we increased our annealing temperature, this phenomenon becomes more and more serious. All the samples annealing at 650°C and 700°C peeled off. Fig. 3-10 shows the pictures of the

peeling off samples. As can be observed, the surface was totally damaged and no further investigation is possible to be done on such layer. This peeling off phenomenon may probably caused by the H2 component exists inside the silicon film as we used H2 as dilute gas in the deposition process.

3.3.1 Crystallographic Properties

Fig. 3-11 shows the X-ray diffraction graphs of the three successfully crystallized samples. Three clearly peaks at 28.5°, 47°, 56°, are shown in each of them. And the peaks shown at these angles represent grain orientations of (111), (220), and (311) respectively, which are exactly the same as samples deposited by e-gun. The peak intensities are almost the same in each of them, which can be regarded as they all have the same crystallization fraction. In order to examine the crystallization fraction, we had the TEM picture. By TEM picture (Fig. 3-12) taken from the intrinsic sample deposited at 200°C and annealed at 600ºC for 96 hours we can see the whole a-Si layer was converted into pc-Si. And thus we can conclude that all the three samples are fully crystallized. From the picture we can also see that the surface of pc-Si layer is smooth and most grains are cross the full layer thickness, which is what we want to further grow our epitaxial layer. Most grain sizes are several hundred nm and smaller than 1 μm. As indicated in the Fig. 3-12 (a) by an arrow, there is one clear grain with the grain size about 1000 nm. Lots of planar defects are also visible in these grains as indicated in Fig.

3-12 (b).

Fig. 3-13 shows the intrinsic PECVD a-Si deposited at 200°C after annealing at 600°C for several different time periods. As can be seen in the graph, there is no peak

can be observed after annealing for 12 hours. But after annealing for 24 hours, the crystallization process started, thus we can see the peaks with very small intensity. The peak intensity keep increasing with annealing time and saturated when the whole layer was fully crystallized, which is around 96 hours as can be seen from the graph. Fig.

3-14 and Fig. 3-15 show the X-ray diffraction graph of intrinsic a-Si deposited at 300°C and boron doped a-Si deposited at 300°C respectively. Comparing to Fig. 3-13, there is nothing very different can be observed between each other even between doping and without doping. We only choose four different annealing times to compare the differences between each of them. Of course it is possible to see more detail into the crystallization progress if the time interval is smaller or using in-situ XRD versus time [33].

3.3.2 Electrical Properties

The ρ vs. T measurement is also carried for PECVD samples and shown in Fig.

3-16. The two intrinsic samples both have high resistivity at room temperature, which are around 4 10⁵ to 5 10⁵ Ωcm with slopes very close to each other. These values are

almost the same as intrinsic e-gun samples as shown in Fig. 3-17. From these measurements we may conclude that if the grain sizes of these intrinsic samples are in the same range, then their trapping densities at the grain boundaries could be at the same order of magnitude.

There is an obvious drop of resistivity for the p⁺ PECVD sample (green line in Fig.

3-9). The resistivity is at the order of 10^-3Ωcm at room temperature. The dramatically drop of resistivity is probably caused by high concentration of dopants compensated all

the trapping states at the grain boundaries and further lower the energy barrier at the grain boundaries. Since the resistivity of the highly doped sample at room temperature is in the acceptable range for performing the Hall measurement. It was carried out on the p+ sample by a homemade Hall setup at IMEC, and the results are shown in Table 3-3 including resistivity, sheet resistance, carrier concentration, and Hall mobility. Since there was only one kind of seed layer from SPC can perform the Hall measurement, no further comparison between SPC samples can be made in this work.

3.4 Comparison of the Crystallization Behavior between SPC Seed Layers

Comparing the time dependence X-ray diffraction graphs of e-gun samples (Fig.

3-3 and Fig. 3-8) and PECVD samples (Fig. 3-13, Fig. 3-14, and Fig. 3-15) we can see that a-Si deposited by different techniques do affect the SPC process. Samples prepared by PECVD are all started to crystallize when annealing at 600°C for 24 hours. On the other hands, all the e-gun deposited a-Si only start to crystallize after 48 hours annealing when annealing temperature is elevated to 700°C. From the results above, we may conclude that the a-Si deposited by PECVD is more easily to crystallize than the ones prepared by e-gun evaporation.

In-situ XRD measurements were carried out in Ghent University for further investigation [34]. The results are shown in Fig. 3-18. The summed intensity of the (220) (black line) and (311) (red line) peaks are displayed versus temperature for 1°C/s ramping anneals. For the (220) peak the intensity is summed of the 2θ range 47° to 47.5º, for the (311) peak this was 56° to 56.5º. For intrinsic e-gun (Fig. 3-18(a)) and

PECVD (Fig. 3-18(c)) samples, the figure indicates that Tcryst is788°C and 750°C respectively, indicated by a steep increase of the intensity. Tcryst is defined as the point at which the first derivative of the summed intensity is maximum [34], For boron doped e-gun (Fig. 3-18(b)) and PECVD (Fig. 3-18(d)) samples, the crystallization are more gradual when comparing to intrinsic samples which means their starting point of crystallization is earlier. The Tcryst of 720°C and 705°C for e-gun and PECVD were

PECVD (Fig. 3-18(c)) samples, the figure indicates that Tcryst is788°C and 750°C respectively, indicated by a steep increase of the intensity. Tcryst is defined as the point at which the first derivative of the summed intensity is maximum [34], For boron doped e-gun (Fig. 3-18(b)) and PECVD (Fig. 3-18(d)) samples, the crystallization are more gradual when comparing to intrinsic samples which means their starting point of crystallization is earlier. The Tcryst of 720°C and 705°C for e-gun and PECVD were