Chapter 3 Results and Discussion
3.7 Characterization of Solar Cells Fabricated on AIC and SPC Seed Layers
3.7.3 Comparison between Metal Contamination Involved and not Involved
Since the possible metal contaminations are much lower in the PECVD system, by comparing the PECVD and e-gun SPC seed layers we may obtain the influence of metal contaminations. Since the solar cells fabricated on p+ PECVD seed layers were obviously affected by the highly doped seed layer, we only consider the cells fabricated
on intrinsic PECVD seed layers. From Table 3-9 we can observe the performance of the cells fabricated on intrinsic PECVD seed layers is slightly better than the ones fabricated on intrinsic e-gun seed layers. Since they had approximately the same grain sizes, we believe that this improvement was due to the reduction of metal contamination in the pc-Si material. However, different deposition techniques may also influence the performance due to different film properties. More detailed investigations could be done to make a confirmation of the results.
Chapter 4
Summary and Conclusions
In this work, we have investigated into some different seed layers and solar cells made on different seed layers. These solar cells were fabricated based on a pc-Si layer formed by the two step process, which were seed layer formation and epitaxial growth.
By using this two step process, we can grow larger grain sizes and solely control our crystalline property without considering the effect of doping concentration which is needed in the absorption layer of solar cell. The results and discussion were summarized in this chapter.
From the material examinations, we can see that the boron doping can always facilitate the crystallization process. Also, the obvious difference between the PECVD and the e-gun deposited a-Si in SPC process was observed in this work. The PECVD deposited a-Si layers always start to crystallize earlier or at lower annealing temperature
than the e-gun evaporated a-Si layers. It was caused by the possible oxygen and carbon contamination on our e-gun targets.
We fabricated our solar cells on several different kinds of seed layers, including AIC with metal contamination involved, SPC with metal contamination involved, and SPC with metal contamination not involved. The solar cells made on the AIC seed layers have the highest efficiency about 4.7% with open circuit voltage of 503 mV, short circuit current of 12.9 mA/cm2, and fill factor of 72.4% in this work. This superior performance over solar cells made on SPC seed layers were due to the much larger grain sizes of its polycrystalline silicon body even though metal contamination was involved. The efficiency is 3.5% with open circuit voltage of 486 mV, short circuit current of 9.7 mA/cm2, and fill factor of 73.5% for the solar cells fabricated on SPC seed layers with metal contamination not involved. And the efficiency is 3.1% with open circuit voltage of 469 mV, short circuit current of 9.2 mA/cm2, and fill factor of 72.7% for the solar cells fabricated on SPC seed layers with metal contamination involved. From these values we can see that the performance of solar cells made on SPC seed layers which were metal contamination not involved showed better results than those metal contamination involved. This improvement of the performance is because of the limitation of unwanted metal contaminations among the pc-Si layer.
To sum up, we have proved that the performances of our pc-Si solar cells were not only affected by grain sizes, but also the metal contamination does affect the final performances of our pc-Si solar cells. As a result, an improvement on the performance of our pc-Si solar cells could be done by minimizing the unwanted metal contaminations existing among the pc-Si layer of the solar cells. Also, with the two step process, possible large grain pc-Si solar cells with high efficiency could be expected in the near future.
Doping
Annealing Temperature
Intrinsic p-type
550°C Not crystallized Not crystallized
600°C Not crystallized Crystallized
650°C Crystallized Crystallized 700°C Crystallized Crystallized
Table 3-1 Crystallization results of e-gun deposited a-Si annealing at several different temperatures for 96 hours. The criteria based on whether there was grain orientation peaks appear on X-ray diffraction measurement.
Doping Deposition
Temperature
600°C 650°C 700°C
i deposit at 200°C Crystallized Peeling off Peeling off i deposit at 300°C Crystallized Peeling off Peeling off P+ deposit at 200°C Peeling off Peeling off Peeling off P+ deposit at 300°C Crystallized Peeling off Peeling off N+ deposit at 200°C Peeling off Peeling off Peeling off N+ deposit at 300°C
Table 3-2 Crystallization results of a-Si deposited at 200°C and 300°C by PECVD. The annealing process was carried out for 96 hours at 600°C, 650°C, and 700°C.
Rho (Ωcm) Rs (Ω/sq.) P (cm-3) μH (cm2/Vs)
2.314×10-3 96.414 1.02×1021 2.875
Table 3-3 Results of Hall effect measurement on the p+ pc-Si seed layers (deposited at 300°C by PECVD and annealing at 600°C for 96 hours).
Sample types I PECVD P-type PECVD I ebeam P-type ebeam
Tcryst (°C) 750 705 788 720
Table 3-4 Tcryst values for the in-situ XRD measurement. Tcryst is defined as the starting point of the increase of intensity in XRD graph.
Rho (Ωcm) Rs (Ω/sq.) P (cm-3) μH (cm2/Vs)
1.68 1034.398 1.429×1018 1.531
Table 3-5 Results of Hall effect measurement on the AIC seed layers.
Annealing time
Annealing temperature
96 hours 5 hours
500°C AIC
600°C
(1) Intrinsic PECVD deposited at 200°C (2) P+ PECVD deposited at 300°C (3) P-type e-gun
650°C (1) Intrinsic e-gun (2) P-type e-gun 700°C (1) Intrinsic e-gun
(2) P-type e-gun
Table 3-6. The seed layers listed here are chosen to make epitaxial growth absorber layers and further solar cell fabrication.
Deposition
Table 3-7 Comparison of the illuminated characteristics of pc-Si solar cells fabricated on different seed layers. The values shown in this table are from the best cells.
Voc(max) (mV) Jsc(max) (mA/cm2) FF(max) (%) Eff(max) (%)
450 8.7 71.7 2.8
Table 3-8 The illuminated characteristics of pc-Si solar cell fabricated on fine grain pc-Si without a seed layer. The values shown in this table are from the best cell.
Deposition
Table 3-9 Comparison of the illuminated characteristics of pc-Si solar cells fabricated on different seed layers. The values shown in this table are average results and the standard deviation from this work.
Voc(avg) (mV) Jsc(avg) (mA/cm2) FF(avg) (%) Eff(avg) (%)
449 8.7 71.1 2.8
Table 3-10 The illuminated characteristics of pc-Si solar cell fabricated on fine grain pc-Si without a seed layer. The values shown in this table are the average values and the standard deviation from this work.
Fig. 2-1. Schematic picture of the process flow for the two step thin film polycrystalline silicon solar cell. (a) Preparation of foreign substrates. (b) Polycrystalline silicon seed layer formation. (c) Epitaxial growth on the seed layer. (d) Fabrication of the thin film polycrystalline silicon solar cell.
Fig. 2-2. Schematic picture of the solid phase crystallization process flow for seed layer formation. (a) Preparation of foreign substrates. (b) Deposition of amorphous silicon layer on a foreign substrate. (c) After annealing of the amorphous silicon layer, the amorphous silicon was converted into polycrystalline silicon.
Fig. 2-3. Schematic picture of aluminum induced crystallization process flow for seed layer formation. (a) Deposition of aluminum and amorphous silicon stacked layer on a foreign substrate. (b) Anneal the stacked layer. (c) Remove the top aluminum layer after annealing.
Fig. 2-4. (a) Cross section of interdigitated thin-film Si solar cells. (b) Top view of interdigitated contacts.
Fig. 3-1. XRD graph of p-type e-gun deposited a-Si after annealing for 96 hours at 700°C (green line), 650°C (black line), 600°C (red line), and as-deposited a-Si (blue line).
Fig. 3-2. XRD graph of p-type e-gun deposited a-Si after annealing at 700°C for 96 hours (green line), 48 hours (black line), and 24 hours (red line).
Fig. 3-3. TEM picture of p-type e-gun deposited amorphous silicon layer after annealing at 600°C for 96 hours. (a) The whole amorphous silicon layer was 480 nm. Only the bottom 100 nm was crystallized, the other 380 nm on top remained in amorphous state.
(b) Zoom in to the bottom 100 nm.
Fig. 3-4. TEM pictures of p-type e-gun deposited amorphous silicon layer after annealing at 700°C for 96 hours. (a) The whole layer was 480 nm and was fully crystallized. (b) Lots of defects exist in the layer.
Fig. 3-5. Resistivity versus inverse temperature plots of p-type e-gun deposited a-Si after annealing for 96 hours at 600°C (red line), 650°C (black line), and 700°C (green line).
Fig. 3-6. XRD graph of intrinsic e-gun deposited a-Si after annealing for 96 hours at 700°C (green line), 650°C (black line), 600°C (red line), and as-deposited a-Si (blue
line).
Fig. 3-7. XRD graph of intrinsic e-gun deposited a-Si after annealing at 600°C for 96 hours (red line) and 173 hours (purple line).
Fig. 3-8. XRD graph of intrinsic e-gun deposited a-Si after annealing at 700°C for 96 hours (green line), 48 hours (black line), and 24 hours (red line).
Fig. 3-9 Resistivity versus reverse temperature plots of intrinsic (red lines) and p-type (blue lines) e-gun deposited a-Si after annealing for 96 hours at 700°C (with circle marks) and 650°C (with triangle marks).
Fig. 3-10. Pictures of n-type a-Si deposited at 200°C by PECVD after annealing at 600°C for 24 hours. Serious peeling off phenomenon can be seen all over the surface.
The left picture is a whole image of a 5 cm by 5 cm sample. The right picture is the
zoom in.
Fig. 3-11. XRD graph of p+ (green line) and intrinsic a-Si deposited by PECVD at 300°C (black line) and 200°C (red line) after annealing at 600°C for 96 hours. Blue line shows the as-deposited a-Si.
Fig. 3-12. TEM picture of intrinsic PECVD deposited amorphous silicon layer after annealing at 600°C for 96 hours. (a) The whole layer was 420 nm and was fully crystallized. (b) Lots of defects existed in the layer.
Fig. 3-13. XRD graph of intrinsic a-Si deposited at 200°C by PECVD after annealing at 600°C for 96 hours (green line), 48 hours (black line), 24 hours (red line), and 12 hours (blue line).
Fig. 3-14. XRD graph of intrinsic a-Si deposited at 300°C by PECVD after annealing at 600°C for 96 hours (green line), 48 hours (black line), 24 hours (red line), and 12 hours (blue line).
Fig. 3-15. XRD graph of p+ a-Si deposited at 300°C by PECVD, annealing at 600°C for 96 hours (green line), 48 hours (black line), 24 hours (red line), and 12 hours (blue line).
Fig. 3-16. Resistivity versus reverse temperature of PECVD deposited a-Si after annealing at 600°C for 96 hours. The black line represents the intrinsic sample deposited at 300°C. The red line represents the intrinsic sample deposited at 200°C. The green line represents the p+ sample deposited at 300°C.
Fig. 3-17. Resistivity vs. reverse temperature of intrinsic samples annealing for 96 hours.
E-gun sample annealed at 650°C (blue line), E-gun sample annealed at 700°C (green line), and 600°C annealed PECVD samples deposited at 300°C (black line) and 200°C (red line) are showed.
Fig. 3-18. Summed intensity versus ramping temperature derived from in-situ XRD [34].
The black line represents the peak intensity at (220) orientation, and the red line represents the (311) orientation. (a) intrinsic e-gun, (b) p-type e-gun, (c) intrinsic PECVD (deposited at 200°C), (d) p-type PECVD (deposited at 200°C).
Fig. 3-19. XRD graph of the AIC seed layer.
Fig. 3-20. IPF EBSD measurements (using the Z direction perpendicular to the sample surface) of AIC seed layers. The areas of 80×80 μm2 were examined with a step size of 0.1μm.
Fig. 3-21. Resistivity versus reverse temperature plots of the AIC seed layer.
Fig. 3-22. XRD graph of the epitaxial growth layer grown on SPC seed layer. The SPC seed layer is p-type e-gun evaporated a-Si layer annealing at 700°C for 96 hours.
Fig. 3-23. XRD graph of the epitaxial growth layer grown on AIC seed layer. The AIC seed layer was annealing at 500°C for 5 hours.
Fig. 3-24. Illuminated current voltage curve of the best pc-Si solar cell in this work made on p-type e-gun seed layer which was annealed at 700°C for 96 hours.
Fig. 3-25. Illuminated current voltage curve of the best pc-Si solar cell in this work made on p-type e-gun seed layer which was annealed at 650°C for 96 hours.
Fig. 3-26. Illuminated current voltage curve of the best pc-Si solar cell in this work made on p-type e-gun seed layer which was annealed at 600°C for 96 hours.
Fig. 3-27. Illuminated current voltage curve of the best pc-Si solar cell in this work made on intrinsic e-gun seed layer which was annealed at 650°C for 96 hours.
Fig. 3-28. Illuminated current voltage curve of the best pc-Si solar cell in this work made on intinsic e-gun seed layer which was annealed at 600°C for 96 hours.
Fig. 3-29. Illuminated current voltage curve of the best pc-Si solar cell in this work made on p+ PECVD seed layer which was annealed at 600°C for 96 hours.
Fig. 3-30. Illuminated current voltage curve of the best pc-Si solar cell in this work made on intrinsic PECVD seed layer which was annealed at 600°C for 96 hours.
Fig. 3-31. Illuminated current voltage curve of the best pc-Si solar cell in this work made on AIC seed layer which was annealed at 500°C for 5 hours.
Fig. 3-32. Illuminated current voltage curve of the pc-Si solar cell made on fine-grain pc-Si without a seed layer.
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