Thesis Organization

This thesis is organized into five chapters.

Chapter 1, the goal and motivation for our implementation are introduced briefly.

In Chapter2, we will introduce the concepts about the switched capacitor filter.

The basic operation and common architecture would be illustrated. It includes the building blocks of the switched capacitor, like switches, capacitors and amplifiers, and the integrator, the most important block for the switched capacitor filter.

Chapter 3 would describe the high performance switched capacitor filter design.

In this thesis, we focus on low voltage low distortion design. There are several techniques for low voltage introduced, like clock boosting, switch opamp and bootstrapped switch. Then we will also introduce some researches about the low distortion design. There are some design considerations which should be noted.

Chapter 4 focuses on our design. We will introduce the bootstrapped switch in detail and its compensation for the higher performance. Then we propose a novel structure for less nonlinearity. Finally, we would like to realize a low voltage low distortion high speed filter. At low voltage, the amplifier is hard to high bandwidth.

The lower bandwidth would constraint clock rate. However, lower clock rate

sometimes result in more high distortion. Besides, we also suppress the distortion by means of the filter structure. The whole chip simulation is used TSMC 0.18um CMOS technology.

Chapter 2

Fundamentals of Switched Capacitor Circuits

2.1 Introduction

A switched capacitor circuit acts like a discrete-time signal processor. Thus it is also easily analyzed with using z-transform. The switched capacitor circuits are so popular for the filter design due to good linearity and dynamic range of the accurate frequency response. The frequency response accuracy is determined by capacitor ratio which can be set quite precisely. This is because the process has a good match on silicon area. The area error often can be suppressed on the order of 0.1 percent. The other factor would affect the accuracy is clock frequency. Fortunately, clock

frequency can be realized precisely with using a crystal oscillator. In this chapter, we will introduce the basic building block of the switched capacitor circuits.

2.2 basic switched capacitor building blocks

In this section, we will introduce the basic block in the SC filter. Good understanding of these blocks can make designer complete a successful design.

2.2.1 Clock generator

The clock signals could be generated by the scheme shows figure 2.1.

The nonoverlapping clock is essential in switched capacitor circuits. The two logic signal (Φ1,Φ2) would not both be high in the meanwhile. Φ1a andΦ2a are slighter than Φ1 and Φ2, respectively, for the purpose of alleviating charge injection error

[6] [11] and leakage.

Figure 2.1 Clock generator

2.2.2 Capacitor

The capacitor is largely used in analog CMOS circuit design. For capacitor design, several parameters are critical: nonlinearity, parasitic capacitor (accuracy) and density. Nonlinearity means the quiescent voltage dependence. The capacitor with less voltage dependency would contribute less harmonic distortion. Parasitic capacitor would affect the accuracy of the capacitor. In SC filter, it would make the corner frequency drift and gain vary. Density equals the capacitance per area by the capacitor.

Large density can cost us smaller area to reach the desired capacitance.

Traditionally, a highly linear capacitance in an integrated circuit is constructed by two silicon area (double poly capacitors). The desired capacitor is formed by the intersection between two silicon layers. By growing a thin oxide between two conductive layers, it usually accompanies with 20% bottom plate parasitic capacitor.

The metal-insulator-metal (MIM) capacitor is often used in the modern analog circuits design. It is formed by two conductive mental layers and a PCB layer between them. It has a high density and a lower parasitic capacitance. The capacitance is defined by the intersection area and dielectric layer thickness. Under the threshold voltage, it can isolate the DC signal to hold the charge energy. In recent years, many researches about MIM capacitor focus on developing a high dielectric constant material [6].

2.2.3 MOS sampling switch

In the common SC filter, we use single MOS transistor for sampling switch. It is shown in figure 4.2. For NMOS device, when the clock goes high, the transistor would be turn on and the output signal would track the input signal. It is assumed that the voltage of the capacitor equals zero initially. The transistor works in saturation region under the condition Vds >Vgs – Vt. Until Vds< Vgs-Vt, the transistor would enter the triode region. It would be stable in deep triode region when output signal nearly equals input signal. Thus it would result in a simple sampling switch with a high accuracy.

Figure 2.2 A simple sampling switch

Unfortunately, there are some errors which are charge injection and clock feedthrough. As we know, the transistor must produce an inversion layer, as to as charge channel, into working. When the transistor is closed, the channel would disappear and the channel charge would be released out. The released charge would flow to drain and source. The charge on the capacitor would also be affected. The total channel charge is expressed byQ_ch

≈

WLC_ox

(

V_DD

−

V_in

−

V_th

)

. In the most case, the channel charge is often assumed to be divided by drain and source. But the real mechanism is very complicated. Now the error by charge injection equals

H

th in DD ox

C

V V V V WLC

2

)

( − −

=

∆ we can find large transistor size and smaller sampling capacitor would produce larger error. Another error source is clock feedthrough. It is induced by gate-drain and gate-source overlap capacitance. Clock feedthrough would happen on the clock transition. When signal goes high, the overlap capacitance would

be charged to clock voltage (Vck). When the signal goes down, the charge saved by capacitance would be released. The sampled output voltage would be affected. The error can be represented by

H ox

ox

CK

WC C

V WC

V

= +

∆ [6] [7].

2.2.4 opamp

In most case, the analysis of SC circuit operation is based on ideal amplifier. It can simplify the analysis and make the SC circuit well understood. But in reality, the amplifier is usually most important component. The whole performance is often dominated by the amplifier design. The adequate amplifier design would make the SC filter successful. Now there are some merits about the amplifier performance would be discussed.

Gain is often first considered by the amplifier design. The gain determines the precision of the system applying a negative feedback amplifier. The larger gain is able to raise the accuracy of the SC filter. Besides, the high gain is also necessary to

suppress the harmonic distortion and result in a fast settling time. In the common case, the open loop gain typically ranges from 40dB to 80dB.

Unit gain bandwidth and phase margin would dominate the linear settling

behavior of the amplifier. Larger unit-gain bandwidth and phase margin can make the circuit stable quickly. There is a thumb rule that the unit gain bandwidth is often five times than clock frequency at a unit gain SC integrator and the amplifier is with 70 degrees.

Another factor would affect the settling time is slew rate. The clock rate and total capacitance would be limited by the slew rate. Insufficient slew rate would not transfer the charge from the capacitor to another. The less capacitance is often less accuracy.

Output impedance is often needed more attentions in the SC circuit. The

amplifier is often loaded by pure capacitive loading. The larger impedance would reduce the unit-gain frequency. Thus the circuit may not be settled quickly [6].

2.3 Switched capacitor integrator

The basic integrator is widely used in the SC circuit. A basic integrator is shown in figure 2.3 the Φ1and Φ2 are nonoverlapped signal that means they are not turn on in the meanwhile.

Figure 2.3 A basic integrator

Assuming the integrator output voltage defined as Vout(nT-T) that means the charge on C2 equals C2Vout(nT-T). At the time (nT-T), SW1 is just turn off before SW is turn on. The charge on C1 equals C1Vin (nT-T). When SW2 is on, the charge on the C1 would be totally transferred to C2 because the negative input is virtually ground. Note that if a positive signal is applied on the input, it will result in a negative voltage on C2. The architecture is called inverting integrator. Thus we can find the charge equation at Φ2 end

2 _co

( / 2)

2 _co

( )

1 _ci

( )

C V nT

−

T

=

C V nT

−

T

−

C V nT

−

T

We also can find the negative sign says that the integrator is an inverting

integrator. Like above, we also would like to derive the charge equation at Φ1 end. the charge on C2 at the end of the next Φ1 equals that at time (nT-T/2). It means that

2 _co

( )

2 _co

(

C V nT

=

C V nT

−

T ) The charge equation can be expressed by

2 _co

( / 2)

2 _co

( )

1 _ci

( )

C V nT

−

T

=

C V nT

−

T

−

C V nT

−

T

We use V n_i

( ) =

V nT_ci

( )

andV n_o

( ) =

V_co

(

nT

)

. Thus we can find the discrete-time

relationship.

Now we can derive the transfer function

1

Unfortunately, as we mentioned before, the capacitors are often with parasitic

capacitance. In addition, the switches also have nonlinear capacitance. The figure 2.4 shows a basic integrator with parasitic capacitance. and represent the top and bottom capacitance of . and represent the top and bottom capacitance of

. Because two ends of and connecting virtual ground node and ground node, respectively, there is little charge that would be stored. Thus their effects are often discarded. In addition, is just an extra loading for the amplifier. So it would affect the speed of the amplifier but not affect the accuracy of the output voltage. Finally, is parallel with . Then it would be also sampled signal like

. The sampled charge would be released on the next state and accuracy would be affected. To overcome this problem, the parasitic insensitive integrator is proposed [6]

[8] [9].

Figure 2.4 The integrator with parasitic capacitors

Parasitic insensitive integrator

Figure 2.5 shows a parasitic insensitive integrator. It can simply reduce the parasitic capacitance error by adding two extra switches. It has a difference from that we mentioned before which is a noninverting integrator. During 1

φ

, the capacitor C1 would sample the input signal Vi and the charge would be transferred to C2 on 2

φ

. We note the positive end of the capacitor is connected to ground node. This is why we called it is noniverting. When the input signal is positive, the opamp would contribute a positive signal on C2, with the phase as the same as input signal. Now we can find its transfer function as

1

Figure 2.5 A noniverting integrator

Now we add the parasitic capacitance for analyzing. As we noted before, only would affect the integrator accuracy. Now we can find would still sample the input signal on

1

Cp C_p1

φ

1, but it would be discharge to ground on 2

φ

. Unlike before, the switch with one end connected to ground would provide a path to ground for

discharging. The parasitic voltage would be charged to C2. It also would not affect the operation [6].

The figure 2.6 shows an inverting parasitic insensitive integrator. It is realized just

by changing the clock of the switches. The integrator is fundamental and important in the SC filter. It is essential to understand it completely.

Figure 2.6 An inverting integrator

2.4 Biquad Design [6]

There are many structures in the switched capacitor. The well-known one is biquad. Many complex filter is achieved by cascading the biquads. It is because the second biquad is often stable and realized easily. More flexibility for parameters is also why it is so popular. Before we introduce the biquad design, we often need the signal flow analysis. It is very useful in the biquad design. (Figure 2.7).

) 1

( 1

−1

− Z

C

Figure 2.7 Z-transformation signal flow

2.4.1 Low-Q biquad

The general transfer function of the continuous time biquad can be expressed by

2

Then we can organize it into

_{out in}

s w V

_in Now the two equations are described in the figure2.8.

Figure 2.8 Continuous time signal flow

Then we can realize the RC biquad based on the signal flow. It is shown in figure 2.9.

Figure 2.9 A low Q RC continuous time RC filter

Finally, we substitute all resistors into the combination of switch and capacitor.

The switched capacitor biquad is shown in figure 2.10.

Figure 2.10 A low-Q switched capacitor biquad

Using Z-transform signal flow analysis that we mentioned before, the transfer function is given by

1

2.4.2 High-Q Biquad Filter

Using the same way, we also can complete a high Q circuit. We just reorganize Now a new continuous time signal flow is obtained in figure 2.11

Figure 2.11 an alternative continuous time signal flow Like before, we also can derive a continuous time RC filter (figure 2.12)

Figure 2.12 A High-Q continuous time RC filter

We substitute all resistors into switches and capacitors. It is shown in Figure 2.13

Figure 2.13 High Q switched capacitor biquad Once again, using the Z-Transform, the transfer function is given by

) design a continuous time filter. Then it can be converted into discrete time filter or digital filter. The Z-transformation provides a concrete solution.

Chapter 3

High Performance Switched Capacitor filter technique

3.1 Introduction

In this chapter, some modern circuit design techniques for high performance are illustrated. The characteristics of lower power supply, distortion and noise are all what we desired. Besides, in order to let the filter applied on communication system, we need to implement a wide band filter. Undoubtedly, the appropriate amplifier design is also very important, especially with a heavy loading. We will introduce what problems we may meet and their proposed solutions for pursuing high performance.

3.2 Low voltage SC circuit design

In analog circuit, dynamic range is often an important index to evaluate the analog circuit performance. In order to achieve high enough SNDR, a large signal swing range is necessary. But as we mentioned before, the signal swing of the MOS sampling switch would be restricted linearly by power supply. The low supply voltage would result in a smaller signal swing that makes dynamic range decrease and thus it is not expected. One solution for this is providing two power supplies, the higher one for the analog circuits and the lower one for the digital circuits. The disadvantage is needed a larger cost because we need to use different CMOS process. Thus there are several solutions in circuit design will be showed below [5].

3.2.1 Clock boosting

Clock boosting is a well known and straight forward approach to solve this problem. The reason for smaller signal swing is the reducing clock voltage. Thus we just boost our clock signal to enlarge the swing range.

The voltage doubler is often used [12] [13] [14]. (Figure 3.1) It is mainly formed by two N-type transistors, capacitors and an inverter. The cross-coupled transistors would alternatively be charged the capacitors to Vdd. Input clock is an ordinary periodic clock. After several periods, two capacitors would be both charged to Vdd. The output voltage of the inverter would be pumped a Vdd by C2. Now the ideal output signal would be 2Vdd. This cell is usually called “charge pump”. This idea is usually widely used in voltage boosting. When the input signal is high, M4 would discharge the gate of the sampling switch to ground. The output clock would be determined by

G p DD

H C C C

V C

V = + +

2

2 2

Cp is the parasitic capacitor of , and is the gate capacitance oh the MOS sampling switch. But clock boosting often results in another problem that it would make the junction voltage exceed a Vdd. The junction breakdown issue is needed to be overcome especially in low threshold voltage process.

C

2

C

_G

VH

VDD

3.2.2 Switch opamp technique

This is a method that allows the circuit operating in low voltage condition without any clock boosting [14] [15]. The system is really operating in low voltage without any junction breakdown problems. The basic concept is illustrated in

figure3.2 (a) shows the standard SC integrator. (b) shows an switch opamp integrator.

The difference between two architectures is that switch opamp integrator operates without any floating sampling switch (S1). The original switch sampling function is replaced by a switch opamp and a switch with one end connected to ground. Thus the signal swing would not be constrained by inefficient clock voltage. They can operate in 1V level with a typical threshold voltage that equals 0.7v. During

Φ 1

, the previous output is valid. The capacitor (C1) would be sampled the input signal. During , the charge of C

Φ 2

1 would be transferred to C₂, and node A would also be reset to ground. In the meanwhile, the previous opamp would be switched off to avoid any conflict caused on the output. The opamp would be on or off alternatively. This is why it is called switch opamp. It overcomes the junction breakdown issue and benefits lower power. But the shortcoming of this architecture is much more complicated. It is not suitable for the analysis from the standard switched capacitor integrator. Besides it is often just used in low speed system because the opamp needs time to recover from

“off” state to “on”state. With the comparison to standard switched capacitor circuit, it often has worse performance like linearity and noise.

Figure 3.2 (a) standard integrator

(b) switched opamp integrator

3.2.3 Bootstrapped switch

Bootstrapped switch is a solution like clock boosting. The fundamental

operating concept is illustrated in figure 3.3. The sampling switch would be driven by a constant gate-source voltage. First the capacitor would be charged to Vdd. Then the input signal would be pumped by a Vdd. The gate voltage would be zero during

“off“ state and Vsig+Vdd during “on” state, respectively. The turn-on resistance of a MOS switch is independent on input signal because of fixed Vgs and it would make the harmonic distortion decrease. But the high junction voltage may cause the breakdown. This technique is often with the reliability

Figure 3.3 Bootstrapped switch concept

3.2.4 A low voltage integrator design

For a SC filter, the problem what we meet is only signal swing that would be reduced by sampling switch. The signal amplitude is also restricted by the amplifier.

Fortunately, we can solve this problem by adequate bias voltage. It is illustrated in

figure 3.4 means virtual ground, usually equaling to /2 and is the bias voltage making amplifier work properly. Assuming there is no input signal applied, the capacitor would have a voltage drop,

Vgnd

V

_DD

V

_B

gnd

B V

V

−

, in the steady state. Since no net charge is transferred, also has the same voltage drop. If the integrator needs to work in low voltage, should be set close to for working properly. The output of the amplifier can be set to /2 to achieve maximum swing [16].

C

F

V

B

V

_DD

V

DD

V

_in

V

_out

V

_B

V

_B

C

_F

Figure 3.4 A low voltage integrator

3.2.5 Multi-threshold voltage process

Many advanced process would provide multi-threshold voltage device. The reason we need multi-threshold voltage is that, as we mentioned before, the analog circuit needs smaller threshold voltage for large signal swing. But the device with small threshold voltage would contribute larger leakage current. It would directly impact the digital circuit performance even result in failure. So the higher threshold voltage device is often used for digital circuits and the lower one is for analog circuits.

In addition, multi-threshold voltage process also means a larger cost [7].

3.3 Low distortion SC circuit design

3.3.1 Distortion mechanism

The distortion may be caused by any component in switched capacitor circuit.

Before we introduce the design technique for low distortion switched capacitor circuit, it is essential to understand the distortion how to be generated [17].

A. Capacitor Nonlinearity

We often discuss the distortion in an integrator. This is because SC circuit seldom uses an amplifier without negative feedback. A single-ended SC integrator is shown in figure 3.5. The charge equation can be expressed by

)

We assume all nonideality is only contributed by the capacitor and other components

)

We assume all nonideality is only contributed by the capacitor and other components

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