On-Chip Buffer - The implementation of channel select filter

Chapter 4 The implementation of channel select filter

4.5 On-Chip Buffer

In order to push the pad, the output buffer is needed. In normal case, the source follower is often used. But in the low power supply, the signal would be reduced.

There is a solution which is using higher power supply. But it may affect the

distortion of the output signal. In our design, the output buffer is just like the amplifier in the biquad but just single end. This is because the signal swing would not be

reduced by output buffer and would not result in much distortion..

Figure 4.12 Output Buffer

4.6 The post simulation result of the filter

Figure 4.13 shows the output signal of the filter at input signal with frequencies being 50k 200k 800k 1500k 2000k 2300k 2500k, respectively. The input signal swing is 1.2Vpp because we set the input common mode close to Vdd. The red and blue lines mean the output signal and input signal, respectively. The output signal with frequency over 2MHz would be attenuate rapidly. The specification of the filter is shown in Table 4.4. The in-band signal with frequencies which equals 50kHz, 100kHz, 200kHz, 300kHz, 400kHz, 700kHz, 900kHz, 1000kHz is analyzed with Fourier series.

It shows the THD is about -47db at 1000k Hz. Figure 4.14 shows FFT of the output signal at input signal with various frequencies. The FFT shows the SFDR are about -60db and -50db at input frequencies with 996k Hz and 1.89Meg Hz, respectively.

Figure 4.13 The output signal of the filter at various input signal frequency

Table 4.4 The specification of the filter

Specification Result

Process TSMC 0.18µm Mixed-Signal

Power supply 1.5V

Filter type 6th order elliptic low pass filter

Corner frequency 2MHz

Signal swing 1.2Vpp

Area 1.082 mm*1.107mm

THD(1.2Vpp) -65db@50k -63db@100k

-55db@200k -54db@300k -50db@400k -47.2db@700k -48.2db@900k

-47db@1000k

Power consumption 66.1327mW

(a) 117k Hz

(b) 195k Hz

(d) 996k Hz

(e) 1.894Meg Hz

Figure 4.14 FFT of the output signal at input signal with various frequencies

Output Buffer

Capacitor

Amplifier

Clock generator

Sampling switch Biquad circuit

Clock line

Figure 4.15 Layout of the channel selection filter

Chapter 5 Conclusions

5-1 Summary

With the constraint of device speed, its application mostly focuses on voice band. In recent years, the mobile communication product is a strong driving force for high speed filter, especially need for high bit rate in 3G generation. The direct

conversion is a concrete solution for highly monolithic integration and multi-standard.

The channel selection is realized in analog circuit with using the wide band switched capacitor filter.

In this thesis, a 1.5v 20MHz low distortion channel selection filter with 2MHz passband for UMTS is completed. It can maintain the output distortion under -65db at input signal with 50 KHz. We use a novel sampling switch for higher linearity and reduce distortion of the integrator. In the integrator, the most important

implementation is the amplifier design. We use the two-stage structure common in switched capacitor filter, because of less output resistance to large capacitance, high gain for both less distortion and high accuracy and high slew rate for suppressing nonlinearity .

5.2 future work and challenge

A 1.5V low distortion channel selection filter is obtained in this thesis. A large swing with low distortion can result in a high dynamic range. In addition, the high DR is often obtained with high OSR. The two-stage structure results in low bandwidth which limits the upper clock rate but suitable for low voltage. The rail-to-rail

amplifier with large bandwidth is essential in the low voltage analog circuit design.

The low distortion structure is also need in the low power supply, especially in low over-sampling ratio.

BIBLIOGRAPHY

[1] W.Aloisi, G. Giustolsis, and G. Palumbo, “Exploiting the High-Frequency Performance of Low-Voltage Low-Power SC filters” IEEE Transactions on Circuits and Systems-II, Vol.51, No.2,Feburary 2004.

[2] L.Maurer, W. Schelmbauer, H. Pretl, B. Adler, A.Springer, R.Weigel “On the Design of a Continuous-Time Channel Select Filter for a Zero-IF UMTS Receiver”, [3] Paul J. Chang, Ahmadreza Rofougaran and Asad A. Abidi, “ IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May 1997

[4] Kuo-Chiang Hsieh, Paul R.Gray, Daniel Senderowicz and David G..

Messerschmitt “, A low noise chopper stabilized differential switched capacitor filtering technique”, IEEE Journal of Solid-State Circuits, Vol. SC-16, No, May 1999 [5] Asad A.Abidi, “Direct-Conversion Radio Transceivers for digital communication”

[6] W.C. Black, D. J. Allstot, S. Patel and J. Weiser, “ A high performance low power CMOS channel filter”, IEEE Journal of Solid-State Circuits, Vol. SC-15, Dec. 1980 [7] David A.Johns and Ken Martin, “Analog Integrated Circuit Design”, John Wiley

& Sons, Inc., 1997.

[8] Razavi, “Design of analog CMOS integrated circuits”, McGraw Hill, 2001 [9] J. T. Caves, M. A. Copeland, C. F. Rahim and S. D. Rosenbaum “Sampled-Data filters using switched capacitor as resistor equivalents,” IEEE Journal of Solid-state Circuit, Vol.SC-12, pp. 592-600, December 1977.

[10] D.L. Fried. “Analog Sampled-Data Filters,” IEEE Journal of Solid-state Circuit, Vol. SC-7, pp. 302-304, August 1972

[11] K. Martin “New clock feedthroigh cancellation technique for MOS switched capacitor circuits”, Electron. Lett., vol. 18, no. 1,pp. 104-106, Februrary 1987

[12] U. Moon, G. Thems, E. Bidari, M. Keskin, L.Wu, J.Steensgaard, F. Maloberti

“Switched Capacitor Circuit Technique in Submicron Low-Voltage CMOS”

[13] Jieh-Tsorng Wu and Kuen-Long Chang “MOS Charge Pump for Low Voltage Operation” IEEE Journal of Solid-state Circuit, Vol.33, No.4, April 1998.

[14] 鄭光偉 “一伏十位元 CMOS 導管式類比數位轉換器” 台灣大學電機工程研究所碩士論文

[15] Jan Crols and Michel Steyaert “ Switched- opamp: An Approach to Realize Full CMOS Switched Capacitor Circuits at Very Low Voltage Circuit at Very Low Power supply Voltage ”, IEEE Journal of Solid-State Circuit, Vol. 29, No.8, August 1994.

[16] W.aloisi, G.. Giustolisi and G.. Palumbo “Exploiting the High Frequency Performance of Low Voltage Low Power SC filters”, IEEE Transactions on Circuit and Systems-II: Express Briefs, Vol.2, February 2004.

[17] Kuang-Lu Lee and Robert G. Meyer, “Low Distortion Switched Capacitor Filter Design Techniques”, IEEE Journal of Solid-State Circuit, Vol. sc-20, No.6, December 1985.

[18] G. Nicollini, A. Nagari, P. Confalonieri and C. Crippa, “-80dB THD, 4Vpp switched capacitor filter for 1.5V battery-operated systems”, IEEE Journal of Solid-State Circuits, Volume 31, No. 8, August 1996

[19] A. M. Abo and P. R.Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Volume 34, Issue 5, pp.599-605, May 1999

[20] J. Steensgaard, ”Bootstrapped low-voltage analog switches,” Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Volume 2, pp.29- 32, May 30 – June 2, 1999.

[21] A. K. Ong, V. I. Prodanov, and M. Tarsia, “A method for reducing the variation in “on” resistance of a MOS sampling switch,” Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Volume 5, pp.437 – 440, May 2000.

[22] Kim Sangwook and Greeneich, “Body effect compensated switch for low voltage switched-capacitor circuits,” Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, Volume 4, pp.437-440, May 2002.

[23] S. R. Sonkusale and J. Van der Spiegel, “A low distortion MOS sampling circuit,” Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, Volume 5, pp.585-588, May 26-29, 2002.

[24] Chun-Yueh Yang and Chung-Chih Hung, “A low voltage low distortion MOS analog switch ” Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, May 2005

[25] Mohamed Dessouky and Andreas Kaiser, ” Very Low Voltage Digital-Audio delta sigma Modulator with 88-dB Dynamic Range Using Local Switch

Bootstrapping”, IEEE Journal of Solid-State Circuits, Vol.36, No.3, March 2001.

[26] Mohamed Dessouky and Andreas Kaiser, “Input switch configuration suitable for rail to rail operation of switched opamp circuits”, IEEE electronics letter 7^th, January 1999, vol.35 no.1

Appendix 1 Accepted paper

[1] Chun-Yueh Yang and Chung-Chih Hung, “A low voltage low distortion MOS analog switch ”, Proceedings of the 2005 IEEE International Symposium on Circuits and Systems, May 2005

[2]Chun-Yueh Yang and Chung-Chih Hung

“A Reliable Low-Voltage Low-Distortion MOS Analog Switch”, IEICE electronics letter, February 2006

A Low-Voltage Low-Distortion MOS Sampling Switch

Chun-Yueh Yang

Department of Communication Engineering &

Innovative Packaging Research Center National Chiao Tung University

Hsinchu, Taiwan

Chung-Chih Hung

Department of Communication Engineering &

Innovative Packaging Research Center National Chiao Tung University

Hsinchu, Taiwan Abstract—In order to reduce distortion due to variation of the gate

overdrive and the threshold voltage, a novel low-voltage constant-resistance sampling switch is proposed in this paper. The technique to reduce nonlinearity can be used in a high resolution sample and hold circuit. TSMC 0.18um standard CMOS technology is utilized in this research. Results indicate that much lower Total Harmonic Distortion (THD) is achieved by the proposed circuit. The low THD meets the requirements in the application of the low-voltage low-distortion switched-capacitor circuits.

I. INTRODUCTION

In the modern system design, the voltage limitation of the technology indicates the analog circuit must operate in the same or comparable low voltage as the digital circuitry.

Digital circuit can benefit from size scaling down to achieve low power and smaller silicon area, but it has become increasingly difficult to design an analog circuit at low voltage. For high resolution Analog to Digital converter (A/D), a high performance Sample and Hold (S/H) circuit is needed. The dynamic performance of the S/H circuit usually limits the overall dynamic range of A/D. In order to achieve high enough SNDR, a full swing range is necessary.

Unfortunately, the traditional CMOS analog switch is not suitable for rail-to-rail swing at low voltage supply.

Therefore, a bootstrapped switch was introduced to achieve the rail-to-rail operation and low distortion [1]. However, the variation in the “on” resistance of the switch dominates the distortion performance. Several techniques for mitigating the variation of “on” resistance were also proposed [2][3]. This paper proposes a novel sampling switch circuit to eliminate the nonlinearity by keeping the gate overdrive and the threshold voltage constant.

This paper is organized as follows. Background of sampling switches is presented in the next section. Then, various techniques proposed previously to hold the “on” resistance constant are illustrated. Section IV shows the proposed sampling switch whose resistance can be held constant by resistible to variation of the gate overdrive and the threshold voltage. The performance of the proposed switch is shown

in Section V. Finally, the conclusion of this paper is provided in Section VI.

II. BACKGROUND

Figure 1 shows a basic S/H circuit. When Ø is high (usually Vdd), the switch will be turned on and the capacitor will be charged to Vin. When Ø is low, the switch will be turned off and the capacitor will hold the sampled voltage. Its resistance is given by

1

There are some obvious drawbacks in this sampling switch.

The sampling switch output is limited to Vdd -Vt. If Vin >

Vdd -Vt, the output voltage would be saturated and the incorrect voltage would be sampled. It would not have a full swing range. Besides, the resistance would vary with the input signal from Equation (1). It may donate larger harmonic distortion. The body effect also contributes nonlinearity, especially at low voltage. Therefore, the bootstrapped switch was proposed to solve the full swing problem and variation of the switch resistance.

III. BOOTSTRAPPED SWITCHES AND RELATED COMPENSATION TECHNIQUES

From Equation (1), to obtain constant resistance, the gate to source voltage should be held constant during the “on” state.

Vin

Figure 2 shows the principle of the bootstrapped switch [2]

and the circuit realization is shown in [1]. During the “off”

state (SW3, SW4 and SW5 on), the capacitor would be charged to Vdd and likely act as a floating battery to bootstrap the gate voltage when the “on” state (SW1, SW2 on) . It is assumed the input terminal of the sampling switch would be source. Therefore, the resistance of the switch is given by

Clearly, it can be independent of input signal to reduce harmonic distortion. However, the MOS switch is bidirectional and symmetric. The source and drain terminals may interchange depending on the input signal and previous sampled voltage. If the input signal is larger than previous sampled voltage, the source and drain terminal would be interchanged. Therefore, the source voltage is not Vin but sampled voltage in the previous state. Then, Vgs is not ”Vdd”. We can not maintain Vgs constant. Another distortion source of threshold voltage variation from body effect still donate large distortion, especially in low power supply. Therefore, the body effect compensated switch was proposed in [2] [3]. The main idea behind [2] is to use direct connection from source to bulk to avoid the body effect during “on” state. This is a straightforward idea, but the real source is not always the input terminal in practice.

And if the source of the P-type transistor is not highest voltage of all terminals, it may cause the latch-up problem [5]. Of course, Vsb also does not remain zero when the real source is not the input terminal of the sampling switch.

Another technique was proposed to use a replica transistor to cancel the threshold voltage [3], as shown in Figure 3. It is modified from a typical bootstrapped switch. It creates a

threshold voltage as the same as the one sampling switch and cancel each other to be deprived of body effect. It is derived as follows. The drain current of MD in saturation is given by

The drain current is constant by ignoring the second-order effect. Then we can find

The gate voltage of the sampling switch would be equal to

G d

V

_d . Substituting Equation (4) into Equation (1) and assuming Vs equals Vi, Ron can be obtained as following.

From Equation (5), all the parameters of the resistance are constant, but this circuit still suffers from the problem described previously, where the source terminal might be

the input. In practice, the Vt of the sampling switch and replica would not match exactly due to the second order effect and process variation. It is difficult to be compensated completely. The input signal is also needed to decrease by a threshold voltage to make sure the replica transistor in saturation. Another circuit was proposed to modify this drawback of smaller swing range in [4].

IV. THE PROPOSED CIRCUIT Through the above discussion, a key point is that a “source follower” is needed to track the “real source” connecting the charged capacitor and maintaining the gate overdrive to be a constant voltage ”Vdd”. Figure 4 shows the proposed circuit.

The sampling switch is composed of a comparator and several switches. Besides some necessary switches of a typical bootstrapped sampling switch, additional switches SW6 and SW7 are added. To ensure rail to rail swing, SW6 and SW7 are made of complementary switches. The comparator is used to trigger SW6 and SW7 to make the bulk connect to the real source terminal. The bulk is guaranteed to connect to only one terminal, the source terminal, during the “on” state. We adopt the structure of direct connection between source and bulk because it has less nonlinearity and large input swing than using a replica.

In the standard CMOS technology, the sampling switch should be P-type. Two cases are discussed in the following where Vin represents input signal and Vout represents the voltage sampled in the “on” state.

Case 1: When Vin > Vout, the real source is the input terminal. During “off” state (SW2, SW3, and SW5 on), the capacitor would be charged to -Vdd. During the “on” state (SW1 and SW4 on), the comparator output will be low to turn on SW6 to make a connection between the input and

bulk because input voltage is higher than Vout . And the gate voltage of switch equals Vin - Vdd. Then the gate overdrive (Vsg) and Vsb exactly equals Vdd and zero respectively, during the “on” state.

source in

Case 2: When Vin < Vout, the real source terminal should be the output terminal. It is certainly the reverse of case 1.

The SW7 would be turn on by the comparator to connect the output and bulk. The gate voltage would become Vout - Vdd and the source voltage is also Vout. The gate overdrive (Vsg) still maintains exact Vdd. And threshold voltage is also held constant.

source out

The above equation is the same as Equation (6). During

“on” state, when the difference between input and output becomes “zero”, the comparator would be low and SW6 would be turn on again. At this time, we do not care which terminal is source because Vin already equals the sampled signal.

V. RESULTS

The simulation was completed by using HSPICE and TSMC 0.18um CMOS process technology. The power supply voltage is 1.8V. A 1.8Vpp 1Meg sinusoidal wave is applied to the ordinary bootstrapped switch without compensation, the bootstrapped switch with compensation in [3], and the proposed switch in this paper respectively. They are all loaded with 1 pF capacitance. The comparator in this paper has the voltage gain of 2000. Figure 5 illustrates the voltage of input, output, and bulk of the sampling switch. It is shown that the bulk would track the lower signal between input and output.

Figure 6 shows the FFT of the output voltage in the ordinary bootstrapped switch without compensation, bootstrapped switch with compensation in [3], and the proposed switch in this paper. Table 1 summarizes the total distortion of these switches. The results show that total harmonic distortion (THD) is improved by 12.3dB and 42.5dB, respectively, in contrast to [3] and ordinary bootstrapped switch. The FFT results clearly indicate the huge improvement.

Table 1. Simulation results for harmonic distortion

In this paper, a novel low-voltage low-distortion switch has been presented. The modified switch makes the rail to rail input signal possible for low voltage switched circuit. By desensitizing “on” resistance of the sampling switch, the linearity of switch is improved. The main idea is to distinguish which terminal is the real source terminal so that the gate overdrive voltage can be maintained exact Vdd and the variation of threshold voltage due to the body effect can be canceled for the analog switch. Because the bulk always connects to the real source, the latch-up problem would not exhibit. Finally, the ”on” resistance does not vary with the input signal and is immune to variation. The total harmonic distortion is highly suppressed.

ACKNOWLEDGMENT

The authors thank TSMC and National Chip Implementation Center for providing the TSMC CMOS 0.18um SPICE model. This work is supported by Taiwan National Science Council.

REFERENCES

[1] A. M. Abo and P. R.Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Volume 34, Issue 5, pp.599-605, May 1999

[2] J. Steensgaard, ”Bootstrapped low-voltage analog switches,” Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Volume 2, pp.29- 32, May 30 – June 2, 1999.

[3] A. K. Ong, V. I. Prodanov, and M. Tarsia, “A method for reducing the variation in “on” resistance of a MOS sampling switch,” Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Volume 5, pp.437 – 440, May 2000.

[4] Kim Sangwook and Greeneich, “Body effect compensated switch for low voltage switched-capacitor circuits,” Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, Volume 4, pp.437-440, May 26-29, 2002.

[5] S. R. Sonkusale and J. Van der Spiegel, “A low distortion MOS sampling circuit,” Proceedings of the 2002 IEEE International Symposium on Circuits and Systems, Volume 5, pp.585-588, May 26-29, 2002.

A Reliable Low-Voltage Low-Distortion MOS Analog Switch

Chun-Yueh Yang and Chung-Chih Hung Department of Communication Engineering, National Chiao Tung University, Hsinchu, Taiwan

Abstract A novel low-voltage low-distortion analog sampling switch is proposed in this letter. A “ source tracker” techniuqe is used to distinguish the real source terminal of the sampling switch. The turn-on resistance of the sampling switch is kept exactly constant. The modified switch makes the rail-to-rail input signal swing possible for low voltage. TSMC 0.18um standard CMOS technology is utilized in this research. Results indicate that

在文檔中 1.5V 寬頻低失真通道選擇濾波器 (頁 56-0)