Summary

design a continuous time filter. Then it can be converted into discrete time filter or digital filter. The Z-transformation provides a concrete solution.

Chapter 3

High Performance Switched Capacitor filter technique

3.1 Introduction

In this chapter, some modern circuit design techniques for high performance are illustrated. The characteristics of lower power supply, distortion and noise are all what we desired. Besides, in order to let the filter applied on communication system, we need to implement a wide band filter. Undoubtedly, the appropriate amplifier design is also very important, especially with a heavy loading. We will introduce what problems we may meet and their proposed solutions for pursuing high performance.

3.2 Low voltage SC circuit design

In analog circuit, dynamic range is often an important index to evaluate the analog circuit performance. In order to achieve high enough SNDR, a large signal swing range is necessary. But as we mentioned before, the signal swing of the MOS sampling switch would be restricted linearly by power supply. The low supply voltage would result in a smaller signal swing that makes dynamic range decrease and thus it is not expected. One solution for this is providing two power supplies, the higher one for the analog circuits and the lower one for the digital circuits. The disadvantage is needed a larger cost because we need to use different CMOS process. Thus there are several solutions in circuit design will be showed below [5].

3.2.1 Clock boosting

Clock boosting is a well known and straight forward approach to solve this problem. The reason for smaller signal swing is the reducing clock voltage. Thus we just boost our clock signal to enlarge the swing range.

The voltage doubler is often used [12] [13] [14]. (Figure 3.1) It is mainly formed by two N-type transistors, capacitors and an inverter. The cross-coupled transistors would alternatively be charged the capacitors to Vdd. Input clock is an ordinary periodic clock. After several periods, two capacitors would be both charged to Vdd. The output voltage of the inverter would be pumped a Vdd by C2. Now the ideal output signal would be 2Vdd. This cell is usually called “charge pump”. This idea is usually widely used in voltage boosting. When the input signal is high, M4 would discharge the gate of the sampling switch to ground. The output clock would be determined by

G p DD

H C C C

V C

V = + +

2

2 2

Cp is the parasitic capacitor of , and is the gate capacitance oh the MOS sampling switch. But clock boosting often results in another problem that it would make the junction voltage exceed a Vdd. The junction breakdown issue is needed to be overcome especially in low threshold voltage process.

C

2

C

_G

VH

VDD

3.2.2 Switch opamp technique

This is a method that allows the circuit operating in low voltage condition without any clock boosting [14] [15]. The system is really operating in low voltage without any junction breakdown problems. The basic concept is illustrated in

figure3.2 (a) shows the standard SC integrator. (b) shows an switch opamp integrator.

The difference between two architectures is that switch opamp integrator operates without any floating sampling switch (S1). The original switch sampling function is replaced by a switch opamp and a switch with one end connected to ground. Thus the signal swing would not be constrained by inefficient clock voltage. They can operate in 1V level with a typical threshold voltage that equals 0.7v. During

Φ 1

, the previous output is valid. The capacitor (C1) would be sampled the input signal. During , the charge of C

Φ 2

1 would be transferred to C₂, and node A would also be reset to ground. In the meanwhile, the previous opamp would be switched off to avoid any conflict caused on the output. The opamp would be on or off alternatively. This is why it is called switch opamp. It overcomes the junction breakdown issue and benefits lower power. But the shortcoming of this architecture is much more complicated. It is not suitable for the analysis from the standard switched capacitor integrator. Besides it is often just used in low speed system because the opamp needs time to recover from

“off” state to “on”state. With the comparison to standard switched capacitor circuit, it often has worse performance like linearity and noise.

Figure 3.2 (a) standard integrator

(b) switched opamp integrator

3.2.3 Bootstrapped switch

Bootstrapped switch is a solution like clock boosting. The fundamental

operating concept is illustrated in figure 3.3. The sampling switch would be driven by a constant gate-source voltage. First the capacitor would be charged to Vdd. Then the input signal would be pumped by a Vdd. The gate voltage would be zero during

“off“ state and Vsig+Vdd during “on” state, respectively. The turn-on resistance of a MOS switch is independent on input signal because of fixed Vgs and it would make the harmonic distortion decrease. But the high junction voltage may cause the breakdown. This technique is often with the reliability

Figure 3.3 Bootstrapped switch concept

3.2.4 A low voltage integrator design

For a SC filter, the problem what we meet is only signal swing that would be reduced by sampling switch. The signal amplitude is also restricted by the amplifier.

Fortunately, we can solve this problem by adequate bias voltage. It is illustrated in

figure 3.4 means virtual ground, usually equaling to /2 and is the bias voltage making amplifier work properly. Assuming there is no input signal applied, the capacitor would have a voltage drop,

Vgnd

V

_DD

V

_B

gnd

B V

V

−

, in the steady state. Since no net charge is transferred, also has the same voltage drop. If the integrator needs to work in low voltage, should be set close to for working properly. The output of the amplifier can be set to /2 to achieve maximum swing [16].

C

F

V

B

V

_DD

V

DD

V

_in

V

_out

V

_B

V

_B

C

_F

Figure 3.4 A low voltage integrator

3.2.5 Multi-threshold voltage process

Many advanced process would provide multi-threshold voltage device. The reason we need multi-threshold voltage is that, as we mentioned before, the analog circuit needs smaller threshold voltage for large signal swing. But the device with small threshold voltage would contribute larger leakage current. It would directly impact the digital circuit performance even result in failure. So the higher threshold voltage device is often used for digital circuits and the lower one is for analog circuits.

In addition, multi-threshold voltage process also means a larger cost [7].

3.3 Low distortion SC circuit design

3.3.1 Distortion mechanism

The distortion may be caused by any component in switched capacitor circuit.

Before we introduce the design technique for low distortion switched capacitor circuit, it is essential to understand the distortion how to be generated [17].

A. Capacitor Nonlinearity

We often discuss the distortion in an integrator. This is because SC circuit seldom uses an amplifier without negative feedback. A single-ended SC integrator is shown in figure 3.5. The charge equation can be expressed by

)

We assume all nonideality is only contributed by the capacitor and other components are ideal. The capacitor voltage can be represented by

where Vc is the nominal values at quiescent voltage. In the most cases, we often just take the first two items into consideration and others would be ignored. The expression would be changed into the following

. We substitute it into equation 3.1

The equation would be approximated by

]}

Now we find the following relation

nT

c

The second and third distortion of the output in the integrator can be derived by

1 2

We can find the second and the third harmonic distortion are proportional to the output voltage and its square, respectively.

(a)

(b)

Figure 3.5 (a) Single-ended SC integrator (b) Two-phase clock B. Distortion caused by amplifier gain nonlinearity

The real opamp usually has finite gain and introduces the distortion into the SC circuit.

We also take the integrator with a feedback factor which equals β into the

consideration. As the same as before, we assume all nonlinearity only comes from the amplifier and is caused by finite gain characteristic. The output voltage can be

represented by

"

+ + +

=

a₁v₁ a₂v₁² av₁³

v_o For simplicity, it would be approximated the first three terms. As before, we can get the charge balance equation as follows

)]

Now we can derive the approximation.

]}

In the expression, the second and the third term represent the errors.

2 Because the SC filter works in discrete time, the signal appears in sampled-data

form. Unfortunately, the output of the SC filter would be directly applied to the next stage, as a continuous time system. The distortion would be caused by finite slew rate of the amplifier. To obtain the distortion caused by finite slew rate, we introduce a summarized model. (Figure 3.6).

x x y

=

Figure 3.6 Model of slewing distortion

In this model, is the filter output and is the transition voltage. Transition voltage means the difference between current sampled output voltage and previous sampled voltage. The function

v

o x

(t )

x x

y

= represents the distortion generator. Now we

assume the output sampled signal expressed by

Now we can find the transition voltage would be represented as a sampled cosine

) 1

wave with a varied magnitude and a shifted phase. The output of the distortion generator can be expressed by

)

From the model, the harm nic wave would be multiplied by an impulse stream a(t) o Thus the magnitude would be also multiplied by a factor

c

This equation shows that if slew rate is symmetrical, there are only odd harmonic

1 summarizes the distortion source [18].

present.

Table 3.

Table 3.1 Distortion Approximation

Distortion source THD theory

Capacitor Nonlinearity

Amplifier open-loop gain Nonlinearity

Switch on resistance nonlinearity

Signal dependent charge injection of the switches

distortion caused by the finite slew rate of amplifier

3.3.2 The design consideration for l ter

gn

techniq ,

aling if necessary.

ed.

A. no

eans we need to scale the internal voltage of the SC filter

)

From the above analysis of the distortion source, the low distortion desi ues would be illustrated in this section. To suppress the harmonic distortion there are three key points for designing.

1. We must do internal voltage sc

2. Reducing internal components distortion 3. The differential architecture should be adopt de voltage scaling

Node voltage scaling m

properly. For lower distortion, the internal should be lower than the peak value of the passband. It can make the internal voltage would not be distorted before the output

voltage limits are reached. In another opinion, the smaller signal swing would result in much lower harmonic distortion. Thus we must try to keep internal signal smaller and the voltage only saturates at the output node.

B. Reducing internal components distortion

In ord filter, we need to design the

e

or the

ns.

fferential

Another

y would be a severe constraint. First, the

the er to lower the distortion generated within the SC

internal components carefully. The main components in the SC filter are switches, capacitors and amplifier. As we mentioned before last lection, we need try to depriv the filter of the distortion source. But the ideal component is impossible to be implemented. Thus we need to get a balance between all components design. F switch design, we need to suppress the distortion caused by turn-on resistance, charge injection and clock feedthrough. As to the distortion induced by the capacitor, we can adopt the differential architecture to mitigate them. For the amplifier design, it is essential to use the differential architecture. The even order distortion would be reduced and PSSRR would be raised. The signal swing also would be enlarged to resist the noise. Besides, we also need a high slew rate to alleviate the distortion caused by finite slew rate. We must pay more concentration on these circuit desig C. The differential architecture should be used

The harmonic distortion would be significantly reduced by fully di

architecture. The linear error and even order nonlinearity would be mitigated.

advantage is a larger signal swing [17].

3.4 Summary

For the analog circuit, the low power suppl

signal swing would be reduced linearly. The sampling switch would not be driven properly. The integrator also meets the same problem. There are several solutions showed in this chapter. In order to design a low distortion filter, we also introduce

distortion mechanism and the design consideration. In the next chapter, we will use these techniques to realize a channel selection filter.

Chapter 4

A low voltage low distortion wide-band CMOS switch capacitor filter

4.1 Introduction

The specification and architecture would dominate the distortion performance of the SC filter. The sampling period, corner frequency and nonideal device all would affect the THD of the output signal. The high sample rate can highly suppress the distortion, but it would be hard to implement an amplifier in this situation. Besides, in order to emerge the analog and digital circuits in the same power supply, the low voltage circuit design is unavoidable. It obviously makes the amplifier design more difficult. Even we can overcome this problem, the nonoverlapped high clock rate generation is also another key point.

In order to work out these problems, we must carefully choose the

architecture. Through a few architecture design consideration, we can complete a high speed low voltage filter immune to the distortion under the lower clock rate. Even using the same architecture, the bad setting of the parameters would be result in the lower performance. These are all what we need to take into consideration. Our filter architecture is made of a six-order elliptic filter. It is widely used in wireless receiver.

In the direct conversion receiver the receiving signal would be first filtered by a anti-aliasing low pass filter. The next, channel select filter, which we intend to carry out this time, would extract the signal band which we need. Finally, the last analog to digital converter would convert the filtering signal to digital code for the next digital

signal process (DSP).

Our channel select filter is composed of three serial second order biquad. As we say before, we adopted the SC filter. It works at 20M Hz with a cut off frequency at 2 MHz. We mainly choose the biquadratic filter because of its convenience. We can easily set all parameters and implement the whole circuit, especially in low voltage. It is a simple way to tune the filter and raise its performance.

In general, people often just focus its frequency response while designing filters, because it would make your filter design more simple. As to phase, we often use an equalizer behind the filter to take charge. Based on the first key point, we should avoid the internal signal magnitude close to the output signal maximum. It will

contribute more distortion because it would be limited by internal voltage level before the signal is restricted by the output terminal. The internal voltage boosting would result in large THD. We should do amplifying in the later stage. For the clock

feedthrough, it would be another source of THD. We can use the bottom sampling to solve it. In the meanwhile, using the differential architecture would suppress switch charge injection, clock feedthrough, even order distortion and linear capacitor voltage error.

Figure 4.1 shows the all parameters of the channel select filter. Because the corner frequency locates on 2MHz, the bandwidth of the biquads should not exceed 2 MHz too far for free of high frequency harmonic distortion, or it would reduce the signal linearity. Besides, because the first stage is responsible for receiving signal, it often dominates the whole performance. So the first stage design is usually very important. In the first stage, the gain is set to be 0.8. This is what we said before about voltage scaling. The second stage would amplify the signal close to normal signal level. It is not considerate to do serial voltage scaling. If you do it, it means we need a

the output noise power raise. It is not what we want. If we would like to achieve a high dynamic range, we need to keep both medium distortion and noise. Another point needed to mention, the high Q stage is suitable in the later stage. But in practice, we may just do little under the constraint of the specification. It is hardly to meet all requirements. In the next section, we will discuss every building block to be used in our SC filter.

Figure 4.1 6th order elliptic filter parameters

4.2 Low voltage low distortion MOS sampling switch

Our novel MOS sampling switch is based on bootstrapped switch. Thus the bootstrapped switch and its modification would be explained in this section. A new MOS sampling switch is proposed in the end of this section.

Simple sampling Switch

Figure 4.2 A simple MOS sampling switch

Figure 4.2 shows a basic S/H circuit. When Ø is high (usually Vdd), the switch will be turned on and the capacitor will be charged to Vin. When Ø is low, the switch will be turned off and the capacitor will hold the sampled voltage. Its resistance is given by

1

( )

n ox gs tn

Ron W

C V V

µ L

=

−

(4.1)

where

V

_tn =

V

_t0+

γ

[ 2

φ

_F +

V

_SB − 2

φ

_F ] (4.2)

There are some obvious drawbacks in this sampling switch. The sampling switch output is limited to Vdd -Vt. If Vin > Vdd -Vt, the output voltage would be saturated and the incorrect voltage would be sampled. It would not have a full swing range. Besides, the resistance would vary with the input signal from Equation (4.1). It may donate larger harmonic distortion. The body effect also contributes nonlinearity, especially at low voltage. Therefore, the bootstrapped switch was proposed to solve the full swing problem and variation of the switch resistance.

BOOTSTRAPPED SWITCHES AND RELATED COMPENSATION TECHNIQUES

From Equation (4.1), to obtain constant resistance, the gate to source voltage should be held constant during the “on” state.

Figure 4.3 The bootstrapped switch operation concept

Figure 4.3 shows the principle of the bootstrapped switch [19] and the circuit realization is shown in [20]. During the “off” state (SW3, SW4 and SW5 on), the capacitor would be charged to Vdd and likely act as a floating battery to bootstrap the gate voltage when the “on” state (SW1, SW2 on) . It is assumed the input terminal of the sampling switch would be source. Therefore, the resistance of the switch is given by

1

( )

n ox t

Ron W

C Vdd V µ L

=

−

(4.3)

Clearly, it can be independent of input signal to reduce harmonic distortion. However, the MOS switch is bidirectional and symmetric. The source and drain terminals may interchange depending on the input signal and previous sampled voltage. If the input signal is larger than previous sampled voltage, the source and drain terminal would be interchanged. Therefore, the source voltage is not Vin but sampled voltage in the previous state. Then, Vgs is not ”Vdd”. We can not maintain Vgs constant. Another distortion source of threshold voltage variation from body effect still dominate large distortion, especially in low power supply. Therefore, the body effect compensated switch was proposed in [22] [23]. The main idea behind [23] is to use direct connection from source to bulk to avoid the body effect during “on” state. This is a straightforward idea, but the real source is not always the input terminal in practice.

And if the source of the P-type transistor is not highest voltage of all terminals, it may cause the latch-up problem [24]. Of course, Vsb also does not remain zero when the real source is not the input terminal of the sampling switch.

Another technique was proposed to use a replica transistor to cancel the threshold voltage [22], as shown in Figure 4.4. It is modified from a typical bootstrapped switch.

It creates a threshold voltage as the same as the one sampling switch and cancel each

It creates a threshold voltage as the same as the one sampling switch and cancel each

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