Distortion mechanism - Low distortion SC circuit design

Chapter 3 High Performance Switched Capacitor filter technique 17

3.3 Low distortion SC circuit design

3.3.1 Distortion mechanism

The distortion may be caused by any component in switched capacitor circuit.

Before we introduce the design technique for low distortion switched capacitor circuit, it is essential to understand the distortion how to be generated [17].

A. Capacitor Nonlinearity

We often discuss the distortion in an integrator. This is because SC circuit seldom uses an amplifier without negative feedback. A single-ended SC integrator is shown in figure 3.5. The charge equation can be expressed by

)

We assume all nonideality is only contributed by the capacitor and other components are ideal. The capacitor voltage can be represented by

where Vc is the nominal values at quiescent voltage. In the most cases, we often just take the first two items into consideration and others would be ignored. The expression would be changed into the following

. We substitute it into equation 3.1

The equation would be approximated by

]}

Now we find the following relation

nT

The second and third distortion of the output in the integrator can be derived by

1 2

We can find the second and the third harmonic distortion are proportional to the output voltage and its square, respectively.

(a)

(b)

Figure 3.5 (a) Single-ended SC integrator (b) Two-phase clock B. Distortion caused by amplifier gain nonlinearity

The real opamp usually has finite gain and introduces the distortion into the SC circuit.

We also take the integrator with a feedback factor which equals β into the

consideration. As the same as before, we assume all nonlinearity only comes from the amplifier and is caused by finite gain characteristic. The output voltage can be

represented by

"

+ + +

=

a₁v₁ a₂v₁² av₁³

v_o For simplicity, it would be approximated the first three terms. As before, we can get the charge balance equation as follows

)]

Now we can derive the approximation.

]}

In the expression, the second and the third term represent the errors.

2 Because the SC filter works in discrete time, the signal appears in sampled-data

form. Unfortunately, the output of the SC filter would be directly applied to the next stage, as a continuous time system. The distortion would be caused by finite slew rate of the amplifier. To obtain the distortion caused by finite slew rate, we introduce a summarized model. (Figure 3.6).

x x y

=

Figure 3.6 Model of slewing distortion

In this model, is the filter output and is the transition voltage. Transition voltage means the difference between current sampled output voltage and previous sampled voltage. The function

v

o x

(t )

x x

y

= represents the distortion generator. Now we

assume the output sampled signal expressed by

Now we can find the transition voltage would be represented as a sampled cosine

) 1

wave with a varied magnitude and a shifted phase. The output of the distortion generator can be expressed by

)

From the model, the harm nic wave would be multiplied by an impulse stream a(t) o Thus the magnitude would be also multiplied by a factor

This equation shows that if slew rate is symmetrical, there are only odd harmonic

1 summarizes the distortion source [18].

present.

Table 3.

Table 3.1 Distortion Approximation

Distortion source THD theory

Capacitor Nonlinearity

Amplifier open-loop gain Nonlinearity

Switch on resistance nonlinearity

Signal dependent charge injection of the switches

distortion caused by the finite slew rate of amplifier

3.3.2 The design consideration for l ter

techniq ,

aling if necessary.

ed.

A. no

eans we need to scale the internal voltage of the SC filter

)

From the above analysis of the distortion source, the low distortion desi ues would be illustrated in this section. To suppress the harmonic distortion there are three key points for designing.

1. We must do internal voltage sc

2. Reducing internal components distortion 3. The differential architecture should be adopt de voltage scaling

Node voltage scaling m

properly. For lower distortion, the internal should be lower than the peak value of the passband. It can make the internal voltage would not be distorted before the output

voltage limits are reached. In another opinion, the smaller signal swing would result in much lower harmonic distortion. Thus we must try to keep internal signal smaller and the voltage only saturates at the output node.

B. Reducing internal components distortion

In ord filter, we need to design the

or the

ns.

fferential

Another

y would be a severe constraint. First, the

the er to lower the distortion generated within the SC

internal components carefully. The main components in the SC filter are switches, capacitors and amplifier. As we mentioned before last lection, we need try to depriv the filter of the distortion source. But the ideal component is impossible to be implemented. Thus we need to get a balance between all components design. F switch design, we need to suppress the distortion caused by turn-on resistance, charge injection and clock feedthrough. As to the distortion induced by the capacitor, we can adopt the differential architecture to mitigate them. For the amplifier design, it is essential to use the differential architecture. The even order distortion would be reduced and PSSRR would be raised. The signal swing also would be enlarged to resist the noise. Besides, we also need a high slew rate to alleviate the distortion caused by finite slew rate. We must pay more concentration on these circuit desig C. The differential architecture should be used

The harmonic distortion would be significantly reduced by fully di

architecture. The linear error and even order nonlinearity would be mitigated.

advantage is a larger signal swing [17].

3.4 Summary

For the analog circuit, the low power suppl

signal swing would be reduced linearly. The sampling switch would not be driven properly. The integrator also meets the same problem. There are several solutions showed in this chapter. In order to design a low distortion filter, we also introduce

distortion mechanism and the design consideration. In the next chapter, we will use these techniques to realize a channel selection filter.

Chapter 4 A low voltage low distortion wide-band CMOS switch capacitor filter

4.1 Introduction

The specification and architecture would dominate the distortion performance of the SC filter. The sampling period, corner frequency and nonideal device all would affect the THD of the output signal. The high sample rate can highly suppress the distortion, but it would be hard to implement an amplifier in this situation. Besides, in order to emerge the analog and digital circuits in the same power supply, the low voltage circuit design is unavoidable. It obviously makes the amplifier design more difficult. Even we can overcome this problem, the nonoverlapped high clock rate generation is also another key point.

In order to work out these problems, we must carefully choose the

architecture. Through a few architecture design consideration, we can complete a high speed low voltage filter immune to the distortion under the lower clock rate. Even using the same architecture, the bad setting of the parameters would be result in the lower performance. These are all what we need to take into consideration. Our filter architecture is made of a six-order elliptic filter. It is widely used in wireless receiver.

In the direct conversion receiver the receiving signal would be first filtered by a anti-aliasing low pass filter. The next, channel select filter, which we intend to carry out this time, would extract the signal band which we need. Finally, the last analog to digital converter would convert the filtering signal to digital code for the next digital

signal process (DSP).

Our channel select filter is composed of three serial second order biquad. As we say before, we adopted the SC filter. It works at 20M Hz with a cut off frequency at 2 MHz. We mainly choose the biquadratic filter because of its convenience. We can easily set all parameters and implement the whole circuit, especially in low voltage. It is a simple way to tune the filter and raise its performance.

In general, people often just focus its frequency response while designing filters, because it would make your filter design more simple. As to phase, we often use an equalizer behind the filter to take charge. Based on the first key point, we should avoid the internal signal magnitude close to the output signal maximum. It will

contribute more distortion because it would be limited by internal voltage level before the signal is restricted by the output terminal. The internal voltage boosting would result in large THD. We should do amplifying in the later stage. For the clock

feedthrough, it would be another source of THD. We can use the bottom sampling to solve it. In the meanwhile, using the differential architecture would suppress switch charge injection, clock feedthrough, even order distortion and linear capacitor voltage error.

Figure 4.1 shows the all parameters of the channel select filter. Because the corner frequency locates on 2MHz, the bandwidth of the biquads should not exceed 2 MHz too far for free of high frequency harmonic distortion, or it would reduce the signal linearity. Besides, because the first stage is responsible for receiving signal, it often dominates the whole performance. So the first stage design is usually very important. In the first stage, the gain is set to be 0.8. This is what we said before about voltage scaling. The second stage would amplify the signal close to normal signal level. It is not considerate to do serial voltage scaling. If you do it, it means we need a

the output noise power raise. It is not what we want. If we would like to achieve a high dynamic range, we need to keep both medium distortion and noise. Another point needed to mention, the high Q stage is suitable in the later stage. But in practice, we may just do little under the constraint of the specification. It is hardly to meet all requirements. In the next section, we will discuss every building block to be used in our SC filter.

Figure 4.1 6th order elliptic filter parameters

4.2 Low voltage low distortion MOS sampling switch

Our novel MOS sampling switch is based on bootstrapped switch. Thus the bootstrapped switch and its modification would be explained in this section. A new MOS sampling switch is proposed in the end of this section.

Simple sampling Switch

Figure 4.2 A simple MOS sampling switch

Figure 4.2 shows a basic S/H circuit. When Ø is high (usually Vdd), the switch will be turned on and the capacitor will be charged to Vin. When Ø is low, the switch will be turned off and the capacitor will hold the sampled voltage. Its resistance is given by

1 ( )

n ox gs tn

Ron W

C V V

µ L

=

−

(4.1)

where

V

_tn =

V

_t₀+

γ

[ 2

φ

_F +

V

_SB − 2

φ

_F ] (4.2)

There are some obvious drawbacks in this sampling switch. The sampling switch output is limited to Vdd -Vt. If Vin > Vdd -Vt, the output voltage would be saturated and the incorrect voltage would be sampled. It would not have a full swing range. Besides, the resistance would vary with the input signal from Equation (4.1). It may donate larger harmonic distortion. The body effect also contributes nonlinearity, especially at low voltage. Therefore, the bootstrapped switch was proposed to solve the full swing problem and variation of the switch resistance.

BOOTSTRAPPED SWITCHES AND RELATED COMPENSATION TECHNIQUES

From Equation (4.1), to obtain constant resistance, the gate to source voltage should be held constant during the “on” state.

Figure 4.3 The bootstrapped switch operation concept

Figure 4.3 shows the principle of the bootstrapped switch [19] and the circuit realization is shown in [20]. During the “off” state (SW3, SW4 and SW5 on), the capacitor would be charged to Vdd and likely act as a floating battery to bootstrap the gate voltage when the “on” state (SW1, SW2 on) . It is assumed the input terminal of the sampling switch would be source. Therefore, the resistance of the switch is given by

1 ( )

n ox t

Ron W

C Vdd V µ L

=

−

(4.3)

Clearly, it can be independent of input signal to reduce harmonic distortion. However, the MOS switch is bidirectional and symmetric. The source and drain terminals may interchange depending on the input signal and previous sampled voltage. If the input signal is larger than previous sampled voltage, the source and drain terminal would be interchanged. Therefore, the source voltage is not Vin but sampled voltage in the previous state. Then, Vgs is not ”Vdd”. We can not maintain Vgs constant. Another distortion source of threshold voltage variation from body effect still dominate large distortion, especially in low power supply. Therefore, the body effect compensated switch was proposed in [22] [23]. The main idea behind [23] is to use direct connection from source to bulk to avoid the body effect during “on” state. This is a straightforward idea, but the real source is not always the input terminal in practice.

And if the source of the P-type transistor is not highest voltage of all terminals, it may cause the latch-up problem [24]. Of course, Vsb also does not remain zero when the real source is not the input terminal of the sampling switch.

Another technique was proposed to use a replica transistor to cancel the threshold voltage [22], as shown in Figure 4.4. It is modified from a typical bootstrapped switch.

It creates a threshold voltage as the same as the one sampling switch and cancel each other to be deprived of body effect. It is derived as follows. The drain current of MD in saturation is given by

V

I

Figure 4.4 The replica compensation

1 ( )

2

n ox GS t

I C W V V

µ L

= −

The drain current is constant by ignoring the second-order effect. Then we can find

1 ( )

2

G S t

n o x

V I V

C W

µ

= +

When SW1 and SW4 are on (Vin =Vs),

1 ( )

The gate voltage of the sampling switch would be equal to

V_G

+

V_d

. Substituting Equation (4.4) into Equation (4.1) and assuming Vs equals Vi, Ron can be obtained as following.

From Equation (4.5), all the parameters of the resistance are constant, but this circuit still suffers from the problem described previously, where the source terminal might be the input. In practice, the Vt of the sampling switch and replica would not match exactly due to the second order effect and process variation. It is difficult to be compensated completely. The input signal is also needed to decrease by a threshold voltage to make sure the replica transistor in saturation. Another circuit was proposed to modify this drawback of smaller swing range in [14].

The proposed sampling switch

Through the above discussion, a key point is that a “source follower” is needed to track the “real source” connecting the charged capacitor and maintaining the gate overdrive to be a constant voltage ”Vdd”. Figure 4.5 shows the proposed circuit. The sampling switch is composed of a comparator and several switches.

Besides some necessary switches of a typical bootstrapped sampling switch,

additional switches SW6 and SW7 are added. To ensure rail to rail swing, SW6 and

SW7 are made of complementary switches. The comparator is used to trigger SW6

and SW7 to make the bulk connect to the real source terminal. The bulk is guaranteed

to connect to only one terminal, the source terminal, during the “on” state. We adopt the structure of direct connection between source and bulk because it has less nonlinearity and large input swing than using a replica. In the standard CMOS technology, the sampling switch should be P-type. Two cases are discussed in the following where Vin represents input signal and Vout represents the voltage sampled in the “on” state.

Figure 4.5 The proposed sampling switch

Case 1: When Vin > Vout, the real source is the input terminal. During “off” state (SW2, SW3, and SW5 on), the capacitor would be charged to -Vdd. During the

“on” state (SW1 and SW4 on), the comparator output will be low to turn on SW6 to make a connection between the input and bulk because input voltage is higher than

Vout . And the gate voltage of switch equals Vin - Vdd. Then the gate overdrive (Vsg) and Vsb exactly equals Vdd and zero respectively, during the “on” state.

source in

Case 2: When Vin < Vout, the real source terminal should be the output terminal. It is certainly the reverse of case 1. The SW7 would be turn on by the comparator to connect the output and bulk. The gate voltage would become Vout - Vdd and the source voltage is also Vout. The gate overdrive (Vsg) still maintains exact Vdd. And threshold voltage is also held constant.

source out

The above equation is the same as Equation (4.6). During “on” state, when the difference between input and output becomes “zero”, the comparator would be low and SW6 would be turn on again. At this time, we do not care which terminal is source because Vin already equals the sampled signal.

The power supply voltage is 1.8V. A 1.8Vpp 1Meg sinusoidal wave is applied to the ordinary bootstrapped switch without compensation, the bootstrapped switch with compensation in [22], and the proposed switch in this paper respectively.

They are all loaded with 1 pF capacitance. The comparator in this paper has the voltage gain of 2000. Figure 4.6 illustrates the voltage of input, output, and bulk of

the sampling switch. It is shown that the bulk would track the lower signal between input and output.

Figure 4.7 shows the FFT of the output voltage in the ordinary bootstrapped switch without compensation, bootstrapped switch with compensation in [22], and the proposed switch in this paper. Table 4.1 summarizes the total distortion of these switches. The results show that total harmonic distortion (THD) is improved by 12.3dB and 42.5dB, respectively, in contrast to [22] and ordinary bootstrapped switch.

The FFT results clearly indicate the huge improvement.

(a) Input signal

(b) Sampled signal

(c) Bulk signal

Figure 4.6 The voltage of the sampling switch

Figure 4.7 FFT of the switch output with small input signal

Table 4.1 Simulation results for harmonic distortion

Typical Ref[22] Proposed

THD -41.6db -71.8db -84.1db

HD2 -44.2db -72.7db -87.9db

HD3 -46.9db -82.6db -105.9db

The modified switch makes the rail to rail input signal possible for low voltage switched circuit. By desensitizing “on” resistance of the sampling switch, the linearity of switch is improved. The main idea is to distinguish which terminal is the real source terminal so that the gate overdrive voltage can be maintained exact Vdd and the variation of threshold voltage due to the body effect can be canceled for the analog switch. Because the bulk always connects to the real source, the latch-up problem would not exhibit. Finally, the ”on” resistance does not vary with the input signal and is immune to variation. The total harmonic distortion is highly suppressed.

4.3 Low Voltage Low distortion amplifier and integrator

It is important to design a good amplifier for switched capacitor circuit. The amplifier is the key component and its design would directly impact the whole performance. We should take it into more considerations. In low power supply, the transistors are not easily in deep saturation region. Therefore, the linearity of the amplifier would be much reduced. It is unavoidable. On the other hand, the non-ideal opamp would also contribute the distortion. The distortion usually results from finite gain, bandwidth and slew rate. These are also being taken into the consideration. The amplifier architecture applied for the switched capacitor filter is two-stage. The two stage amplifier can provide a large gain which can reduce the error caused by finite gain. The two-stage is also flexible for designing. Especially we need a large output current to improve the slew rate. Besides, we can benefit a low output resistance. The amplifier would not be much restricted by a large load. It is good to switched

capacitor filter because the large capacitor is often applied in it [25] [26].

For designing a high speed switched capacitor filter, setting time would be a critical point. Inadequate setting time would make the resolution of SC filter decrease, because the amplifier could hardly complete the charge or discharge on the capacitor.

Thus settling time would be a big impact on switched capacitor filter. For producing an adequate settling time, the bandwidth and slew rate of the amplifier should be taken into consideration. The infinite unit gain bandwidth and slew rate are both what we desired. But it is difficult to achieve. On the other hand, a high slew rate is

sometimes incompatible with a high gain. A high slew rate must be achieved by a large bias current in the output stage. It also may reduce the output resistance that makes the overall gain decline. We need to get a balance between them.

The settling time is highly related to the step response of the amplifier. It is often defined to the time which opamp can reach a specified percentage. The settling time consists of two distinct parts: non-linear and linear slewing. The linear portion is caused by finite unity-gain bandwidth of the amplifier. It would be a minimum value

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