Chapter 1 Introduction
1.2 Thesis Outline
The dissertation is organized into the following chapters:
In chapter 1, a brief overview of the TFT technology and the interconnections with
low-RC delay is introduced to describe the various applications of them. We describe the trend of TFT technology development and the degradation of low-k caused by Cu penetration. Then, the outline throughout the dissertation is discussed here.
In chapter 2, a new structure of beck-channel etching (BCE) a-Si TFTs was first proposed. This novel device owns superior performance than the conventional one.
The ON-current of the new devices is 1.5 times the conventional BCE device.
Moreover, the proposed device owns low leakage current either in dark or under bottom-side illumination.
In chapter 3, the temperature and AC stress effects on poly-Si TFT are studied, separately. The electrical characteristics of n-TFT with/without LDD are measured at temperatures. The characterizations of the n-TFTs without LDD under AC gate-bias stressing are investigated to clarify the degradation mechanism.
Chapter 4 contains two parts. For part I, the grain boundary effects of poly-Si TFT were discussed. The electrical properties of TFTs are compared to clear the carrier transport in poly-Si TFT . For part II, the influence of grain boundary in reliability is investigated under DC and AC stress.
In chapter 5, we demonstrated two kinds of the non-volatile memory devices fabricated using low-temperature poly-Si technology. The programming and erasing methods for poly-Si memory devices are also investigated. Moreover, the electrical characteristics and reliabilities of devices
In chapter 6, the intrinsic properties of low-k nano-porous silica and the impact of moisture absorption for interconnect applications are investigated. In addition, the reliability of nano-porous silica with Cu electrode using bias-stressing method is also demonstrated in this chapter.
In chapter 7, the intrinsic properties of barrier dielectric film, a-SiCN, are investigated.
In chapter 8, we summarize our experimental results and give a brief conclusion.
Recommendations of several topics relevant to the thesis are also given for further study.
Fig. 1-1 Four structures for a-Si TFTs.
1 2
3 2 1
3 Ec
Ev Et
Leakage Current Mechanism (1) Thermionic emission (2) Thermionic field emission (3) Pure tunneling
Fig. 1-2 Three possible mechanisms of leakage current in poly-Si TFTs, including thermionic emission, thermionic field emission and pure tunneling.
Fig. 1-3 (a) Plan view of the pixel using low-k passivation technology.
(b) Low dielectric constant (k) material as an inter-level dielectric.
Chapter 2
High Performance amorphous Silicon TFT
2.1 Introduction
Amorphous silicon technology is very attractive due to its low processing temperature and low cost manufacture. The hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT) have been applied on the flat panel displays and X-ray sensor arrays. There are four structures for a-Si:H TFT’s, including staggered, inverted staggered, coplanar and inverted coplanar TFT’s. Among these four structures, the inverted staggered one is most popular due to its simple process and acceptable electrical characteristics. Therefore, the inverted-staggered back-channel-etched (BCE) type of a-Si:H TFT has been widely used as a switching element to control the gray level in liquid crystal display(LCD) [2.1-2.5] and to drive organic light-emitting-diode (OLED). [2.6-2.12] TFT with a large switch ratio and low off-state leakage current is suitable to control LCDs. In addition, a-Si:H TFT with high stability and driving capability is suitable for AMOLED application since OLEDs require a current driving scheme in contrast to LCDs, which are voltage driven.
The a-Si:H material is a well-known photoconductor and its conductivity increases drastically resulting from the generation of electron-hole pairs under illumination of a visible light.[2.13-2.15] However, LCD panels are usually used in an illumination environment such as under the back-light. Therefore, the leakage current of TFT under back-light illumination in TFT-LCD displays should be reduced to avoid losing
structure for the TFT using in AMLCDs.[2.16] Figure 2-1(a) and 2-1(b) show the conventional and Akiyama’s structures, respectively. The major difference between them is that a-Si:H island is completely located inside the coverage of gate metal in Akiyama’s structure. The gate metal effectively shields the back-light irradiating to a-Si:H layer, as shown in Fig. 2-1(b). However, the edges of a-Si:H island are direct contact with the source/drain (S/D) electrode, when the TFT fabricated with the deposition of metal deposit on the tri-layer(SiNx/ a-Si:H/n+ layer), as shown in Fig.
2-1(b). The metal/a-Si:H contact usually exhibits the Schottky type conduction, being subjected to the leakage.[2.13]
We propose a new and convenient technology to reduce the leakage current originated from the leaky contact between the metal and a-Si:H layer in this study.
The turn-on current of the proposed TFT is also increased due to the reduction in parasitic source/drain resistance. Moreover, the proposed TFT exhibits better stability than the conventional BCE TFT under the current stress.
2.2 Experimental Procedure
The fabrication process of the proposed TFT device is described as below. The inverted staggered a-Si:H TFT’s were fabricated, but the a-Si:H active island of TFT is located inside the coverage of gate metal electrode. First, metallic Cr was deposited on glass substrates by sputtering and then was patterned to form gate electrodes. It was followed by SiN, undoped a-Si:H and phosphorous-doped a-Si:H (n+ a-Si:H) layer deposition sequentially on the Cr patterned glass, without breaking the vacuum in a plasma-enhanced chemical vapor deposition (PECVD) chamber. The SiN layer was deposited using a mixture of SiH4 and NH3 gases at a substrate temperature of 300oC and the undoped a-Si:H was deposited from a gas mixture of H2 and SiH4 at
300 oC. The film thickness of Cr, SiNx, a-Si:H and n+ a-Si:H layers was 150, 200, 150 and 20 nm, respectively. The definition of a-Si:H active region was performed with lithography and etching processes. In our proposed new TFT, the second layer of 20-nm-thick n+ a-Si:H film was deposited to clad the active regions. Aluminum film was evaporated to form the source/drain electrodes. Finally, the patterned Al films were used as a mask to etch back the channel to isolate the source and drain electrodes of TFT. In the proposed process, only three masks were required to fabricate TFT and the number of mask is equal to the conventional BCE procedure. Figure 2-1(c) illustrates the new structure of our proposed light-shied TFT device. It should be noted that the proposed TFT described above consists of 20nm n+ layer at the edge and 40nm n+ layer on the top of the active island. We performed the DC stress using Agilent 4156 analyzer on the TFTs to evaluate the stability of TFTs.
2.3Results and Discussions
The solid and dashed lines in Fig2-2 indicate transfer characteristics of light-shield a-Si:H TFTs fabricated with conventional as well as our proposed process, respectively. The leakage current of Akiyama’s light-shield TFT is as high as two order the proposed TFT under the simialr negative gate voltages. The S/D metal/intrinsic a-Si:H contact at the edge of a-Si:H island, as shown in Fig. 2-1(b), usually behaves as the Schottky emission.[2.13] On the contrary, the capped n+ a-Si layer on the a-Si:H island effectively avoids the direct contact between a-Si:H and S/D metal, as shown in Fig. 2-1(c). The n+ a-Si:H layer can effectively block the hole current when the gate is biased with negative voltages. The leaky path between the metal/intrinsic a-Si:H was thus eliminated and the leakage current was reduced. Under
the same applied gate voltages, the leakage current of Structure C is two orders of magnitude lower compared to the Structure B. In addition, the proposed TFT structure exhibits superior current driving capability, as shown in Fig. 2-3. The turn-on current of the new TFT is about 1.5 times higher than that of Structure A, the conventional inverter-staggered counterpart. Using the proposed structure in this work, the TFT with effective mobility of 1.05 cm2/Vsec extracted at Vd = 0.1V was obtained. The carrier mobility of conventional inverter-staggered TFT, structure A, fabricated with the same process is 0.72 cm2/Vsec. Moreover, the threshold voltageof the proposed TFT is 2.3V, extracted at current density of 1 nA with normalized channel width (W)/channel length (L) ratio and lower than the conventional inverter-staggered one (2.8V). To compare the leakage current between the proposed and the conventional BCE TFTs under illumination, the electrical measurements were performed under white-light illumination of 6000 nits underneath, as sketched in the inset of Fig. 2-4.
Fig. 2-4 illustrates that the proposed structure has lower leakage current than that of the conventional BCE Structure A device at Vd=10V under the illumination of 6000 nits. Meanwhile, the devices were operated with drain bias of 10V at saturation region (VD>Vgs-VT) since the photo-induced leakage current would be enhanced by the high drain bias.
The electrical characteristic of the inverter-staggered a-Si:H TFT suffers from the parasitic resistance.[2.17-2.18] The parasitic resistance is dependent on several factors, for instance, the thickness of a-Si:H, sheet resistance of n+ a-Si layer, and source/drain contact quality. For a constant W/L ratio, the effect of parasitic resistance can be clearly observed in the output characteristics of a-Si:H TFTs. The large parasitic resistance would result in the current crowding effect. A comparison of output characteristics (ID-VD) for the new TFT and the conventional TFTs under nominal W/L ratio is shown in Fig. 2-5. The current crowding is found in the
conventional inverter-staggered TFT, not observed in the proposed TFT device. The significant difference in device structure is an n+ a-Si contact formed at the sidewall of a-Si:H island (a-Si:H/n+a-Si) in the proposed TFT, as shown in Fig. 2-1(c). To investigate the difference of electrical characteristics between Structures A and C, the parasitic resistances of TFT devices were extracted. Under the operation of small drain voltages VD and high gate voltages VG, it is assumed that the turn-on resistance Ron of TFT device consists of the channel resistance Rch and the parasitic source/drain resistance Rp.
where Ci is the gate nitride capacitance per unit area and W, L, and Vt are the intrinsic device channel width, length, and the threshold voltage, respectively.[2.17] The parasitic resistance RP of a-Si:H TFT can be extracted through measuring the ON resistance Ron from the linear region of TFT output characteristics and through plotting the RonW against the channel length L.[2.17-2.20] Figure 2-6 illustrates the typical gate voltage dependence of the parasitic resistance Rp of Structures A and Structure C, comparatively. The Rp value of the proposed TFT is significantly lower than that of the conventional one. Moreover, the Rp of the conventional inverter-staggered TFT is strongly dependent on the gate voltages. The value of Rp decreases from 6.6 MΩ to 2.2 MΩ, when the gate voltage increases from 6V to 12V.
By contrast, the gate-voltage dependence of the Rp of the proposed TFT is weaker and just decreases from 1.2 MΩ to 0.5 MΩ. In the proposed TFT device, the lack of an intrinsic a-Si:H layer between channel and source/drain contacts can reduce such nonlinear effects, as similar to the space charge-limited conduction (SCLC).[2.19-2.20] The SCLC occurred in intrinsic a-Si:H region is influenced seriously by both the drain and gate voltages. Also, the simulation results indicate that
the carriers can be transported form the channel to the n+ layer at the sidewall of a-Si:H island and are quite different from those having an intrinsic layer between n+ a-Si layer and the channel.
Figures 2-7 and 2-8 illustrate the distributions of electrons near the drain region in the corresponding structures A and C. The arrow heads labeled in the two figures present the carrier transport directions. In the proposed structure, the electrons can transport though contacts, the side wall and the top contact of drain metal overlap region. By the contrary, the conventional inverted staggered TFT owns one path for transporting, from the bottom accumulation layer of the a-Si:H layer to the top contact of metal. Hence, the lower parasitic resistance of the proposed TFT results in relatively high mobility and low threshold voltage.
Application of a-Si:H TFT on AMOLED is really attractive due to its low cost of a-Si:H TFT processing. TFT is used as a controller to determine the driving current of OLED. However, the stability of a-Si:H TFT is the key concern for the realization of amorphous silicon AMOLED technology. With increasing the operation duration of a-Si:H TFT, the conduction current of a-Si:H TFT is decreased gradually. The interface state creation at a-Si/gate dielectric interface and charges trapped at the gate dielectrics are usually responsible for the degradations of a-Si:H TFT. Figure 2-9 shows the evolution of conducting currents in TFTs during bias temperature stressing (BTS) at 60oC. The current of 200nA was conducted on two devices with the same W/L ratio. The gate bias of Structure A and C was 11.25V and 9V, respectively. The proposed TFT exhibits the better ability against the DC current stressing. Figure 2-10 shows the ID-VG relationship of both TFTs after bias temperature stress. A significant threshold voltage shift of 1.75V was found in the conventional TFT after the stress, while the shift amount of the threshold voltage for the proposed TFT is as low as 0.75V. Since the proposed TFT owns superior driving capability, it could conduct the
same magnitude of current at the lower VGS than the conventional one. Thus, the gate dielectric in the proposed TFT is under lower perpendicular electric field across the gate dielectric, so the amount of trapped charges in the dielectric are decreased. The electrical stability of a-Si: H TFT is therefore improved.
2.4 Conclusions
A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) TFT is developed in this chapter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with an extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts between source/drain metal and a-Si:H at the edge of a-Si:H island. In addition, our proposed a-Si:H TFT device exhibits superior effective carrier mobility, as high as 1.05 cm2/Vsec due to the enormous improvement in parasitic resistance. We have evidenced that the leakage current of proposed TFT is lower than the conventional BCE device under bottom-side illumination of 6000 nits. It also exhibits the better ability against the DC current stressing. The impressively high performance provides the potential of the proposed a-Si:H TFT to apply for AMLCD and AMOLED technology.
Fig 2-1(a)
(a)
Fig2-1(b)
(b)
Fig. 2-1(c)
Fig. 2-1 (a) Conventional inverted-staggered a-Si:H TFT (Structure A). (b) Akiyama’s light-shield a-Si:H TFT (Structure B) (c) The new structure a-Si:H TFT (Structure C)
VG ( V )
- 6 - 4 - 2 0 2 4 6
Drain Current I
1 0- 1 5 1 0- 1 4 1 0- 1 3 1 0- 1 2 1 0- 1 1 1 0- 1 0 1 0- 9 1 0- 8 1 0- 7
S t r u c t u r e B S t r u c t u r e C
D(A)
Fig. 2-2 ID-VG transfer characteristics of TFTs, Structures B and C with the same W / L ratio at VD=0.1V. The leakage current of Structure C is effectively suppressed in the proposed TFT structure
V
G(V)
-10 -5 0 5 10 15
Drain Current I
D(A)
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7
Linear transconductance g m (A/V )
0 5e-10 1e-9 2e-9 2e-9
Sturcture C Structure A
Fig. 2-3 ID-VG transfer characteristics and linear transconductances (gm) of TFTs, Structure A and C with the same W / L ratio. The superior current driving capability of the proposed TFT is demonstrated.
VG (V)
-15 -10 -5 0 5 10 15 20
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
Fig. 2-4 Comparison of ID-VG relations of Structures A and C at VD=10V under the white-light illumination of 6000 nits. The inset sketches the illumination from the bottom-side of the TFTs.
Drain Current I
D(A)
Structure A
Structure C
V
D(V)
0 2 4 6 8 10 12 14
Drain current I
D(x10
-7A) 2 4 6 8
Structure C Structure A
0
Fig. 2-5 A comparison of output characteristics (ID-VD) for the proposed TFT and the conventional inverter-staggered TFT. The current crowding is found in the conventional inverter-staggered TFT, Structure A.
V
G(V)
5 6 7 8 9 10 11 12 13
R p (o h m )
0 2x106 4x106 6x106 8x106 10x106
Structure C Structure A
Fig. 2-6 The gate voltage dependence of the parasitic resistance Rp of Structures A and Structure C.
Fig. 2-7 The distribution of electrons near the drain region in the structures A. The arrow heads labeled in the two figures present the carrier transport directions.
.
Fig. 2-8 The distribution of electrons near the drain region in the structures C. In the proposed structure, the electrons can transport though contacts, the side wall and the top contact of drain metal overlap region.
S tre s s tim e (s e c )
0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0
Drain cruuent I D (A)
1 .5 x 1 0-6 1 .6 x 1 0-6 1 .7 x 1 0-6 1 .8 x 1 0-6 1 .9 x 1 0-6 2 .0 x 1 0-6 2 .1 x 1 0-6
S tru c tu re A S tru c tu re C
Fig. 2-9 The evolution of conducting currents in TFTs during bias temperature stressing (BTS). The current of 200nA was conducted on Structure A and C at 60oC with the gate bias of 11.25 V and 9V, respectively.
V G ( V )
- 1 0 - 5 0 5 1 0 1 5
Drain Current I D (A )
1 0 - 1 5 1 0 - 1 4 1 0 - 1 3 1 0 - 1 2 1 0 - 1 1 1 0 - 1 0 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 1 0 - 5
S t r u c t u r e A S t r u c t u r e C
Fig. 2-10 The ID-VG relationships of the TFTs after bias temperature stress. The threshold voltage shift of structure A and C is 1.75V and 0.75V, respectively.
Chapter 3
Investigation of Poly-Silicon Thin Film Transistors with/without LDD Structure at Temperatures and under AC stress
3.1 Introduction
Poly-Silicon Thin film transistors (Poly-Si TFTs) have been wily applied on the flat-panel displays like AMLCD and AMOLED. The major advantages of poly-Si TFTs are the higher driving capability than the amorphous silicon devices, and the existence of complementary devices.[3.1-3.5] Taking advantage of these features, poly-Si TFTs can be used to incorporate the integrated peripheral driving circuitry and switching transistor in the same substrate for flat-panel displays.[3.6-3.7] The integration of driver circuits would reduce the assembly complication and cost dramatically. If the mobility of poly-Si TFTs is further increased, this poly-Si technology will realize the system on panel (SOP) which will integrate memory, CPU, and display.[3.8-3.9] TFT devices in functional circuits serve as the switches and suffer the high frequency voltage pulses. Previous research reports have shown a relationship between the creation of states and hot-carriers effect by performing DC stress.[3.10-3.13] The degradation mechanism of n-channel TFT under dynamic voltage stress, however, has not been clarified yet.[3.14-3.16] The degraded TFT will seriously influence the operation of the circuits.
In addition, the dangling bonds in the grain boundaries in the poly-Si film serve as the trapping centers that play a cruel role for the electrical performance of poly-Si TFT. [3.17-3.18] These defect states in energy band gap would enhance the carrier to tunnel at the high field.[3.19-3.20] Therefore, the leakage current due to trap-assisted
tunneling effect is much larger in poly-Si TFTs than in the single crystal MOSFETs.
Trap-assisted tunneling effect is known to be strongly dependent on the electrical field.
In order to reduce the horizontal electric field around a drain, the lightly doped drain (LDD) structure is widely used for poly-Si TFTs. Some reports have demonstrated that the light-drain doping (LDD) technology can effectively reduce the electric field at the drain region and suppress the leakage current. [3.21-3.22] It also can keep down the kink effect resulted from the impact-ionization of energetic carriers which usually leads to the undesirable effect in electrical characteristics of TFT. The LDD-structure, hence, is necessary for the application of poly-Si TFT, especially for the N-channel TFTs.
Moreover, the large area electronics or the flat-panel displays comprised of poly-Si TFTs are used by peoples at the globe. Thus, the displays should keep the performances well at all kinds of the environments. Temperature usually influences the characteristics of solid-devices, and its relative effects are important for the application of Poly-Si TFT technology. In this chapter, the temperature effects on the n-type poly-Si TFT with/without LDD structure was firstly investigated. Then we observed the AC stress effects on n-channel poly-Si TFTs without LDD to clarify the degradation mechanism.
3.2 Temperature Effects on Poly-Si TFTs
3.2.1 Device FabricationTop-gate structured poly-Si TFTs were fabricated on glass substrate by low-temperature processes. Buffer SiO2 films and 90nm-thick amorphous silicon films were deposited by plasma enhanced chemical vapor deposition (PECVD), and
subsequently, the films were dehydrogenated by furnace annealing. After dehydrogenation, the a-Si films were crystallized by XeCl excimer-laser. [3.23-3.24]
The power of the line-shaped beam was 350 mJ/cm2. Following the laser process, 100nm-thick gate oxide was deposited by PECVD. Then the implantation was
The power of the line-shaped beam was 350 mJ/cm2. Following the laser process, 100nm-thick gate oxide was deposited by PECVD. Then the implantation was