Chapter 2 High Performance amorphous Silicon TFT
3.2 Temperature Effects on Poly-Si TFTs
Top-gate structured poly-Si TFTs were fabricated on glass substrate by low-temperature processes. Buffer SiO2 films and 90nm-thick amorphous silicon films were deposited by plasma enhanced chemical vapor deposition (PECVD), and
subsequently, the films were dehydrogenated by furnace annealing. After dehydrogenation, the a-Si films were crystallized by XeCl excimer-laser. [3.23-3.24]
The power of the line-shaped beam was 350 mJ/cm2. Following the laser process, 100nm-thick gate oxide was deposited by PECVD. Then the implantation was adapted to define the LDD region and S/D region. The LDD and S/D region was doped by phosphorous of 1 x 1013 atom/cm2 and 8 x 1014 cm3, respectively. Then MoW was sputtered as a gate metal. The LDD/gate overlap region is 0.75μm and LDD extends outside the gate 0.75μm. The dimension of the non-LDD TFTs in this section was W=12μm and L=6μm, the overlap of gate metal and S/D junction is 1μm. The cross section views of TFTs were illustrated in Figs. 3-1(a) and 1(b).
3.2.2 Results & Discussions
Figure 3-2(a) shows the ID-VG relations and transconductance, gm, of poly-Si TFT at the temperatures from 50K to 250K. Figure 3-2(b) shows ID-VG relations in the linear scale. The conducting current of STD TFT is significantly increased with the decreasing of the temperature. The ON-current of TFT at 250K is 0.825 times that at the 50K. Moreover, the threshold voltageof the TFTs varied from 1.6V to 0.8V, extracted at current density of 10 nA with normalized channel width (W)/channel length (L) ratio. In figures 3-2(b), the maximum value of gm is also raised with the decreasing in temperature. The mobility extracted from the maximum value of gm is 135.8 cm2/Vs and 106.5 cm2/Vs at 50K and 250K, respectively. This phenomenon can be explained by the evolutions of the carrier scattering in poly-Si TFT at temperatures.
Some reports have shown that the carriers in the MOSFET made on mono-crystalline silicon wafer suffer three types of scatterings, including impurity scattering, surface scattering and the phonon scattering, as shown in Fig. 3-3. [3.25] The phonon
scattering is due to the lattice vibrations and strongly dependent on the temperature.
The carrier transport of poly-Si TFT is evidenced to be mainly limited by the grain boundaries in the poly-Si film.[3.26] However, the field effective mobility of carriers should be affected by the phonon scattering within the same boundaries in channel region. At high temperature, the carrier is seriously scattered by the numerous phonon.
Accordingly, the effective mobility of carrier is lower at high temperature than that at low temperature. Unlike the MOSFET, the ELA poly-TFT owns lots of grain boundaries in the channel region. Thus, both the grain boundaries and phonons would deeply affect the carrier transport in the poly-Si TFT.
Figure 3-4 illustrates the ID-VG relations of LDD-TFT at the temperatures from 50K to 250K. Unlike the non-LDD TFT, the conducting current of LDD TFT is decreased with the decreasing of the temperature. The dominant mechanism in conducting capability of LDD TFT at the low temperature should be different from the non-LDD TFT. To clarify the difference between two devices, the sheet resistances of phosphorous heavily-doped and lightly-doped poly-Si film are measured from 50K to 250K, demonstrated in Figs. 3-5 (a) and (b). It’s apparent that the resistivity of heavily-doped film almost keep well as the temperature changed.
However, the LDD layer behaves as a temperature-dependent resistor which is a lager resistance at low temperature than at high temperature. The sheet resistivity of LDD at 50K is 4.72 times that at 300K. Since the LDD poly-Si sheet does not achieve the degeneracy doping level, the freeze effect of doped impurity atoms was observed. In addition, the traps of grain boundary play an important role for the conductivity of the poly-Si film. According to the Seto’s model, the electrons activated from the doped atoms, Phosphorous, were filled at the trap states at the grain boundaries. For simplify, the amount of free carrier in LDD layers, Nfree, can be equated to:
T D
free N N
N = + − (1), where ND+ is the number of ionized impurities and NT is the effective trap density.
Thus, the conductivity of poly-Si film is proportional to the amount of free carriers.
With the decreasing of the temperature, the amounts of activated electrons are decreasing and the ratio of trapped electrons is rising by assuming that the amount of trap states is non-varied. The few free electrons are contributed to the conduction, and thus the conductivity is decayed at low temperature. In heavily-doped poly-Si sheet, the amount of doped atoms is much larger than the trap density. Thus, the amount of activated electrons is much larger than the trap density in heavily-doped poly-Si sheet since the high doping level would lead to the degeneracy. Seto has shown that the resistivity of boron doped poly-Si film as a function of the doping level. At high doping level (Nd>>Nt), resistivity of poly-Si tends to approach the mono-crystalline one while the poly-Si may be degeneracy. Thus, heavily-doped poly-Si sheet exhibits the temperature-independent conducting behavior.
Figure 3-6 schemes that LDD layers extended out the gate overlap region behave as the temperature-dependent resistors and series connecting with the gate control region.
Although the conductivity of channel region is reversion to the temperature, the LDD sheets extended outside the gate electrode behave as the large resistors and limit the drain current.