Chapter 2 High Performance amorphous Silicon TFT
2.4 Conclusion
A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) TFT is developed in this chapter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with an extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts between source/drain metal and a-Si:H at the edge of a-Si:H island. In addition, our proposed a-Si:H TFT device exhibits superior effective carrier mobility, as high as 1.05 cm2/Vsec due to the enormous improvement in parasitic resistance. We have evidenced that the leakage current of proposed TFT is lower than the conventional BCE device under bottom-side illumination of 6000 nits. It also exhibits the better ability against the DC current stressing. The impressively high performance provides the potential of the proposed a-Si:H TFT to apply for AMLCD and AMOLED technology.
Fig 2-1(a)
(a)
Fig2-1(b)
(b)
Fig. 2-1(c)
Fig. 2-1 (a) Conventional inverted-staggered a-Si:H TFT (Structure A). (b) Akiyama’s light-shield a-Si:H TFT (Structure B) (c) The new structure a-Si:H TFT (Structure C)
VG ( V )
- 6 - 4 - 2 0 2 4 6
Drain Current I
1 0- 1 5 1 0- 1 4 1 0- 1 3 1 0- 1 2 1 0- 1 1 1 0- 1 0 1 0- 9 1 0- 8 1 0- 7
S t r u c t u r e B S t r u c t u r e C
D(A)
Fig. 2-2 ID-VG transfer characteristics of TFTs, Structures B and C with the same W / L ratio at VD=0.1V. The leakage current of Structure C is effectively suppressed in the proposed TFT structure
V
G(V)
-10 -5 0 5 10 15
Drain Current I
D(A)
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7
Linear transconductance g m (A/V )
0 5e-10 1e-9 2e-9 2e-9
Sturcture C Structure A
Fig. 2-3 ID-VG transfer characteristics and linear transconductances (gm) of TFTs, Structure A and C with the same W / L ratio. The superior current driving capability of the proposed TFT is demonstrated.
VG (V)
-15 -10 -5 0 5 10 15 20
10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5
Fig. 2-4 Comparison of ID-VG relations of Structures A and C at VD=10V under the white-light illumination of 6000 nits. The inset sketches the illumination from the bottom-side of the TFTs.
Drain Current I
D(A)
Structure A
Structure C
V
D(V)
0 2 4 6 8 10 12 14
Drain current I
D(x10
-7A) 2 4 6 8
Structure C Structure A
0
Fig. 2-5 A comparison of output characteristics (ID-VD) for the proposed TFT and the conventional inverter-staggered TFT. The current crowding is found in the conventional inverter-staggered TFT, Structure A.
V
G(V)
5 6 7 8 9 10 11 12 13
R p (o h m )
0 2x106 4x106 6x106 8x106 10x106
Structure C Structure A
Fig. 2-6 The gate voltage dependence of the parasitic resistance Rp of Structures A and Structure C.
Fig. 2-7 The distribution of electrons near the drain region in the structures A. The arrow heads labeled in the two figures present the carrier transport directions.
.
Fig. 2-8 The distribution of electrons near the drain region in the structures C. In the proposed structure, the electrons can transport though contacts, the side wall and the top contact of drain metal overlap region.
S tre s s tim e (s e c )
0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0
Drain cruuent I D (A)
1 .5 x 1 0-6 1 .6 x 1 0-6 1 .7 x 1 0-6 1 .8 x 1 0-6 1 .9 x 1 0-6 2 .0 x 1 0-6 2 .1 x 1 0-6
S tru c tu re A S tru c tu re C
Fig. 2-9 The evolution of conducting currents in TFTs during bias temperature stressing (BTS). The current of 200nA was conducted on Structure A and C at 60oC with the gate bias of 11.25 V and 9V, respectively.
V G ( V )
- 1 0 - 5 0 5 1 0 1 5
Drain Current I D (A )
1 0 - 1 5 1 0 - 1 4 1 0 - 1 3 1 0 - 1 2 1 0 - 1 1 1 0 - 1 0 1 0 - 9 1 0 - 8 1 0 - 7 1 0 - 6 1 0 - 5
S t r u c t u r e A S t r u c t u r e C
Fig. 2-10 The ID-VG relationships of the TFTs after bias temperature stress. The threshold voltage shift of structure A and C is 1.75V and 0.75V, respectively.
Chapter 3
Investigation of Poly-Silicon Thin Film Transistors with/without LDD Structure at Temperatures and under AC stress
3.1 Introduction
Poly-Silicon Thin film transistors (Poly-Si TFTs) have been wily applied on the flat-panel displays like AMLCD and AMOLED. The major advantages of poly-Si TFTs are the higher driving capability than the amorphous silicon devices, and the existence of complementary devices.[3.1-3.5] Taking advantage of these features, poly-Si TFTs can be used to incorporate the integrated peripheral driving circuitry and switching transistor in the same substrate for flat-panel displays.[3.6-3.7] The integration of driver circuits would reduce the assembly complication and cost dramatically. If the mobility of poly-Si TFTs is further increased, this poly-Si technology will realize the system on panel (SOP) which will integrate memory, CPU, and display.[3.8-3.9] TFT devices in functional circuits serve as the switches and suffer the high frequency voltage pulses. Previous research reports have shown a relationship between the creation of states and hot-carriers effect by performing DC stress.[3.10-3.13] The degradation mechanism of n-channel TFT under dynamic voltage stress, however, has not been clarified yet.[3.14-3.16] The degraded TFT will seriously influence the operation of the circuits.
In addition, the dangling bonds in the grain boundaries in the poly-Si film serve as the trapping centers that play a cruel role for the electrical performance of poly-Si TFT. [3.17-3.18] These defect states in energy band gap would enhance the carrier to tunnel at the high field.[3.19-3.20] Therefore, the leakage current due to trap-assisted
tunneling effect is much larger in poly-Si TFTs than in the single crystal MOSFETs.
Trap-assisted tunneling effect is known to be strongly dependent on the electrical field.
In order to reduce the horizontal electric field around a drain, the lightly doped drain (LDD) structure is widely used for poly-Si TFTs. Some reports have demonstrated that the light-drain doping (LDD) technology can effectively reduce the electric field at the drain region and suppress the leakage current. [3.21-3.22] It also can keep down the kink effect resulted from the impact-ionization of energetic carriers which usually leads to the undesirable effect in electrical characteristics of TFT. The LDD-structure, hence, is necessary for the application of poly-Si TFT, especially for the N-channel TFTs.
Moreover, the large area electronics or the flat-panel displays comprised of poly-Si TFTs are used by peoples at the globe. Thus, the displays should keep the performances well at all kinds of the environments. Temperature usually influences the characteristics of solid-devices, and its relative effects are important for the application of Poly-Si TFT technology. In this chapter, the temperature effects on the n-type poly-Si TFT with/without LDD structure was firstly investigated. Then we observed the AC stress effects on n-channel poly-Si TFTs without LDD to clarify the degradation mechanism.