Chapter 2 High Performance amorphous Silicon TFT
4.2 Device Fabrication
Top-gated poly-Si TFTs were fabricated on glass substrate by low-temperature processes. Buffer SiO2 films and 90-nm-thick amorphous silicon films were deposited by plasma enhanced chemical vapor deposition (PECVD), and subsequently, the films were dehydrogenated by furnace annealing. After dehydrogenation, the a-Si films were crystallized by sequential lateral solidification (SLS) laser annealing process.
XeCl excimer laser, 2) a reticule mask with chevron-shaped apertures, 3) projection optics, and 4) a high-precision translation system. The SLS process is an excimer-laser projection-based scheme for crystallization of thin films on amorphous substrates. This method can be used to readily produce a wide range of microstructures through manipulation of grain boundary placement within the crystallized material. Following the SLS process, 100-nm-thick gate oxide was deposited by PECVD. MoW was sputtered as a gate electrode and phosphorous ion doping was used to form source and drain (S/D) regions. The dimension of TFTs in this work was 20μm for channel width (W) and 5μm for channel length (L), respectively. The overlap between gate electrode and S/D junction is 1μm.
4.3 Results & Discussions
4.3.1 Electric Properties & DC stress
Figure 4.1(a) shows the top view of a high-resolution scanning electron microscopy (SEM) image of SLS laser annealed poly-Si film. The SLS laser annealed poly-Si thin film includes a domain region containing a mixture of plurality of crystals substantially parallel to the carrier body. The crystals may be columnar or capillary crystals. The grain boundaries present in the SLS laser annealed poly-Si film can be divided into two types, namely main-GB and sub-GB. The orientation of GB which is perpendicular to channel direction is called main-GB, as labeled by the arrowhead in Fig. 4.1(a). Furthermore, the grain boundaries which lie between main-GBs are called sub-GBs and substantially parallel to the transport paths of carriers flow drifted by the electric field of the drain side. The width of each main-GB is about 100 nm and the space between main-GBs is about 10 µm measured by atomic force microscopy (AFM). Figure 4.1(b) shows the AFM image, the height of
protrusion is about 100nm at the grain boundary region.The channel length of TFTs in this study is 5μm for all samples and relatively smaller than the main poly-Si grain (10μm). Therefore, the channel region of TFT may locate entirely inside the main poly-Si grain zone. But some TFT devices would contain a main-GB within the channel. The two kinds of poly-Si TFT were depicted in the Fig. 4.2(a). Figures 4.2(b) and (c) show the microscope picture of the GB and NGB TFT, respectively. An obvious duck-line is placed at the middle of the channel of GB TFT. We named the TFTs with the main-GB GB-TFT, and ones without the main-GB NGB-TFT for short in this study. Figure 4.3 illustrates the transfer curves, ID-VG, and linear trans-conductance (gm) of GB-TFT and NGB-TFT, respectively. The field effect mobility (μFE) was extracted from a peak linear trans-conductance at Vd = 0.1 V.
According to Fig. 4.3, NGB-TFT has higher μFE of 283.2 cm2 / Vs than GB-TFT of 262.5 cm2 / Vs. Additionally, the threshold voltage (Vth) and sub-threshold slope (SS) of poly-Si TFTs are extracted for discussion. The Vth is defined as the gate voltage required to achieve a normalized drain current of ID = 10-8 A at Vd = 0.1 V with a normalized W/L ratio. The Vth of NGB and GB TFT is 2.64 and 2.90V, respectively.
The NGB TFT owns superior SS value of 0.39V/dec than that of GB TFT, 0.43V/dec.
The better conducting characteristics were exhibited in NGB-TFTs. Moreover, the capacitance-voltage (C-V) characteristics of the TFTs were investigated using HP4284, as illustrated in Figs. 4.4. The voltage signals were conducted on the gate electrode of the TFT, and the S/D electrodes were connected together to the ground. It was found that the CV curve of NGB TFT transfers abruptly from the turn-off state to the channel-formation state. The CV transition curve of GB TFT shows a slightly slow in comparison with the NGB TFT as the voltage is increased from -10 to 15V.
The existence of the trap numerous region (GB) at the middle of the channel in GB
would be filled by the field-induced carrier, and thus the GB TFT exhibits the slow transition in CV measurement.
In order to examine the GB effects on the TFT reliability characteristics, the hot carrier stressing tests were performed on the poly-Si TFTs. As for the DC stress conditions, a gate voltage of 6V and drain voltage of 12V were applied. Figure 4.5 shows the ID-VG characteristics of NGB-TFTs after stress for 10 and 100 s, respectively. It is apparent that with increasing stress time the impact of the applied stress leads to a decrease of on-current in the above threshold region of the ID-VG
characteristics, while TFT operating in the linear region. The mobility of NGB-TFT is decayed from 283.2 to 46.9 cm2 / Vs after 100 seconds stress. Moreover, the Vth is shift from 2.64 to 4.6V and SS is increased to 0.64 V/dec after the stress.
For comparison, figure 4.6 depicts the ID-VG relations of GB-TFT after the DC stress for 10 and 100 s. The distinct difference in endurance against the hot carrier stress is demonstrated. The NGB-TFT was degraded rapidly during the DC stressing, but the electrical properties of GB-TFT kept at a good level. For the case of GB-TFT, both threshold voltage and sub-threshold slope almost unchanged, and the mobility was decreased from 262 to 227 cm2 / Vs after 100 s stress. These results made a remarkable comparison to the intrinsic properties of both devices. Although the GB TFT owns lower current driving capability, it has outstanding endurance against the DC stressing. In poly-Si TFTs the electrical degradation is often characterized by a decrease of the subthreshold slope, mainly due to the generated traps in the grains and a threshold voltage shift caused by charge trapping in the gate oxide and at the interface states, as shown in Fig. 4.5. However, the GB-TFT showed that both subthreshold slope and threshold voltage remain unchanged. This indicates that the degradation of the GB-TFT occurred due to neither charge trapping in the gate oxide
nor the creation of traps at the deep states. We can infer that the tail states produced by the strained bounding are responsible for the degradation of GB-TFT.
To clarify the distinct difference between the TFTs’ electrical reliabilities, the effective trap density of the TFTs were extracted. According to Seto’s model, the effective trap density (NT) of NGB and GB TFT is extracted to be 4.95 x1017 and 8.64 x1017cm-3, respectively. For brevity, the increasing in NT of GB-TFT is assumed to be mainly contributed by the 100 nm trap-numerous region in the 5μm channel. Thus, a 100 nm region with trap concentration of 1.84 x1019 cm-3 was added in the middle of channel of the GB TFT, while other regions had trap concentration about 5x1017 cm-3 . The trap concentration of 4.95 x1017 cm-3, however, was uniformly distributed in whole channel of the NGB TFT. Then, the electrical field distribution was simulated by a simulation tool ISE-TCAD. The comparison between GB and NGB TFT in electric field is illustrated in Fig. 4.7. It was found that the electric field near the drain region was reduced while GB located in the center of the channel, as shown in Fig.
4.7. For GB-TFT, the maximum of electric field at the drain shows about 27% lower than that without grain boundary in the channel. The reduction of electric field at the drain side effectively contributed to the suppression of hot carrier effects.
4.3.2 AC stress
For logic circuits application, the influences of AC gate pulse on poly-Si TFTs have to be clarified. The dimensions of TFTs in this work were L=9μm, W=6μm and the overlap of gate metal and S/D junction is 1μm. The cross section views of TFTs were illustrated in Fig. 1. The stress pulses were performed on the gate electrode as the dynamic stress and source/drain were grounded, as shown in the inset of Fig. 1. As for
the stress condition, we used the rectangular pulse with amplifier of ±10V and frequency of 500kHz. Both the rising time (Tr) and falling time (Tf) were 100 ns.
Figs. 4.8 and 4.9 present the ID-VG relations of GB and NGB TFT with the dynamic stress times for 10 to 1000 s, respectively. The distinct decrease in on-current of the TFTs was found with the increasing stress duration. The mobility of NGB TFT is decayed from 282.9 to 204 cm2/Vsec after 1000s stress. Both the sub-threshold swing (0.36 V/dec.) and threshold voltage (2.34V) kept well during the stressing.
Accordingly, GB TFT possessed the lower value of mobility (136.9 cm2/Vsec) than the initial mobility (243 cm2/Vsec). A slight degradation was found in the threshold voltage and subthreshold swing of the GB TFT. From the evolution of the transfer characteristics at the linear operation with stress time, it is apparent that the impact of the applied stress leads to a parallel decrease of the on-current operated at the above threshold region of the ID-VG characteristics.
Contrary to the results of DC stress, the NGB devices exhibit better endurance against the AC gate pulse stress. The degradation of AC stress is usually contributed to the occurring of hot carrier near the S/D electrode region, as mentioned in chapter 3.
We have known that the impact of hot carrier effect in DC stress on GB TFT is weaker because of the reduction of electric field at the drain region. The damage of GB TFT should be contributed by other factors under AC gate pulse stress. The distinct differences between the NGB and GB device are the existence of GB and the surface roughness of poly-Si film. The NGB TFT owns smooth plane for the channel region, as shown in Fig. 4.1(b). By contrast, an obvious protrusion of 100nm is located at the middle of GB TFT. The thickness of gate oxide at protrusion is thinner than the other region in GB TFT. The simulation tool was performed to understand the difference between two devices in electrical field at the protrusion region. Figs. 4.10(a) and 4.10(b) illustrate the distribution of electrical field at the
protrusion and smooth plane. The interface of oxide/poly-Si at protrusion is suffered the higher electrical field than that at the smooth plane. The state creation and charge trapping in the oxide at the protrusion should be responsible for the degradation. Thus, the difference in degradation evolutions between GB and NGB TFTs under AC gate bias is properly resulted from the protrusion. Except to the damage region near the S/D junctions, GB TFT possessed the damaged region locating at the protrusion due the high gate bias stress.
4.4 Conclusions
The comparison of electrical stability between GB and NGB-TFT has been shown in this study. The NGB-TFT owns superior conducting ability than the GB TFT which contains a 100-nm trap-numerous region at the middle of the channel. However, the GB-TFT exhibits the better endurance against DC stress than the NGB-TFT. Based on the simulation result, the existence of GB in the middle of channel of poly-Si TFT would reduce the electric field in the drain region significantly. Accordingly, the GB-TFT suffers relatively lighter impact of hot carrier stress and maintains electrical characteristics well during the DC stressing. The NGB-TFT was seriously degraded by the DC stress with the high electric field at the drain side.
Nevertheless, the distinct electrical behaviors of the TFTs were demonstrated under the AC gate bias stress. Due to the existence of protrusion in the channel, GB-TFT shows weaker endurance against the AC gate pulse stress than that of NGB TFT. The magnitude of the vertical field at the protrusion is stronger than the other regions in GB TFT. The strong electric field would lead to the state creation and charge trapping at the protrusion and reduce the device’s electrical performance. Consequently, grain
boundaries perpendicular to the channel direction in SLS poly-Si TFT would reduce the horizontal field near the drain side. But the protrusion of grain boundaries of SLS poly-Si film would lead to the larger vertical field. The influences of horizontal and vertical fields can be observed and identified under hot carrier and AC gate stresses.
4-1(a)
4-1(b)
Fig. 4-1 (a) Thetop viewof a high-resolution scanning electron microscopy (SEM) image of SLS laser annealed poly-Si film. The orientation of main-GB and sub-GB is perpendicular and parallel to channel direction of the TFTs we utilized, respectively.
(b) The AFM image of SLS poly-Si film, the height of protrusion is about 100nm at the grain boundary region
4-2(a)
4-2(b)
4-2(c)
Fig. 4-2 (a) GB-TFT owns a main-GB in the middle of the channel. NGB-TFT lies in the main-GB free region. (b) The microscope picture of GB TFT (c) The microscope picture of NGB TFT
Gate voltage (V)
-10 -5 0 5 10 15 20
Fig. 4-3 ID - VG transfer characteristics of NGB and GB TFTs with the same W / L ratio. The NGB TFT has larger field mobility (283.2 cm2/Vsec) than that of the GB device (262.5 cm2/Vsec).
Voltage (V)
-10 -5 0 5 10 15
C a pac it anc e ( f F )
2 3 4 5 6 7 8 9
NGB TFT GB TFT
Fig. 4-4 The capacitance-voltage (C-V) characteristics of GB and NGB TFTs. The CV transition curve of GB TFT shows a slightly slow in comparison with the NGB TFT.
Gate Voltage (V)
to 12% of the magnitude of the initial value.Drain Current I
D(A)
Gate voltage (V)
position along channel
0 1 2 3 4 5 6
Ele c tric Fie ld ( x 1 0
5V/ cm)
0 1 2 3 4 5 6
GB TFT NGB TFT
Fig. 4-7 The electric distribution in the channel region of the TFTs under the bias conditions VG=6V and VD=12V. The main-grain locates at the center of the channel in GB-TFT. For GB-TFT, the maximum of electric field at the drain shows about 27%
lower than that without grain boundary in the channel
VG (V) 1000 s. The mobility of NGB TFT is decayed from 282.9 to 204 cm2/Vsec after 1000s stress.
VG (V) s. The mobility of GB TFT is decayed from 243 to 136.9 cm2/Vsec after 1000s stress.
Drain Current ID (A) Gm
Fig. 4-10 The distribution of electrical field at (a) smooth plane and (b) the protrusion.
Chapter 5
Non-Volatile Memory Devices Fabricated on Glass Substrate Using Low Temperature Poly-Si Technology
5.1 Introduction
In the electrically erasable programmable read only memory (EEPROM) semiconductor device area, there are essentially two dominant technologies which compete for an ever-expanding world market: (1) floating gate EEPROM’s and (2) SONOS (historically MNOS) or floating-trap EEPROM’s. [5.1-5.5] In 1960’s, the electronic industries urgently needed a new kind of memory device to replace the magnetic-core memory due to the high cost, large volume, and high power consumption of the magnetic-core memory. D. Kahng and S. M. Sze invented the floating-gate (FG) nonvolatile semiconductor memory at Bell Labs in 1967 [5.6]. To date, the stacked-gate FG device structure, continues to be the most prevailing nonvolatile-memory implementation, and is widely used in both standalone and embedded memories. The invention of FG memory impacts more than the replacement of magnetic-core memory, and creates a huge industry of portable electronic systems. The most widespread memory array organization is the so-called Flash memory, which has a byte-selectable write operation combined with a sector
“flash” erase. However, once the tunnel oxide has been created a leaky path, all the stored charge in the floating gate will be lost. When the tunnel oxide is thinner for the first consideration, the retention characteristics may be degraded. And when the tunnel oxide is made thicker to take the isolation into account, the speed of the operation will be slower. Therefore, there is a tradeoff between speed and reliability
and the thickness of the tunnel oxide is compromised to about 8-11 nm, which is barely reduced over more than five successive generations of the industry.
To overcome the scaling limits of the conventional FG structure, SONOS [5.7-5.9]
nonvolatile memory device is mostly mentioned candidate [5.10-5.12]. The nitride layer is used as the charge-trapping element, as for SONOS in Fig. 5-2. The intrinsic distributed storage takes an advantage of the SONOS device over the FG device, its improved endurance, since a single defect will not cause the discharge of the memory.
There are a number of applications for SONOS NVSMs, with particular emphasis on
“drop-in” modules for the application-specific integrated circuits (ASICs) such as wireless application, embedded NVSM in microcontrollers, and the so-called smart cards. [5.13-5.14] Future smart cars in public transport schemes will be operated using RF data transmission without the need for external contacts and power supplies.
SONOS NVSMs may be employed in mobile computing systems such as handheld PCs and notebook and subnotebook PCs; digital still picture cameras; smart digital phones; data acquisition systems for industry, commerce, and military; audio recorders; GPS systems for automobiles, ships, and planes; and communication equipments, including cellular base stations, PBS equipment, and digital routing switches. In addition, it is attractive to fabricate the non-volatile memory devices on insulator substrates, such as glass ones. Smart cards which embed the memory cells may be manufactured using glass substrate for low cost. Moreover, the integration of systems on flat panels using low-temperature poly-silicon technology has been attractive. The high performance of poly-Si TFT processes enables the monolithic integration of analogue and digital display driver circuits as well as other peripheral functions on the active matrix substrate. The degree of circuit integration will continue to increase as device characteristics improve further. In the future, system on panel will be implanted with the advanced poly-Si technology. The nonvolatile
memories devices fabricated on the glass can increase the flexibility of circuits for the display. The previously reported poly-Si TFT EEPROM’s using low-temperature poly-Si TFT is composed of two active regions of poly-Si layer[5.15-5.17]. The area of memory device is an important consideration for the high density memory manufacture. In this chapter, we demonstrate two non-volatile memory devices, (1) floating gate EEPROM’s and (2) MONOS EEPROM’s. The devices were fabricated using a low-temperature poly-Si technology with good characters. The maximum temperature of processing is below 650oC for the glass substrate. We used the metal layer as the floating gate for the EEPROMs. Similar to the silicon/oxide/nitride/oxide/silicon (SONOS) devices in Si technology, the oxide-nitride-oxide (ONO) stack plays as the tunneling oxide/charge storage layer/control oxide. Moreover, the area of this non-volatile memory device is half the prior poly-Si TFT EEPROM. The memory characteristics and reliabilities had also been investigated in this chapter.
5.2 Device Fabrication
5.2.1 Floating-Gate EEPROMFigs. 5-1(a) show the schematics of the planar poly-Si TFT EEPROM’s using p-channel poly-Si TFT’s as the control gate electrode in this study. To fabricate poly-Si TFT EEPROM’s, an active amorphous silicon film (a-Si) of 100 nm thickness was deposited by plasma enhanced chemical vapor deposition (PECVD).
Subsequently, the films were dehydrogenated by furnace annealing. After dehydrogenation, the a-Si films were crystallized by excimer laser annealing process.
Following the laser process, 15nm-thick gate oxide was deposited by PECVD. Then
annealing process was performed to activate the dopant impurities. Mo was sputtered and defined as a floating gate metal of T1 and T2. Then 200nm block oxide was formed by PECVD. The dimensions of T1 in this work were L=6μm, W=16μm and the overlap of gate metal and S/D junction is 1μm. In addition, the length and width of T2 is 6 and 16μm, respectively. To investigate the influence of overlap area of floating gate and S/D in T2, two memory cells A and B were made. The device A is illustrated
annealing process was performed to activate the dopant impurities. Mo was sputtered and defined as a floating gate metal of T1 and T2. Then 200nm block oxide was formed by PECVD. The dimensions of T1 in this work were L=6μm, W=16μm and the overlap of gate metal and S/D junction is 1μm. In addition, the length and width of T2 is 6 and 16μm, respectively. To investigate the influence of overlap area of floating gate and S/D in T2, two memory cells A and B were made. The device A is illustrated