A Distributed Model for determining Border Traps

In general, the bulk oxide traps can interchange charge with mobile carriers in the semiconductor bands by tunneling mechanism in devices. Hence, Fig. 3.1 schematically exhibits the mechanism between bulk-oxide traps and valence band of the p-type MOS devices in the accumulation gate bias. The time constant connected with charge exchange between bulk-oxide traps and semiconductor is regulated by tunneling mechanism that has exponential dependence on the trap distance x from the interface of oxide/semiconductor [5, 7-10] as follows:

𝜏(𝑥) = (1 − 𝑓₀)𝜏₀𝑒^2𝜅𝑥 (3.1) Here, 𝜏₀ is the time constant of the interface trap which equals 1/(𝑛_𝑠𝜎𝑣_𝑡ℎ) with σ being the trap cross-sectional area, and vth is the thermal velocity of hole. Other parameters in Eq.(3.1) are as follows: f0 is the Fermi-Dirac function which a trap occupied by an electron at energy E, and κ is the attenuation coefficient for an energey E wavefunction of an hole decaying due to an energy barrier Ev,ox> E.

𝜅 = √2𝑚^∗(𝐸_{𝑣,𝑜𝑥}− 𝐸)/ℏ (3.2) m* is the hole effective mass of the gate dielectric, and Ev,ox is the bottom energy of the gate insulator band (tunneling barrier), as shown in Fig. 3.1.

The bulk-oxide traps at a specific depth x and energy E change occupancy with respond to a small-signal ac modulation for a given dc bias. The border traps at energy about E ~ E_f

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are most responsible for the small-signal capacitance. In the other words, we assume the border traps located within certain distance from the interface maintain a Fermi level the same as the semiconductor. Then, we can find that the influences of the bulk-oxide traps at certain depth x and energy E can be modeled by a series of connecting capacitance and conductance on the small-signal MOS admittance. The bulk-oxide traps in an incremental depth Δx at x and incremental energy ΔE at E are symbolized by the incremental capacitance ΔC_bt (E, x) and the incremental conductance ΔGbt (E, x) which are connected in series. If the density per volume per energy of bulk-oxide traps is N_bt in units of eV^-1cm^-3, then [5-6] the equation of ΔC_bt will indicates:

Δ𝐶_bt(𝐸, 𝑥) = ^{𝑓0(1−𝑓}_𝑘𝑇^{0)𝑞2𝑁bt} 𝛥𝐸 𝛥𝑥 (3.3) And the ΔC_bt (E, x) andΔG_bt (E, x) have the relationship in time constant 𝜏(𝑥)

_Δ𝐺^{Δ𝐶𝑏𝑡(𝐸,𝑥)}

𝑏𝑡(𝐸,𝑥) = 𝜏(𝑥) = (1 − 𝑓₀)𝜏₀𝑒^2𝜅𝑥 (3.4) In order to integrate with the continuous energy distribution of bulk-oxide traps, the ΔCbt (E, x) andΔG_bt (E, x) in serial combination have to be transfer to a parallel connection of the incremental admittanceΔYbt (E, x). Due to the factor f0(1-f0) has pointy peak at E = Ef , the attenuation coefficient k in Eq.(3.2) is determined as a constant with E = Ef in the integration.

Therefore, the total incremental admittance at certain depth x and energy E is indicated for 𝛥𝑌_bt(𝑥) = ∫ 1 ¹

𝑗𝜔𝛥𝐶bt(𝐸,𝑥)+ ¹ 𝛥𝐺bt(𝐸,𝑥)

𝐸 =^{𝑞2𝑁btln⁡(1+𝑗𝜔𝜏}_𝜏 ^{0𝑒2𝜅𝑥)}

0𝑒^2𝜅𝑥 𝛥𝑥 (3.5) Because of a continuous energy distribution of the border trap all over the gate oxide thickness, an equivalent circuit of the distributed model in the MOS device is illustrated in Fig. 3.2, where the oxide capacitance is separated into an infinite number of serial slices with branches of ΔYbt(x), which is linked in different depth. Here, 𝜖_𝑜𝑥 is the permittivity of the gate dielectric and C_s is the semiconductor capacitance.

Consequently, if we define Y(x) to be the equivalent admittance at the point x looking into the semiconductor in Fig. 3.2, the recursive nature of the circuit will give the admittance

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of the next point x +Δx as

𝑌(𝑥 + 𝛥𝑥) = 𝛥𝑌_bt(𝑥) + 𝛥𝑥 ¹

𝑗𝜔𝜖𝑜𝑥+_𝑌(𝑥)¹ (3.6) Then, substituting Eq.(3.5) forΔY_bt(x), the first order terms in Δx will yield a differential equation for Y(x)

^𝑑𝑌_𝑑𝑥= −_𝑗𝜔𝜖^𝑌2

𝑜𝑥+^{𝑞2𝑁btln⁡(1+𝑗𝜔𝜏}_𝜏 ^{0𝑒2𝜅𝑥)}

0𝑒^2𝜅𝑥 (3.7) There are two equations as boundary conditions as follows:

𝑌(𝑥 = 0) = 𝑗𝜔𝐶_𝑠+ 𝑗𝜔𝐶_𝑖𝑡+ 𝐺_𝑖𝑡 (3.8) where C_s is the semiconductor capacitance and C_it and G_it are contributions from interface traps and given in [6] as

𝐶_𝑖𝑡 = ² _𝑖𝑡 𝑛(𝜔𝜏_𝑖𝑡)/ (𝜔𝜏_𝑖𝑡) (3.9) 𝐺_𝑖𝑡 = ² _𝑖𝑡 𝑛[1 + (𝜔𝜏_𝑖𝑡)²] /2𝜏_𝑖𝑡 (3.10) where D_it (eV⁻¹· cm⁻²) is the interface trap density.

Moreover, Eq.(3.7) need to be numerically solved to obtain the total admittance looked into semiconductor by gate

𝑌(𝑥 = _𝑜𝑥) ≡ 𝐺_tot+ 𝑗𝜔𝐶_tot (3.11) For the typical measured frequency limit of 1 kHz - 1 MHz, 1.4*10^-6 < 𝜔𝜏₀ < 1.4*10^-3, the bulk-oxide traps can’t respond to the ac signal and Ctot is equal to Cox in series with Cs, so the C_tot varies with ln(1/𝜔) linearly, and Gtot varies with 𝜔, that is to say, Gtot /⁡𝜔 ~ constant.

For a given bias, the constant Gtot /⁡𝜔 shows that the response of the border traps causes wide frequency dispersion because of their various depth distribution, in other words, an obvious distinction from conventional interface traps [6]. Then, for a given frequency of 𝜔 < ⁡1/𝜏₀, the depth of the slow traps that respond to the small-signal can be estimated by making the factor 𝜔𝜏₀𝑒^2𝜅𝑥 in Eq.(3.7) equal unity, as the exhibition 𝑥⁡~⁡(2𝜅)⁻¹ln(1/𝜔𝜏₀), which is in the range of 0.1~1nm.

When 𝜔 = 0 or in dc condition, the circuit of Fig. 3.2 becomes a purely capacitive

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circuit model, and Eq.(3.7) is simplified to a real equation for C(x) as follows:

^𝑑𝐶_𝑑𝑥= −_𝜖^𝐶2

𝑜𝑥+ ²𝑁_bt (3.12) The capacitance boundary condition at x=0 is C_s. For the uniform distribution of N_bt , Eq.(3.12) can be analytically resolved to produce

𝐶(𝑥) = 𝐶₀^{(𝐶𝑠+𝐶0) exp(2𝑞𝑥√}

𝑁bt𝜖𝑜𝑥)+(𝐶_𝑠−𝐶₀)

(𝐶𝑠+𝐶₀) exp(2𝑞𝑥√^𝑁bt_𝜖𝑜𝑥)−(𝐶_𝑠−𝐶₀) (3.13) Here,𝐶₀ = √𝜖𝑜𝑥𝑁_bt. If 2 √𝜖𝑜𝑥𝑁_bt >> 1, then C(x = tox) ≈ √ ²𝜖_𝑜𝑥𝑁_bt , which is insensitive to Cs. Certainly, this is only a matter of theoretical interest, nevertheless, it would take much longer than the age of the universe to charge up all the border traps in the gate dielectric.

Besides, the C_s in accumulation region of the case is very high. From Eq.(3.13), Ctot(dc)⁡⁡≈ C0coth(C0/Cox), is larger than Cox. This result is in contrast to the interface states or lumped-circuit bulk-oxide traps model, which don’t yield dispersion when shorted out by large Cs. Consequently, frequency dispersion in accumulation region is a good indicator of distributed bulk-oxide traps. Moreover, the model should be applicable to any oxide/semiconductor interface with border traps since the derivation isn’t depend on material.

However, some parameters, such as v_th and κ, are material dependent and need to be calculated compatibly [11].

Furthermore, the time constant 𝜏₀ is gate-voltage dependent which is assumed to submit standard SRH theory for advanced devices, one should account for inversion layer quantization and its impact on the carrier recombination at the interface. A final factor which must be carefully investigated is that most of the oxide traps show inelastic tunneling transitions, while by default, elastic tunneling is assumed in many cases [4].

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3.3 The Relationship between the Model and the measured