Al 2 O 3 Inter-layers
2.5 Conductance Method
Impedance measurements of MOSCAPs as a function of voltage, frequency, and temperature of high-k/semiconductor interfaces contain contributions from Dit that can be extracted in different ways [36]. The conductance method, established by Nicollian and Goetzberger in 1967, is one of the sensitive methods to quantify Dit [37]. It is the most complete method, because it yields Dit in the depletion and weak inversion portion of the band gap and the capture cross-sections for majority carriers. Although Berglund, Terman and high-low frequency extracted methods could determine interface states, they might overestimate the Dit value on low band gap III-V semiconductor because the signal may induce by minority carrier response. Fig 2.21 (a) shows energy band diagram of n-type MOSCAP in depletion region. A dc gate bias is applies to the gate which superimpose on a small amplitude (~25 mV) ac signal with frequency f (typically between 1 MHz and 100 Hz).
Besides, it displays an arbitrary interface states density distribution, the Fermi level EF and the intrinsic level EI. The gate voltage Vg which determines the Fermi level position at the interface induces a space charge and band bending. The ac signal causes a periodic change in band bending and the gate bias determines the energy level position where the Fermi level oscillates at the interface. The traps with energy levels near the Fermi level are capable of changing their occupancy. The conductance is representing the loss mechanism due to interface trap capture and emission of carriers. The equivalent circuit of MOSCAP with interface states in depletion region appropriate for the conductance method is simplified as shown in Fig. 2.21 (b). It consists of the gate oxide capacitance, Cox, the semiconductor capacitance, Cdos (ω,ψs), the interface trap capacitance, Cit (ω,ψs), equivalent parallel conductance, Gp (ω,ψs) and a series resistance, Rs. The simplified circuit model supposes the minority carrier response is negligible. The equivalent circuit of impedance analyzer with the
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measured capacitance Cm and conductance Gm is shown in Fig. 2.21 (c). The frequency dependence is related with the characteristic trap response time, τ=2π/ ω, where ω is the angular frequency ( f is measured frequency).
The interface trap capacitance which is induced by the interface state density is
Cit = qDit, where q is the elemental charge. The trap response time for hole is given by Shockley-Read-Hall statistics of capture and emission rate:
average thermal velocity of majority carriers (hole), Nv is the effective DOS of the majority carrier (hole) band, kB is the Boltzmann constant, and T is the temperature.The conductance method is the way of analyzing the loss that is caused by the variation in the trap level charge state. In fact, interface trap are continuously distributed all over the band gap rather than single energy level. Capture and emission occurs chiefly by traps located within a few kT/q above and below the Fermi level, giving rise to a time constant dispersion and indicating the normalized conductance as follows:
measured capacitance Cm, and the measured conductance Gm, are shown as follows:2
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where A is the device area. In addition, Et can be determined at the specific frequency from (Gp/ω)max and applying Eq. (2.2). Fig. 2.22 shows the behavior of the interface trap time constant at room temperature as a function of capture cross section, which determines the part of interface traps in the band gap observable in the MOS admittance characteristic. Fig. 2.23 shows trap level position calculated from Eq. (2.2) using the values for the average thermal velocity and the density of state band for In0.53Ga0.47As and a capture cross section σ = 1×10-17 cm2, which chosen from Fig. 2.22. The trap characteristic frequency as a function of temperature determines the part of interface traps in the band gap conspicuously in the MOS admittance characteristic. Because of the representative measurement frequency between 100 Hz and 1 MHz, it’s difficult to extract the interface state density over the whole band gap at room temperature. Nevertheless, the Dit of whole band gap profiles can be extracted by measuring in the various temperatures. For In0.53Ga0.47As, the traps near midgap could be observed at room temperatures. However, if we want to determine the traps which close to the band edges, we have to measure the impedance at lower temperature because of the increasing of the trap response time. Next section, we extract Dit at room temperature and compare the influence of the interface state with various PDA conditions in same Al2O3 inter-layer and various Al2O3 cycles at same PDA conditions. As well correspond to XPS interfacial chemical properties.
2.5.1 MOSCAPs with FGA under Various PDA Conditions
Fig 2.24 (a) (b) (c) (d) show parallel conductance maps of p-type Pt/Ti/TMA+Al2O3
1cycle+ZrO2/In0.53Ga0.47As MOSCAPs with FGA under different PDA conditions, at temperature 300K. The Dit is estimated by the multiple peak values of the curves, which indicate the maximum of [(Gp/ω)/Aq] with a factor of 2.5[see Eq. 2.5]. In Fig 2.24, all maps
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show distinct signal at the gate voltage between -1 and -2 volts and lower frequency. We speculate that these responses might be the bulk oxide traps or slow traps, resulting in high frequency dispersion at Vg= -2 volts, which is consistent with aforementioned section. Among these plots, we can find the color variation in this region is more indistinct with PDA 300 °C.
However, because of a great deal of slow traps signal at accumulation region, the response of Dit at depletion region is suppressed and results in more invisible signal. Therefore, the [(Gp/ω)/Aq]-f curves from Fig. 2.25 are demonstrated here, and the interface states can be acquired with the factor of 2.5. From these curves, we can find that the peak value is getting larger as increasing PDA temperature. From Fig. 2.30 (a) and Table 2.4, it is observed that the Dit of PDA 300 °C is slightly smaller than the as-deposited one, but mostly better than PDA 400 °C and 500 °C. Accordingly, higher PDA temperature should be avoided so as to prevent the inferior native oxide and interface quality which might degrade electrical characteristics.
Furthermore, the parallel conductance maps of Al2O3 5 cycles inter-layer are shown in Fig. 2.26 and the [(Gp/ω)/Aq] curves in Fig. 2.27 with FGA under various PDA condition.
These contour maps also show the slow traps at the high negative gate voltage, especially at PDA 500 °C. Because of the signal between Vg= -1 and -2 volts at lower frequency is much stronger than the response of interface states, we can’t see more obviously about the Dit signal.
Then, we define the interface state quantitatively by Fig. 2.27 and show in Fig. 2.30 (b) and Table 2.4. Compare to these values with various PDA temperatures, we demonstrate that the Dit at PDA 300 °C is much lower than others.
Moreover, from Fig. 2.28 and Fig. 2.29, for Al2O3 10cycles inter-layer, the signal of PDA 500 °C in accumulation region is apparent and the peak of the [(Gp/ω)/Aq] curves is more seriously. Then, from Fig. 2.30 (c) and Table 2.4, these values indicate that the PDA 300 °C one is the best case of all the samples.
In order to be convinced of the conclusion which the PDA 300 °C is the best one of all the conditions and to prevent more Al2O3 inter-layer from interfering with the signal between
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ALD-TMA/Al2O3 and Al2O3/ZrO2 interface, we analyze the interfacial chemistry characteristics of ALD-TMA/Al2O3 1 cycle/ZrO2 on p-type In0.53Ga0.47As with FGA under different PDA conditions.
XPS spectra were taken by Ga 2p3/2, In 3d5/2, and As 2p3/2 core levels in Fig. 2.35 (a) (b), and (c). Deconvolution of XPS lines involves Shirley baseline removal and Lorentzian-Gaussian doublets as fitting components [38-40]. From Fig. 2.35 (a), there is no significant variation in Ga 2p3/2 spectra. Nevertheless, the In 3d5/2 and As 2p3/2 spectra show the presence of In- and As-oxide in both samples, are shown in Fig. 2.35 (b) (c). Upon different annealing temperatures, it is possible that there are some oxygen bonds transfer processes from one oxidation to another. In other words, the As5+ oxidation state is seen to undergo an oxygen transfer to the As3+ with the small As2+ state related component after specific annealing conditions. The As2O5 portion of the native oxide decreases with the As2O3 increases; this suggests that the arsenic oxides undergo a bond conversion from one form of arsenic oxide to another. However, the In3+ and the InAsO4 oxides are seen to increase, whereas there is an unobvious signal in the gallium oxide states suggesting this signal takes place as a result of oxygen bond transfers from gallium to indium. The Table 2.5 shows the ratio of the fitted area such as In2O3 to InAsO4 from In 3d5/2 spectra, As2+ to As2O5 and As2O3
to As2O5 from As 2p3/2 spectra. With evidence in Fig. 2.37 (a), these area ratio were compared to the electrical characteristics, we can illustrate that the better interface property is caused by the higher ratio values of the superior oxide. This phenomenon may be caused by the passivation of the trivalent oxides or lower valence As on the interface. Therefore, we can demonstrate that the PDA 300 °C is the best condition in our samples.
2.5.2 Comparison of Various Al
2O
3cycles with same PDA Conditions
Fig. 2.31 shows the comparison of Dit profiles of ALD-TMA/ZrO2/In0.53Ga0.47As
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MOSCAPs with various Al2O3 inter-layers at the same PDA conditions, which are measured at 300K. These diagrams show that incorporating more Al2O3 inter-layers with ALD-TMA/ZrO2, the oxide and interface quality will be more improvable, especially at PDA 300 °C. It indicates that the interface could be passivated within Al2O3. Therefore, we further compare the electrical properties of ALD-TMA/ZrO2 case which means Al2O3 0cycle inter-layer [see Fig. 2.32] and the ALD-TMA/Al2O3 case which means all of the gate dielectric is composed of Al2O3 [see Fig. 2.33] with Al2O3 1,5, and 10 cycles inter-layer under PDA 300 °C/120s, w/FGA. From Fig. 2.34 and Table 2.4, we notice that thicker Al2O3 might passivate the In0.53Ga0.47As surface, the oxide and interface quality might be improved [41]. In addition, we will analyze the interfacial chemistry characteristics of ALD-TMA/ZrO2 with various Al2O3 inter-layers under PDA 300 °C to prove the aforementioned results.
The Ga 2p3/2, In 3d5/2, and As 2p3/2 core levels of XPS spectra are reported in Fig. 2.36 (a) (b), and (c) for ALD-TMA/Al2O3 0, 1, 5, 10cycle/ZrO2 10cycle on p-type In0.53Ga0.47As, respectively, except the top one. It is found that the signal of Ga 2p3/2 spectra hardly depends on the various Al2O3 inter-layer. However, we can notice the variation at the In 3d5/2 and As 2p3/2 spectra. When increasing Al2O3 inter-layers, the As2O5 decreases with the As2O3 and As2+ increase. It indicates that the more Al2O3 layer tend to displace the As5+ oxidation state to the As3+ and As2+. From Table 2.6, we can see that the area ratio of In2O3 to InAsO4, As2+ to As2O5, and As2O3 to As2O5 increase when inserting Al2O3 10cycles between the ZrO2 and the In0.53Ga0.47As interface. To further demonstrate the connection between electrical and chemical characteristics of the interface, we combine the density of interface state with the area ratio in the profile. From Fig. 2.37 (b), it shows that the interface can be effectively passivated by trivalent oxides such as Al2O3 and As2O3 without generating a large amount of dangling bonds [42]. Consequently, we show that the Al2O3 10cycles inter-layer condition is better than other conditions.
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