Al 2 O 3 Inter-layers
3.3 The Relationship between the Model and the measured Multi-frequency C-V and
Accumulation region
To further discuss the effect of bulk-oxide traps in gate dielectrics at accumulation region and extract Nbt quantitatively, we have fitted the experimental capacitance and conductance data for the ALD-TMA/ZrO2/In0.53Ga0.47As MOSCAPs under different PDA conditions with several Al2O3 layers at the gate voltage range from -2 to -1volts which are correlated with the distributed model. There are several parameters of the model, such as Nbt, 𝜏0, Cs, 𝜖𝑜𝑥, and k, need to be given an initial supposed values and be matched between the measured data and the oxide traps model from 1 kHz to 100 kHz. Part of the parameters like gate oxide thickness tox is determined by TEM image, the semiconductor capacitance Cs is selected which gives Ctot slightly below the capacitance value of 1 MHz at Vg= -2 V. Moreover, due to two kinds of gate dielectric layers in our sample, we have to assign different parameters, such as 𝜖𝑜𝑥, k, and tox for Al2O3 and ZrO2, respectively. Pay more attention to the attenuation coefficient k, we find that Al2O3 should be larger than ZrO2 because of the difference between the valence band of gate oxide and the energy E. And 𝜏0 is given to probably achieve the frequency condition 𝜔𝜏0 ~1, which means the influence of bulk-traps has not existed on the capacitance and conductance characteristics. Finally, we can discover that the consequences of the model and the measured data are matched because of being sensitive to the initial supposed values.
Fig 3.3, 3.5, 3.7, and 3.9 show the transferred C-V map of total experimental C-F data for the ALD-TMA/ZrO2/In0.53Ga0.47As MOSCAPs under different PDA conditions with various Al2O3 inter-layers at frequency from 1 kHz to 100 kHz, and Fig 3.4, 3.6, 3.8, and 3.10 display
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the converted G-V map of total experimental G-F data. With these figures of C-V and G-V maps, the values of Nbt are extracted as shown in Table. 3.1 at Cs=0.75 (μF/cm2), which indicate the surface band bending of semiconductor are in the same conditions. And this substrate capacitance corresponding to the energy E of band gap is above valence band about 0.15 eV.
From Fig 3.11 and 3.12, both the slopes of C-F and G-F of different PDA conditions are sensitive to bulk-oxide trap density Nbt which demonstrate the frequency dispersion at accumulation region, and in contrast with Table. 3.1, the temperature of 300 °C has lower Nbt in each Al2O3 inter-layer conditions except for Al2O3 with 1cycle. This might be a slightly error of the extraction. Besides, we compare these results of Nbt with the frequency dispersion ΔC in Table. 2.2, and have good consistency with the consequence. In addition, the ΔC and Nbt of 400 °C and 500 °C have some mismatch; these might be the capacitance values at accumulation region of PDA 500 °C is much higher than 400 °C and result the ΔC at PDA 500 °C in lower values.
Furthermore, from each post-deposition annealing conditions, we demonstrate that the bulk-oxide trap density Nbt of thicker Al2O3 layers have lower values and low frequency dispersion, as shown in Fig 3.13, 3.14, and Table 3.1. This might be the quality of gate dielectric ZrO2 is not good enough, and the Al2O3 inter-layer can be used to improve the oxide and interface characteristics.
3.4 Summary
The distributed bulk-oxide traps model has been developed for the tunneling mechanism which indicate charging and discharging of the border traps between the In0.53Ga0.47As surface and trap states. Besides, due to the broad frequency spectrum of traps response, the model
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differs from the usual interface state circuit. However, the model is demonstrated with the measured data in C-V and G-V curves. And the extraction of density Nbt of bulk-oxide traps has similar property which compared to the aforementioned chapter. By this distributed model, we could further demonstrate the consistency with the border traps from the quantitative analyses.
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Reference (Chapter 3)
[1] D.M. Fleetwood, ““Border Traps” in MOS devices,” IEEE Trans. Nucl. Sci., vol. 39, no.
2, pp. 269-271, 1992.
[2] D.J. DiMaria, D.A. Buchanan, J.H. Stathis, and R.E. Stahlbush, “Interface states induced by the presence of trapped holes near the silicon-silicon dioxide interface,” J. Appl. Phys., vol. 77, no. 5, pp. 2032-2040, 1995.
[3] D.M. Fleetwood, W.L. Warren, M.R. Shaneyfelt, R.A.B. Devine, and J.H. Scofield,
“Enhanced MOS 1/f noise due to near-interfacial oxygen deficiency,” J. Non-Cryst.
Solids, vol. 187, pp. 199-205, 1995.
[4] E. Simoen, H.-C. Lin, A. Alian, G. Brammertz, C. Merckling, J. Mitard, and C. Claeys,
“Border Traps in Ge/III-V Channel Devices: Analysis and Reliability Aspects,”
Deviceand Materials Reliability, IEEE Trans., vol. PP, p.99, 2013.
[5] F. P. Heiman, and G. Warfield, “The effects of oxide traps on the MOS capacitance,”
IEEE Trans. Electron Devices, vol. ED-12, p.167, 1965.
[6] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
[7] H. Prier, “Contribution of surface states to MOS impedance,” Appl. Phys. Lett., vol. 10, p.
361, 1967.
[8] Y. Yuan, B. Yu, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J. W. Rodwell, and Y. Taur,
“A distributed Bulk-Oxide Trap Model for Al2O3 InGaAs MOS Devices,” IEEE Trans.
Electron Devices, vol. 59, p. 2100, 2012.
[9] Y. Yuan, L. Wang, B. Yu, B. Shih, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J. W.
Rodwell, and Y. Taur, “A Distributed Model for Border Traps in Al2O3 – InGaAs MOS Devices,” IEEE Electron Device Lett., vol. 32, p. 485, 2011.
[10] D. S. L. Mui, J. Reed, D. Biswas, and H. Morkoc, “A new circuit model for tunneling
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related trapping at insulator-semiconductor interfaces in accumulation,” J. Appl. Phys., vol. 72, p. 553, 1992.
[11] Chen Zhang, Student Member, IEEE, Min Xu, Peide D. Ye, Fellow, IEEE, and Xiuling Li, Senior Member, IEEE ,” A Distributive-Transconductance Model for Border Traps in III–V/High-k MOS Capacitors,” IEEE Trans. Electron Devices, vol. 34, no. 6, 2013.
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Y(x)
Gate Substrate
x=0 C
sx = t
oxΔC
bt(x) ΔG
bt(x)
ΔY
bt(x) C
itR
it
/Δx
Ev Ef Ec Gate dielectric Semiconductor
Ev,ox E－
x 0
Fig. 3.1 Band diagram of tunneling mechanism between bulk-oxide traps in the gate dielectric and valence band of the semiconductor.
Fig. 3.2 An equivalent circuit for border traps distributed over the depth x of the gate dielectrics.
The semiconductor capacitance is represented by Cs, the interface trap capacitance is Cit, and the resistance Rit is a lossy process of Dit.
80 compared from the distributed border trap model.
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0
81 compared from the distributed border trap model.
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0
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(a) (b)
(c) (d)
Fig. 3.5 The transferred C-V map of total experimental C-F data for p-type Pt/Ti/TMA+Al2O3 1 cycle+ZrO2/In0.53Ga0.47As at the frequency 1 kHz ~ 100 kHz from Vg= -1 to -2 volts at
83
(a) (b)
(c) (d)
Fig. 3.6 The transferred G-V map of total experimental G-F data for p-type Pt/Ti/TMA+Al2O3
1 cycle+ZrO2/In0.53Ga0.47As at the frequency 1 kHz ~ 100 kHz from Vg= -1 to -2 volts
84
(a) (b)
(c) (d)
Fig. 3.7 The transferred C-V map of total experimental C-F data for p-type Pt/Ti/TMA+Al2O3 5 cycle+ZrO2/In0.53Ga0.47As at the frequency 1 kHz ~ 100 kHz from Vg= -1 to -2 volts at
85
(a) (b)
(c) (d)
Fig. 3.8 The transferred G-V map of total experimental G-F data for p-type Pt/Ti/TMA+Al2O3
5 cycle+ZrO2/In0.53Ga0.47As at the frequency 1 kHz ~ 100 kHz from Vg= -1 to -2 volts
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(a) (b)
(c) (d)
Fig. 3.9 The transferred C-V map of total experimental C-F data for p-type Pt/Ti/TMA+Al2O3
10 cycle+ZrO2/In0.53Ga0.47As at the frequency 1 kHz ~ 100 kHz from Vg= -1 to -2
87
(a) (b)
(c) (d)
Fig. 3.10 The transferred G-V map of total experimental G-F data for p-type Pt/Ti/TMA+Al2O3
10 cycle+ZrO2/In0.53Ga0.47As at the frequency 1 kHz ~ 100 kHz from Vg= -1 to -2
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(a) (b)
(c) (d)
Fig. 3.11 The frequency dispersion calculated by using the bulk-oxide traps model (line) and experimental data taken at Cs=0.75μF/cm2(circle) of ALD-TMA/ZrO2/In0.53Ga0.47As MOSCAPs under different PDA conditions with various Al2O3 inter-layer(a) 0 cycle (b) 1 cycle (c) 5 cycle(d) 10 cycle. Moreover, the color of black, red, green, and blue indicate as deposited, PDA 300 °C, 400 °C, 500 °C, respectively.
103 104 105
Al2O3 5cycles/ZrO2 as deposited,w/FGA PDA 300C,w/FGA
Al2O3 1cycles/ZrO2 as deposited,w/FGA PDA 300C,w/FGA PDA 400C,w/FGA PDA 500C,w/FGA
Model
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(a) (b)
(c) (d)
Fig. 3.12 Comparison of the fitted G-F map at Cs=0.75μF/cm2 of
ALD-TMA/ZrO2/In0.53Ga0.47As MOSCAPs under different PDA conditions with various Al2O3 inter-layer (a) 0 cycle (b) 1 cycle (c) 5 cycle (d) 10 cycle.
Moreover, the color of black, red, green, and blue indicate as deposited, PDA 300 °C, 400 °C, 500 °C, respectively.
103 104 105
90
(a) (b)
(c) (d)
Fig. 3.13 The frequency dispersion calculated by using the bulk-oxide traps model (line) and experimental data taken at Cs=0.75μF/cm2(circle) of ALD-TMA/ZrO2/In0.53Ga0.47As MOSCAPs with various Al2O3 inter-layer under different PDA conditions (a) as
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(a) (b)
(c) (d)
Fig. 3.14 Comparison of the fitted G-F map at Cs=0.75μF/cm2 of
ALD-TMA/ZrO2/In0.53Ga0.47As MOSCAPs with various Al2O3 inter-layer under different PDA conditions (a) as deposited (b) 300 °C (c) 400 °C (d) 500
°C.
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Table 3.1 Overview of the extraction in border traps density Nbt (1019eV-1cm-3) at E-Ev=0.15 eV ( Cs=0.75μF/cm2 ) for various Al2O3 cycles after FGA under various PDA conditions.
N
bt(10
19eV
-1cm
-3) As-deposited PDA 300°C /120s
PDA 400°C /120s
PDA 500°C /120s
Al
2O
30cyc 8.93 17.34 21.72
Al
2O
31cyc 8.34 8.39 14.29 15.62
Al
2O
35cyc 7.16 7.02 10.44 13.65
Al
2O
310cyc 7.00 6.74 8.75 12.37
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Chapter 4
Conclusion
In this thesis, we have investigated the electrical characteristics and interfacial chemistry of In0.53Ga0.47As MOSCAPs with ZrO2 gate dielectric. At first, we utilize the precursors of ALD, such as TMA or TEMAZ, to passivate the surface before depositing dielectrics. Then, the thermal treatments of various PDA conditions with FGA were employed to observe the effect of interface and oxide properties. From the frequency dispersion and hysteresis, we can find the TMA pretreatment is effective to improve the interface and oxide quality. Moreover, comparing to post-deposition temperatures, PDA 300 °C is the best one than the others. The XPS spectra also shows that the higher area ratio of In2O3 to InAsO4, As2+ to As2O5 and As2O3
to As2O5 indicate the passivation of the trivalent oxides or lower valence As on the interface and result in the better electrical characteristics.
However, the ZrO2/In0.53Ga0.47As interfaces still have inferior properties than Al2O3 on In0.53Ga0.47As, so we incorporate several Al2O3 inter-layers to discuss its interface property.
From the electrical characteristics of the capacitors, we note that the interface and gate dielectric qualities were much improved by inserting thicker Al2O3 inter-layer. The Dit at midgap also demonstrates the interface could be passivated within thick Al2O3. With the evidence of XPS spectra, we can clarify that the better interface property is caused by the higher ratio values of the As2O3 and In2O3 passivation. It might be the thicker Al2O3 layers tend to displace the As5+ oxidation state to the As3+ and As2+. Subsequently, we compare the different PDA conditions at each Al2O3 inter-layer. It shows that PDA 300 °C with FGA demonstrates the best property than others under certain conditions like frequency dispersion, hysteresis, and the density of interface states. Furthermore, the XPS spectra also displays that
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the area ratio becomes larger as the PDA temperature decreasing. Comparison of electrical characteristics, it indicates if interface exist more As2O3 and In2O3 components, the properties might be improved.
In addition, the influence of frequency dispersion at high negative gate voltage is caused by oxide traps. To further realize the phenomenon of accumulation region, a distributed border traps model between In0.53Ga0.47As and trap states in the gate dielectrics is developed.
Then, we fitted the experimental data with the model and extracted density of trap states Nbt
quantitatively. Finally, comparing with the aforementioned chapter, we can find it has good consistency with our experimental data.
In the future, we suggest that the double layer of gate dielectrics in our experiment can be replaced by depositing ZrO2 with O2-plasma treatment during the process of atomic-layer deposition, which gate oxide quality may be further improved. Moreover, lower temperature of ALD down to 200 °C or less can be a promising method to suppress the interface states.
Finally, we expect the improvable gate stacks on III-V substrates can be fabricated by self-aligned MOSFETs.
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