Analog Baseband Design

The analog baseband functions as channel selection and programmable amplification for both In-phase and Quadrature signal processing. Programmable gain function provides the flexibility to optimize noise, linearity and power consumption. To optimize noise, power consumption and silicon area, it is necessary to make trade-offs in the Op-amp together with the input/feedback resistor pair. In this design, the analog baseband provides total gain control from 0 to 63.5dB in 0.5dB steps. It includes several circuit blocks as shown in Fig. 5.8: a variable-gain low-pass channel filter (VGCF) with cutoff frequency calibration, a first-order all-pass filter, a programmable-gain amplifier, four independent dc-offset cancellation (DCOC) loops with on-chip capacitors, and a unit-gain buffer.

Fig. 5.8 Architecture of Analog Baseband.

The channel filter is a seventh-order Chebyshev type-I implemented using the leap-frog topology. Embedded into the filter blocks, gain control provides a range from

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0 to 48dB with a tunable cutoff frequency from 2 to 5 MHz depending on the channel bandwidth in use. In the VGCF, the first two Op-amps consume high current for low noise and large signal-handling capability. Also small input/feedback resistor pairs are applied to reach better noise performance at the expense of large capacitor area. The remaining five Op-amps consume less current since the noise contributions are less critical. In addition, the input/feedback resistor pairs have high resistances to reduce the capacitor area. Following the VGCF, the first-order all-pass filter is added to improve the group delay. Then two PGA stages provide an extra gain of 15.5dB.

5.4.1 Auto-Bandwidth Calibration

On-chip RC auto-calibration activated at power up accurately sets up the channel bandwidth from 2.5 to 4 MHz against PVT variations. The architecture and the timing diagram are depicted in Fig. 5.9. A duplicate RC integrator compares the RC time constant with a reference clock generated from the crystal output through a programmable divider. The detailed procedure is described as follows.

Two successive states are utilized to complete the auto-calibration process in an iterative process. In the first phase, the clock CLKB is set to high. The integrator is configured as a resistive feedback amplifier with gain attenuation. As a result, both integrator outputs, V_op and V_on, are reset to the Op-amp’s common-mode voltage. In the second phase, CLKB is low. The integrator is configured as a lossless integrator, which forces its positive output V_op to charge toward VDD and its negative output V_on to discharge to ground. Once V_on voltage becomes smaller than the reference voltage, the comparator will deliver a control signal to stop counting. The 6-bit counter’s code is subsequently subtracted from the Bandwidth Code, a default value of RC time constant corresponding to the channel bandwidth. After that, the subtracted output code is sent to update the Capacitor Code used to control the capacitor banks. The calibration will continue until the capacitor code remains constant for several consecutive iterations. As soon as the calibration is finished, another control signal will be sent to power off the calibration circuits and stop the input clock. Finally, a 5-bit control word is provided to adjust the capacitors in the TIA and filter stages within 3% bandwidth accuracy.

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5.4.2 DC Offset Cancellation

DC-offset cancellation is indispensable in a direct conversion receiver because DC offset may saturate the baseband output and degrade the dynamic range. Featuring a high-pass response in the signal chain, the DCOC has a cutoff frequency less than 1 kHz to ensure sub-carriers around DC are not affected too much. However, if a single loop cancellation is utilized, such a low cutoff frequency will demand for large loop capacitors, inevitably implemented in off-chip components at the expense of four extra package pins [18], [49]. Since the high-pass corner frequency is proportional to the signal processing gain, but inverse to the loop capacitance, multi-loop cancellation can effectively reduce the required loop capacitances. For example, as the signal chain is uniformly divided into M segments in cascade and each segment has an independent servo-loop for DCOC, the processing gain and the used capacitance in each loop can be expressed by A^(1/M) and Cml/M, respectively, where A is the total gain of the signal chain and Cml is the total capacitance required in M loops. To maintain the same high-pass corner frequency in the single-loop and multi-loop implementations, the ratio of the total required loop capacitance in single-loop calibration to that in multi-loop can be approximated as

M where C_sl is the total capacitance required in single-loop cancellation. In this design, four independent servo-loops are utilized to reject DC offset, in total using 16pF capacitance which is much easier to integrate on chip since 60 times less total capacitance is required compared with a single loop implementation.

The final high-pass cutoff frequency is set constant at 1 kHz for all gain settings by keeping the gain of feedback loop inversely proportional to that of the signal path.

Furthermore, the remaining DC offset resulting from the last stage of the servo loop chain is carefully minimized by enhancing transistor symmetry and by using larger dimensions. The measured DC offset is less than 6mV with an average of 4mV characterized over 50 samples at the maximum gain setting. The analog baseband totally dissipates 22mA current, where 8.3mA is dissipated by the first two stages. The simulated input-referred noise level is about 6nV/ Hz .

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Fig. 5.10 Schematic of VCOs.