Chapter 6 65nm Tuner Implementation and Verification
6.8 Appendix I – 65nm Tuner (II)
Since MBRAI 2.0 releases a stringent sensitivity specification, NF less than 4dB in RF tuners is required to meet the specification. Further to improve the overall NF, an auxiliary LNA with a lower NF is added in parallel with an established LNA. The auxiliary LNA has an imbalanced size ratio between the CG and CS branches as described in Section 4.8. Fig. 6.33 shows the simplified schematic of the UHF front-end. As can be seen, the auxiliary path contains an asymmetric CG-CS balun LNA along with a duplicated input transconductor of the mixer. The input port of each LNA is connected to one common ESD pad and the differential outputs of two transconductors are summed together in a current mode. The summation in a current mode can alleviate the impacts of the layout routing and the RC parasitic on circuit performance. The tuner chip is fabricated in 65nm 1P6M LP CMOS process. It occupies a total silicon area of 7.8 mm2 including all ESD pads. Fig. 6.34 shows the die micrograph of the chip. The measurement result shows that this tuner achieves a NF of 3－3.5dB across 474－858MHz channels. It means that an improvement of 0.3dB, i.e., -97.6dBm sensitivity, can be achieved due to this auxiliary LNA. In addition, the performance of this tuner is similar to that of the single-ended mode in Table 6.3 and Table 6.4.
Chapter 6 65nm Tuner Implementation and Verification
Chapter 6 65nm Tuner Implementation and Verification
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Front-end
Analog Baseband
PLL VCO
BGR I2C
Aux. LNA UHF LNA
Fig. 6.34 The die micrograph of the high sensitivity tuner chip.
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155
Chapter 7
Conclusion and Future Works
7.1 Conclusion
This dissertation concentrates on the design and implementation of CMOS RF tuners for mobile TV applications. In this dissertation, considerations on system-level and circuit-level design have been presented, mainly focused on the DVB-T/H standard, MBRAI 2.0.
The design aspects of DVB-T/H system have been described in chapter 2 and chapter 3. The design procedure starting from standard specifications, receiver specifications to building block requirements is presented. What we have illustrated is expected to bridge the gap between the circuit design and radio standards in realization of wireless communication system.
A CMR current buffer is proposed and analyzed in chapter 4. By incorporating an extra capacitor pair into the CG current buffer, the CMRR characteristic at RF frequencies can be enhanced by 10dB. In cascode of the CMR buffer, the CG-CS amplifier has a significantly reduced NF and improved linearity. With symmetric branch sizes, the LNA can be configured as a differential or single-ended receiving mode, both featuring a NF of 2.3dB. With asymmetric branch sizes, the LNA is approved to have a NF as low as 1.7dB.
To develop low-voltage, low-power, and high-integration tuners, direct- conversion architecture is adopted and a novel frequency plan is proposed. In use of divide-by-2/4/6 dividers, the frequency plan effectively reduces the required VCO
Chapter 7 Conclusion and Future Works
156
tuning range to 40%. Divide-by-N circuits with even number of N ensures high quadrature accuracy. Furthermore, operating at higher frequencies enables the use of on-chip inductors with smaller area and higher Q-factors.
Based on the proposed architecture and frequency plan, three fully integrated CMOS tuners compliant with DVB-T/H system are presented. Techniques in current-mode operation are widely used in the design, such as the high SNIR gain-switching method and the RSSI detection. The first tuner is implemented in 0.13μm CMOS technology. With the proposed balun LNA, the tuner achieves a sensitivity level of -96.6dBm and dissipates 114mW from a 1.2 V supply. The second tuner is implemented in 65nm CMOS technology. Incorporating the reconfigurable LNA, the tuner highly adapts to various market requirements, either RF stand-alone or SoC solutions. This tuner achieves a sensitivity level of -97.3dBm and dissipates 88mA from a 1.2 V supply. The third tuner is also implemented in 65nm CMOS technology. It is implemented to demonstrate even better sensitivity performance with an asymmetric balun LNA. The tuner achieves a sensitivity level of -97.6dBm and dissipates 88mW from a 1.2 V supply.
7.2 Future Works
In this dissertation, a wideband LNA is adopted and demonstrated in a tuner compliant with the DVB-T/H standard. Compared to narrow-band LNAs used in previous work [16], [17], [18], [31], [64], wideband LNAs achieve better performance and reliability. However, wideband receptions possibly suffer from the problem of GSM interference much more. To provide a more competitive solution, a GSM-rejecting notch function could be incorporated into the proposed LNA topology.
As can be found in the chip micrographs, the analog baseband occupies a significant part of the total die area. To minimize the area and power consumption of the RF tuner, more system budgeting can be left for the digital part in 65nm CMOS.
Significant reduction in area/power can be achieved by removing most of the analog baseband function, while replaced with high performance ADC and digital filters [77]
[78], [79], [80]. To meet the market requirements, more integration of system blocks
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and functionality is a trend. To achieve multi-standard operation and to cover most popular mobile TV bands, the VHF III band (174–240 MHz) should be added. This new chain can be realized by duplicating the UHF-band RF front-end, but still need to extend the channel bandwidths from 0.3 to 8MHz in the baseband filters [31], [64].
With the transition from analog to digital TV, much more TV spectrum is released. More and more wireless standards target at TV-band operations, such as 802.11af, 4G LTE/WiMAX [81], 802.22 cognitive radio [82], etc. The proposed techniques could be generalized to the implementation of these new standards.
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Bibliography
159
Bibliography
[1] G. Faria, J. Henriksson, E. Stare, and P. Talmola, ―DVB-H: Digital broadcast services to handheld devices,‖ Proc. IEEE, vol. 94, no. 1, pp. 198–209, Jan. 2006.
[2] S. Cho, G. Lee, B. Bae, K. Yang, C. Ahn, S. Lee, and C. Ahn, ―System and services of Terrestrial Digital Multimedia Broadcasting (T-DMB),‖ IEEE Trans.
Broadcast., vol. 53, no. 1, pp. 171–178, Mar. 2007.
[3] M. Takada and M. Saito, ―Transmission system for ISDB-T,‖ Proc. IEEE, vol. 94, no. 1, pp. 251–256, Jan. 2006.
[4] M. R. Chari, F. Ling, A. Mantravadi, R. Krishnamoorthi, R. Vijayan, G. K. Walker, and R. Chandhok, ―FLO physical layer: An overview,‖ IEEE Trans. Broadcast., vol. 53, no. 3, pp. 145–160, Mar. 2007.
[5] R. A. Burger, G. Iacovoni, C. Reader, X. Fu, X. Yang, and H. Wang, ―A Survey of Digital TV Standards China,‖ in IEEE Proc. of 2nd Int. Conf. on Communications and Networking, Aug. 2007, pp. 687–696.
[6] Mobile and Portable DVB-T/H Radio Access—Part 1: Interface Specification, International Standard IEC 62002-1, IEC, May 2008.
[7] Mobile and Portable DVB-T/H Radio Access—Part 2: Interface Conformance Testing, International Standard IEC 62002-2, IEC, May 2008.
[8] Behzad Razavi, RF Microelectronics, Prentice Hall PTR, 1998.
[9] A. Maxim, R. Johns, and S. Dupue, ―0.13μm CMOS hybrid TV tuner using a calibrated image and harmonic rejection mixer,‖ in Symp. VLSI Circ. Dig. Tech.
Papers, June 2007, pp. 206–207.
[10] L. Connell, N. Hollenbeck, M. Bushman, D. McCarthy, S. Bergstedt, R.Cieslak, and J. Caldwell, ―A CMOS broadband tuner IC,‖ in IEEE ISSCC Dig. Tech.
Papers, Feb. 2002, pp. 400–401.
Bibliography
160
[11] M. Dawkins, A. Burdett, and N. Cowley, ―A single-chip tuner for DVB-T,‖ IEEE J.
Solid-State Circuits, vol. 38, no. 8, pp. 1307–1317, Aug. 2003.
[12] C. H. Heng, M. Gupta, S. H. Lee, D. Kang, and B. S. Song, ―A CMOS TV tuner/demodulator IC with digital image rejection,‖ in IEEE ISSCC Dig. Tech.
Papers, Feb. 2005, pp. 432–433.
[13] M. Gupta, S. Lerstaveesin, D. Kang, and B. Song, ―A 48-to-860 MHz. CMOS direct conversion TV tuner,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp.
206–207.
[14] J. van Sinderen, F. Seneschal, E. Stikvoort, F. Mounaim, M. Notten, H.
Brekelmans, O. Crand, F. Singh, M. Bernard, V. Fillatre, and A. Tombeur, ―A 48-860MHz digital cable tuner IC with integrated RF and IF selectivity,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 444–405.
[15] H.-K. Cha, S.-S. Song, H.-T. Kim, and K. Lee, ―A CMOS harmonic rejection mixer with mismatch calibration circuitry for digital TV tuner applications,‖ IEEE Microwave and Wireless Component Letters, vol. 18, no 9, pp. 617-619, Sept.
2008.
[16] I. Vassiliou, K. Vavelidis, S. Bouras, S. Kavadias, Y. Kokolakis, G. Kamoulakos, A.
Kyranas, C. Kapnistis, and N. Haralabidis, ―A 0.18µm CMOS dual-band direct-conversion DVB-H receiver,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 606–607.
[17] Y. J. Kim, J. W. Kim, V. N. Parkhomenko, D. Baek, J. H. Lee, E. Y. Sung, L. Nam, and B. H. Park, ―A multi-band multi-mode CMOS conversion DVB-H tuner,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 608–609.
[18] M. Womac, A. Deiss, T. Davis, R. Spencer, B. Abesingha, and P. Hisayasu,
―Dual-band single-ended-input direct-conversion DVB-H receiver,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 610–611.
[19] P.-I. Mak and R. P. Martins, ―Design of an ESD-protected ultra-wideband LNA in nanoscale CMOS for full-band mobile TV tuners,‖ IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no 11, pp. 2327-2334, Nov. 2005.
[20] P.-I. Mak and R. P. Martins, ―A 2xVDD–enabled TV-tuner RF front-end supporting TV-GSM interoperation in 90nm CMOS,‖ in IEEE Symp. VLSI Circ.
Dig. Tech. Papers, June 2009, pp. 278-279.
[21] A. G. Armada, ―Understanding the effects of phase noise in orthogonal frequency division multiplexing (OFDM),‖ IEEE Trans. Broadcast., vol. 47, no. 2, pp.
153–159, June 2001.
[22] B. Razavi,“A study of phase noise in CMOS oscillators,‖ IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331–343, Mar. 1996.
Bibliography
161
[23] J. Jussila, ―Analog baseband circuits for WCDMA direct-conversion receiver‖, PhD thesis, Helsinki University of Technology, Electronic Circuit Design Laboratory, June 2003.
[24] B. Razavi, ―Design considerations for direct-conversion receivers,‖ IEEE Trans.
Circuits Syst. II, vol. 44, pp. 428–435, June 1997.
[25] A. Tarighat, R. Bagheri, and A. H. Sayed, ―Compensation schemes and performance analysis of IQ imbalances in OFDM receivers‖, IEEE Trans. Signal Process., vol. 53, no. 8, pp. 3257–3268, Aug. 2005.
[26] Fa-Long Luo, Mobile Multimedia Broadcasting Standards: Technology and Practice, Ch. 5, Springer, 2009.
[27] H. T. Friis, ―Noise Figure of Radio Receivers," Proc. IRE, vol. 32, pp. 419-422, July 1944.
[28] M. Hammes, C. Kranz, D. Seippel, J. Kissing, and Leyk, ―Evolution on SoC integration : GSM baseband-radio in 0.13 μm CMOS extended by fully integrated power management unit,‖ IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 236–245, Jan. 2008.
[29] S. S. Mehta, D. Weber, M. Terrovitis, K. Onodera, M. P. Mack, B. J. Kaczynski, H.
Samavati, S. H.-M. Jen, W. W. Si, M.Lee, K. Singh, S. Mendis, P. J. Husted, N.
Zhang, B. McFarland, D. K. Su, T. H. Meng, and B. A. Wooley, ―An 802.11g WLAN SoC,‖ IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2483–2491, Dec.
2005.
[30] M. Xu, D. Su, D. K. Shaeffer, T. H. Lee, and B. Wooley, ―Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver,‖ IEEE J.
Solid-State Circuits, vol. 36, no. 3, pp. 473–485, Mar. 2001.
[31] I. Vassiliou, K. Vavelidis, N. Haralabidis, A. Kyranas, Y. Kokolakis, S. Bouras, G.
Kamoulakos, C. Kapnistis, S. Kavadias, N. Kanakaris, E. Metaxakis, C. Kokozidis, and H. Peyravi, ―A 65nm CMOS multistandard, multiband TV tuner for mobile and multimedia applications,‖ IEEE J. Solid-State Circuits, vol. 43, no. 7, pp.
1522–1533, July 2008.
[32] D. K. Shaeffer and T. H. Lee, ―A 1.5 V, 1.5 GHz CMOS low noise amplifier,‖
IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997.
[33] D. J. Allstot, X. Li, and S. Shekhar, ―Design considerations for CMOS low-noise amplifiers,‖ in Proc. IEEE Radio Frequency Integrated Circuits Symp. (RFIC), Jun. 2004, pp. 97–100.
Bibliography
162
[34] W. Zhuo, S. H. K. Embabi, J. Pineda de Gyvez, and E. Sánchez-Sinencio, ―Using capacitive cross-coupling technique in RF low-noise amplifiers and down-conversion mixer design,‖ in Proc. Eur. Solid-State Circ. Conf., Sep. 2000, pp. 116–119.
[35] W. Zhuo, X. Li, S. Shekhar, S. H. K. Embabi, J. Pineda de Gyvez, D. J. Allstot, and E. Sánchez-Sinencio, ―A capacitor cross-coupled common-gate low noise amplifier,‖ IEEE Trans. Circuits Syst. II: Expr. Briefs, vol. 52, no. 12, pp. 875–879, Dec. 2005.
[36] X. Li, S. Shekhar, and D. J. Allstot, ―Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18- m CMOS,‖ IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
[37] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, ―Wide-band CMOS low-noise amplifier exploiting thermal noise cancelling,‖ IEEE J. Solid-State Circuits, vol.
39, no. 2, pp. 275–282, Feb. 2004.
[38] S. Chehrazi, A. Mirzaei, R. Bagheri, and A. A. Abidi, ―A 6.5 GHz wideband CMOS low-noise amplifier for multi-band use,‖ in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sept. 2005, pp. 801–804.
[39] S.C. Blaakmeer, E.A.M. Klumperink, B. Nauta, and D.M.W. Leenaerts,
―Wideband Balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling‖, IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1341–1350, June 2008.
[40] J. Jussila and P. Sivonen, ―A 1.2-V highly linear balanced noise-cancelling LNA in 0.13-μm CMOS,‖ IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 579–587, Mar.
2008.
[41] S. Wu and B. Razavi, ―A 900-MHz/1.8-GHz CMOS receiver for dual-band applications,‖ IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2178–2185, Dec.
1998.
[42] S. Chatterjee, Y. Tsividis, and P. Kinget, ―0.5-V analog circuit techniques and their application in OTA and filter design,‖ IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2373–2387, Dec. 2005.
[43] S. Woo, W. Kim, C.-H. Lee, K. Lim, and J. Laskar, ―A 3.6mW differential common-gate CMOS LNA with positive-negative feedback,‖ in IEEE ISSCC Dig.
Tech. Papers, Feb. 2009, pp. 218–219.
[44] D. Im, I. Nam, H.-T. Kim, and K. Lee, ―A wideband CMOS low noise amplifier employing noise and IM2 distortion cancellation for a Digital TV tuner,‖ IEEE J.
Solid-State Circuits, vol. 44, no. 3, pp. 686–698, Mar. 2009.
Bibliography
163
[45] M. Ranjan and L. Larson, ―Distortion analysis of ultra-wideband OFDM receiver front-ends,‖ IEEE Trans. Microw. Theory Tech., vol. 54, no. 12, pp. 4422–4431, Dec. 2006.
[46] W.-H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, ―A highly linear broadband CMOS LNA employing noise and distortion cancellation,‖ IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1164–1176, May 2008.
[47] X. Fan, H. Zhang, and E. Sanchez-Sinencio, “A noise reduction and linearity improvement technique for a differential cascode LNA,‖ IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 588–599, Mar. 2008.
[48] P. Antoine, P. Bauser, H. Beaulaton, M. Buchholz, D. Carey, T. Cassagnes, T. K.
Chan, S. Colomines, F. Hurley, D. T. Jobling, N. Kearney, A. C. Murphy, J. Rock, D. Salle, and T. Cao-Thong, ―A direct-conversion receiver for DVB-H,‖ IEEE J.
Solid State Circuits, vol. 40, no. 12, pp. 2536–2546, Dec. 2005.
[49] K. Iizuka, H. Kawamura, T. Fujiwara, K. Kagoshima, S. Kawama, H. Kijima, M.
Koutani, S. Toyoyama, and K. Sakuno, ―A 184mW fully integrated DVB-H tuner with a linearized variable gain LNA and quadrature mixers using cross-coupled transconductor,‖ IEEE J. Solid-State Circuits, vol.42, no. 4, pp862-871, Apr. 2007.
[50] J. Xiao, I. Mehr, and J. Silva-Martinez, ―A high dynamic range CMOS variable gain amplifier for mobile DTV tuner,‖ IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 292–301, Feb. 2007.
[51] G. Retz and P. Burton, ―A CMOS up-conversion receiver front end for cable and terrestrial DTV applications,‖ in IEEE ISSCC Dig. Tech. Papers, 2003, pp.
442–443.
[52] C. D. Hull, J. L. Tham, and R. R. Chu, ―A direct-conversion receiver for 900 MHz (ISM band) spread-spectrum digital cordless telephone", IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1955-1963, Dec. 1996.
[53] K. L. Fong, ―Dual-band high-linearity variable-gain low-noise amplifier for wireless applications‖, in IEEE ISSCC Dig. Tech. Papers, Feb. 1999, pp. 224–226.
[54] M. Koutani, H. Kawamura, S. Toyoyama, and K. Iizuka, ―A digitally controlled variable-gain Low-Noise Amplifier with strong immunity to interferers,‖ IEEE J.
Solid-State Circuits, vol. 42, no. 11, pp. 2395–2403, Nov. 2007.
[55] I. Mehr, S. Rose, S. Nesterenko, D. Paterson, R. Schreier, H. L'Bahy, S. Kidambi, M. Elliott, and S. Puckett, ―A dual-conversion tuner for multi-standard terrestrial and cable reception,‖ in Symp. VLSI Circ. Dig. Tech. Papers, June 2005, pp.
340–343.
Bibliography
164
[56] E. Sacchi , I. Bietti , S. Erba , L. Tee , P. Vilmercati, and R. Castello "A 15 mW, 70 kHz l/f corner direct conversion CMOS receiver", in Proc. IEEE Custom Integrated Circuit Conf., Sept. 2003, pp. 459 – 462.
[57] Y. Wu and V. Aparin, ―A monolithic low phase noise 1.7GHz CMOS VCO for zero-IF cellular CDMA receivers,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 396–397.
[58] A. Ravi, G. Banerjee, R. E. Bishop, B. A. Bloechel, L. R. Carley, and K.
Soumyanath, ―10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18µm digital CMOS process,‖ in Symp. VLSI Circ. Dig. Tech. Papers, June 2003, pp. 181–184.
[59] Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D. Jeong, and W. Kim, ―A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems,‖ IEEE J.
Solid-State Circuits, vol. 37, no. 5, pp. 536–542, May 2002.
[60] D. Su, ―Challenges in designing low-power CMOS wireless systems-on-a- chip,‖
in IEEE Custom Integr. Circ. Conf., Sept. 2006, pp. 113-120.
[61] L. Zhang, X. Yu, Y. Sun, W. Rhee, D. Wang, Z. Wang, and H. Chen, ―A hybrid spur compensation technique for finite-modulo fractional-N phase-locked loops,‖
IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2922–2934, Nov. 2009.
[62] D. Kosaka, M. Nagata, Y. Hiraoka, I. Imanishi, M. Maeda, Y. Murasaka, and A.
Iwata, ―Isolation strategy against substrate coupling in CMOS mixed-signal/RF circuits,‖ in IEEE Symp. VLSI Circ. Dig. Tech. Papers, June 2005, pp. 276-279.
[63] A. Ravi, G. Banerjee, R. E. Bishop, B. A. Bloechel, L. R. Carley, and K.
Soumyanath, ―A high performance DC-20 GHz SPDT switch in a low cost plastic QFN package,‖ in European Microw. Integr. Circ. Conf., Sept. 2009, pp. 320–323.
[64] J.-H. Chang, H. Kim, J.-H. Choi, H. Chung, J. Heo, S. Kang, J.-D. Bae, H. Oh, Y.
Kim, T.-W. Kwon, R. Kim, W. Choo, D. Rhee, and B. Park, ―A multistandard multiband mobile TV RF SoC in 65nm CMOS,‖ in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 462–463.
[65] H. Kim, S. Kang, J.-H. Chang, J.-H. Choi, H. Chung, J. Heo, J.-D. Bae, W. Choo, and B. Park, ―A multi-standard multi-band tuner for mobile TV SoC with GSM Interoperability,‖ in Proc. IEEE Radio Freq. Integr. Circ. Symp. (RFIC), June 2010, pp. 189-192.
[66] J.-C. Lee, M.-W. Hwang, S. Hong, M.-K. Ahn, S. Jeong, Y.-H. Oh, S. Lim, H. Cho, J.Moon, J.-R. Lee, and S. Han, C. Handa, T. Fujie, K. Hashimoto, and K. Tamukai,
“A 1.2V 57mW mobile ISDB-T SoC in 90nm CMOS,‖ in IEEE A-SSCC Dig.
Tech. Papers, Nov. 2009, pp. 345–348.
Bibliography
165
[67] K. Muhammad, C.-M. Hung, D. Leipold, T. Mayhugh, I. Elahi, I. Deng, C.
Fernando, M.-C. Lee, T. Murphy, J.L. Wallberg, R.B. Staszewski, S. Larson, T.
Jung, P. Cruise, V. Roussel, S.K. Vemulapalli, R. Staszewski, O.E. Eliezer, G.
Feygin, K. Kunz, and K. Maggio, ―A low-cost quad-band single-chip GSM/GPRS radio in 90nm digital CMOS,‖ in Proc. IEEE Radio Freq. Integr. Circ. Symp.
(RFIC), June 2009, pp. 197-200.
[68] D. Yang, Y. Ding, and S. Huang, ―A 65-nm high-frequency low-noise CMOS-Based RF SoC technology,‖ IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 328–335, Jan. 2010.
[69] M. Ismail, Radio Design in Nanometer Technologies, Springer, 2006.
[70] A. Kruth, ―The impact of technology scaling on integrated analogue CMOS RF front-ends for wireless applications,‖ PhD thesis, RWTH Aachen University, 2008.
[71] S. Donnay and G. Gielen, Eds., Substrate Noise Coupling in Mixed-Signal ASICs, Kluwer Academic Publishers, 2003.
[72] N. Checka, ―Substrate noise analysis and techniques for mitigation in mixed-signal RF systems,‖ PhD thesis, Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2005.
[73] Nordic whitepaper,“Design-in of RF circuits,‖ 2003. [Online]. Available:
http://www.nordicsemi.no/files/Product/white_paper/RF-design-in.pdf.
[74] Maxim datasheet, ―MAX2112 Evaluation Kit‖, Jul. 2010. [Online]. Available:
http://datasheets.maxim-ic.com/en/ds/MAX2112EVKIT.pdf.
[75] [Online]. Available:
http://www.tdk.com/s_details.php?class_code=TJA743&item_roots_key=TCM1 2B51-900-2P-T00&item_name=TCM12B51-900-2P-T00.
[76] [Online]. Available:
http://www.tdk.com/s_details.php?class_code=TJA743&item_roots_key=HHM1 525&item_name=HHM1525.
[77] K. Koli, J. Jussila, P. Sivonen, S. Kallioinen, and A. Parssinen, ―A 900MHz direct ΔΣ receiver in 65nm CMOS,‖ in ISSCC Dig. Tech. Papers, pp. 64-65, Feb., 2010.
[78] M. Jeong, B. Kim, Y. Cho, Y. Kim, S. Kim, H. Yoo, J. Lee, J.K. Lee, K.S. Jung, J.
Lee, J. Lee, H. Yang, G. Taylor, and B.-E. Kim, ―A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC,‖ in ISSCC Dig. Tech. Papers, pp. 460-461, Feb., 2010.
[79] F. Opteynde, ―A maximally-digital radio receiver front-end,‖ in ISSCC Dig. Tech.
Papers, pp. 450-451, Feb., 2010.
Bibliography
166
[80] K.-W. Cheng, K. Natarajan, and D.J. Allstot, ―A Current Reuse Quadrature GPS Receiver in 0.13μm CMOS,‖ IEEE J. Solid-State Circuits, vol. 45, no. 3, pp.
510–523, Mar. 2010.
[81] J.-W. Zhang, and C.-T. Wang, ―700MHz RF transceiver of base station for 802.16e,‖ in IEEE Int. Symp. Circ. and Syst., pp. 1950-1953, May, 2008.
[82] J. Park, T. Song, J. Hur, S.M. Lee, J. Choi, K. Kim, K. Lim, C.-H. Lee, H. Kim, and J. Laskar, ―A fully integrated UHF-band CMOS receiver with Multi-Resolution Spectrum Sensing (MRSS) functionality for IEEE 802.22 cognitive radio applications,‖ IEEE J. Solid-State Circuits, vol. 44, no. 1, pp.
258–268, Jan. 2009.
Vita
167
Vita
Ming-Ching Kuo received the B.S. degree in electrical engineering and the M.S. degree in electronics engineering from National Tsing-Hua University, Hsinchu, Taiwan in 1998 and 2000, respectively. He is currently working toward the Ph.D. degree in electronics engineering at National Chiao-Tung University, Hsinchu, Taiwan.
In 2001, he joined SoC Technology Center (STC), Industrial Technology Research Institute (ITRI), Hsinchu, Taiwan. Since 2010, he is with Information & Communications Research Laboratories (ICL), ITRI. His research interests are in the area of wireless communication integrated circuits.
Vita
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Publication List
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Publication List
Journal Papers：
[1] Ming-Ching Kuo, Yi-Shing Shih, and Chien-Nan Kuo, "Reconfigurable Low-Noise Amplifier Operating as either Differential or Single-ended,"
International Journal of Electrical Engineering (IJEE) , vol. 17, no. 2, pp.
145-154, Apr. 2010.
[2] Ming-Ching Kuo, Chien-Nan Kuo, and Tzu-Chan Chueh, "Wideband LNA compatible for differential and single-ended inputs," IEEE Microwave and Wireless Component Letters (MWCL), vol. 19, no. 7, pp. 482-484, Jul. 2009.
[3] Ming-Ching Kuo, Shiau-Wen Kao, Chih-Hung Chen, Tsung-Shuen Hung, Yi-Shing Shih, Tzu-Yi Yang, and Chien-Nan Kuo, "A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13-μm CMOS", IEEE J. Solid-State Circuits (JSSC), vol. 44, no. 3, pp. 740-750, Mar. 2009
[4] Chun-Lin Ko, Ming-Ching Kuo, Chien-Nan Kuo, “A CMOS Dual-Mode RF Front-End Receiver for GSM and WCDMA Applications,” IEICE TRANS.
[4] Chun-Lin Ko, Ming-Ching Kuo, Chien-Nan Kuo, “A CMOS Dual-Mode RF Front-End Receiver for GSM and WCDMA Applications,” IEICE TRANS.