Testability

To prevent errors in block design having a large impact on the testability, special test modes should be implemented to allow for testing of circuit blocks in-situ. As mentioned above, the receiver system typically can be divided into three main blocks, PLL, RF front-end, and analog baseband, from the view of functionality and division of labour. Therefore, there exist two interfaces needed to be reserved for testability.

One of them is the interface between the front-end and the analog baseband. Since the signal passing though this interface is at the baseband in a voltage output, four pads can be reserved for connections to the signal traces at the TIA output. This facilitates a bidirectional I/O testing, either to observe the output of RF front-end or to be used as the signal input to allow observation of analog baseband if the front-end does not work. The other interface for testability exists between the front-end and the PLL. This interface is very important to verify the impacts of completely integrated LO chain on the overall receiver performance. At least, it can ensure that the receiver chain performance can be measured if the PLL does not work. As shown in Fig. 5.13, a bidirectional LO testing buffer is implemented to allow observation of the PLL output or the input of an external LO. If the PLL is to be measured, the testing buffer is activated and SWt1/SWt2 are turned off, driving a 50Ω load of the measurement

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instrument. Alternately, the LO pads can be used as inputs by turning on the VCO buffer and LO testing buffer, while activating SWt1/SWt2. Such a capability makes it possible to characterize performance using external LO compared with on-chip LO.

In a normal operation mode, rather than a testing mode, both the LO testing buffer and SW_t1/SW_t2 are turned off, and the on-chip LO source passes through the VCO buffer which drives the quadrature generator, i.e., dividers of divide-by-2/4/6.

Fig. 5.14 Die photograph.

5.7 Measurement Results

The tuner chip was fabricated in 0.13-m 1P8M CMOS process. It occupies a total silicon area of 7.2 mm² including all ESD pads. The chip is housed in a 5x5 mm² 40-pin QFN package. The micrograph of the die is shown in Fig. 5.14, where the analog baseband occupies a significant portion of the chip area due to using low-density MIM capacitors of 1fF/um². A single 1.2 V supply is applied for the measurement. The measured performance referred to the SMA connector input is summarized in Table 5.1.

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The measured NF ranges from 3.7dB to 4.3dB in the UHF band. The stated IIP3 values are measured, applying two-tone frequencies at 13.25MHz and 29.25MHz away from the desired frequency, whereas, for the IIP2, a two-tone test with blockers at 13.25MHz and 16MHz offset was performed. At 11dB back-off from maximum RF gain, which is convergent by the RSSI-AGC loop for L3 blocking test, IIP3 is -4.3dBm while NF is 8.7dB. The current switch path provides a 15dB RF gain backoff, achieving a baseband IIP2 of 50dBm in the UHF band.

The overall NF versus the RFE and ABB gain settings are measured and shown in Fig. 5.15. It is noted that as the ABB gain is towards 0dB, the contribution of the measurement instruments such as the differential probe and spectrum analyzer becomes much dominant. This means that the measured NF is much larger than the real case. Fig. 5.16 illustrates the measured NF at different IF frequency. As can be seen, the flicker noise corner is around 200 kHz.

The measured phase noise spectrum at the synthesizer output is as shown in Fig.

5.17. The noise profile will be lowered by 15dB after a /6 divider for 626MHz channel, resulting in an integrated noise from 400Hz to 4MHz better than 0.3 degrees.

The measured transient frequency response during the locking process is depicted in Fig. 5.18, showing a locking time of 78μsec including coarse and fine tuning. The locking time is still less than 100μsec in the worst case of the power-up sequence.

The C/N plot at the baseband output, evaluated in terms of EVM, is exhibited in Fig.

5.19 by applying an input signal of the 16-QAM 1/2 modulation scheme. The SNR shown is better than 30dB from -70dBm to -7dBm, allowing for robust operation in a mobile environment. Because the BER test (system performance) depends on not only the radio chip but also the baseband demodulator, the estimates in sensitivity, selectivity, and linearity tests are given according to the measured MER not exceeding one specific value based on the modulation scheme defined in the MBRAI specification. In Table 5.2 summarized are these measurement results.

Compared with the previously reported work related to DVB-H tuner, shown in Table 5.3, this chip achieves the lowest power consumption from a single 1.2V supply while maintaining comparable performance. The maximum power consumption is 114mW in the UHF band as all circuits are activated in the continuous mode. However, the power consumption reduces to 103mW in the L-band. The reduced power mainly results from the operation with divide-by-2

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instead of divide-by-6 as well as no usage of RF power detector.

0 10 20 30 40 50 60

4 8 12 16 20 24 28 32 36

RFE=35dB RFE=31dB RFE=26dB RFE=20dB

NF (dB)

ABB Gain Setting (dB)

Fig. 5.15 Measured overall NF versus the RFE and ABB gain settings.

10 100 1000

2 4 6 8 10

NF (dB)

Frequency (KHz)

Fig. 5.16 Measured NF at different IF frequencies.

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Fig. 5.17 Phase noise profile measured at synthesizer output.

Fig. 5.18 Measured locking process of frequency synthesizer.

Chapter 5 Dual-Band RF Tuner in 0.13μm CMOS

estimates by hand cal.

16-QAM, CR=1/2, 8k, GI=1/8

Gain Max/Min/Step (dB) 95/-5/0.5 100/10/0.5

RF range/BB range (dB) 40/63.5 30/63.5 Filter rejection with 4MHz BW

setting @ 5.25/13.25MHz 32/102 (dB)

DC offset 6mV

I/Q matching <-35dBc

Power consumption

in continuous RX 114mW @ 1.2V 103mW @ 1.2V

Die size 7.2 mm² in 0.13 um CMOS

a Measured at (Max RF -19dB).

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Table 5.2

SELECTIVITY/LINEARITY AND SENSITIVITY MEASUREMENT RESULTS Pattern Modulation Interferer

location

BENCHMARK OF RFTUNERS FOR DVB-HAPPLICATIONS Ref.–Year Process Power

(mW)

a 5dB Noise Figure is measured at the channel above 800MHz.

b Measured at (Max RF -10dB).

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5.8 Conclusion

A 1.2V highly integrated RF tuner for DVB-T/H applications in 0.13-μm CMOS technology is demonstrated. Utilizing a direct-conversion structure and a smart frequency plan, the tuner consumes only 114mW in the continuous mode and occupies a silicon area of 7.2 mm². Together with system and circuit design techniques, this tuner complies with the MBRAI 1.0 requirement, while slightly insufficient to meet the stringent MBRAI 2.0 specifications. However, low BOM as well as small PCB size are achieved, requiring a minimum number of external components: an inductor and a coupling capacitor for each LNA input, a crystal, and RC components for the loop filter. Since the supply voltage is as low as 1.2V, it is straightforward to convert to advanced technologies of 65nm and beyond towards a more competitive SoC solution.

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Chapter 6

65nm Tuner Implementation and Verification

Current and future trends call for the highest levels of integration to achieve low cost and low power for handheld wireless devices. Such demands drive nanometer digital CMOS as the process of choice to integrate digital, mixed-signal, and RF components on a chip. For system-on-a-chip (SoC) solutions, the digital part usually occupies a significant part of chip area and consumes much power compared to the mixed-signal and RF parts [64], [65], [66], [67]. New CMOS technology nodes can bring great strides within the digital part in reduced cost, higher speed, and lower power consumption. These benefits also push more and more RF and mixed-signal components to be developed in nanometer CMOS technologies, towards a SoC evolution. This chapter introduces the impacts of technology scaling on RF/mixed-signal design. The previous 0.13-μm CMOS tuner has been migrated to 65nm for SoC integration. New features in this 65nm CMOS tuner will be highlighted in this chapter. In addition, chip verification will be also described in more details.

6.1 Effects of Technology Scaling

For RF and mixed-signal components, technology scaling is a mixed blessing [68]. High-frequency operation typically benefits from the scaling as the transit