Chapter 5 Application to Strained SiC Devices
5.4 The Analysis of I D -RTN in SiC Devices…
5.4.1 Drain Current Waveform
The stress induced slow oxide trap near the drain side which would cause the drain current instability (ID-RTN) through trapping and detrapping of the channel carriers. The ID-RTN measurements were performed in the linear operation at a constant drain voltage VDS= 0.05V for gate voltages VGS between 0.64~0.78 V, in steps of 20mV using HP4156.
Fig. 5.3 and Fig. 5.4 show the different ID-RTN wave spectra for bulk-Si and SiC on S/D device respectively. The drain current amplitude is about 100nA.
5.4.2 Capture and Emission Time
The extracted capture time and emission are shown in Fig. 5.5and Fig. 5.6. We can see the similar behavior of the capture and emission of electrons in the two devices.
5.5 Discussion
5.5.1 Depth
Also, from the ce( versus Vg curve), Fig. 5.7, we can calculate the effective trap depth Zeff from the slope. The depth in bulk is about 5.15A and in SiC on S/D device is about 8.45A. The trap location is deeper in SiC on S/D device than in bulk-Si , as shown in Fig. 5.8 which implies that HC stress produces more damage in the Si/SiO2 for the SiC on S/D device.
5.5.2 Normalized Drain Current Amplitude
The RTN amplitude, ΔID divided by the ID becomes the normalized current amplitude. From Fig. 5.9 and Fig. 5.10, the normalized current amplitude is proportional to the normalized conductance change, gm/ID in the bulk-Si device and SiC on S/D device which implies that the generated slow oxide trap in SiGe on S/D device follows the same mechanism as that of the bulk device. In the SiC on S/D device, the SiC on S/D device will induce the tensile strain along the channel direction to enhance the electron mobility.
As a result, although both CESL and SiC on S/D devices use the uniaxial strain technology to enhance the mobility, there is no extra vertical strain in SiC on S/D device gate dielectric to cause more scattering and degrade the Si/SiO2 interface quality. As a result, the normalized ID-RTN amplitudes have the same trend for SiC on S/D and bulk-Si devices.
Gate
n n
Gate
SiC SiC
(a)
(b)
Fig. 5.1 The cross-section view of the experimental devices, (a) bulk-Si and (b) SiC on S/D devices (uniaxial-strain). Both of them are <100>
channel on (100) substrate.
Bulk
SiC on S/D
0.0 0.2 0.4 0.6 0.8 1.0
0 2 4 6 8 10
Fig. 5.3 Drain current waveform of bulk-Si device, T=25℃.
0 2 4 6 8 10
Fig. 5.4 Drain current waveform of SiC on S/D device, T=25℃.
10/24
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 1E-3
0.01 0.1 1 10
Emission time Capture time
Gate Voltage (volt) E m is s io n t im e ,
e( s e c )
1E-3 0.01 0.1 1 10
Bulk (N)
W/L=0.5/0.04 m
C a p tu re ti m e ,
c(s e c )
Fig. 5.5 Variation of capture time c (filled symbol) and emission time c (open symbol) as gate voltage increases for bulk-Si device.
0.32 0.34 0.36 0.38 0.40 0.42 0.44 1E-3
0.01 0.1 1 10
1E-3 0.01 0.1 1 10
SiC (N)
W/L=0.5/0.04 m
Emission time Capture time
Gate Voltage (volt)
E m is s io n t im e ,
e( s e c ) Ca p tu re t im e ,
c(s e c )
Fig. 5.6 Variation of capture time c (filled symbol) and emission time e
(open symbol) as gate voltage increases for SiC on S/D device.
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.1
1 10
Zeff=8.45A
bulk SiC
Zeff=5.15A
c / e
VG (volt)
Fig. 5.7 Capture time over emission time versus gate voltage plots for n-MOSFETs.
(a)
(b)
Fig.5.8 The effective depth location for the two traps in, (a) bulk-Si and (b)SiC on S/D devices.
8.45Α
Trap
Channel 5.15Α
Trap
Channel
0.6 0.7 0.8 0.9 0.00
0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
I
D/I
D
D
D
g
m
D
Gate Voltage (volt) Bulk (N)
W/L=0.5/0.04 m
Fig. 5.9 Normalized RTN amplitude (square symbol) and normalized conductance change (circle symbol) versus gate voltage for bulk-Si device.
0.25 0.30 0.35 0.40 0.45 0.50 0.00
0.02 0.04 0.06
I
D/I
D
D
Dg
m
DGate Voltage (volt) SiC (N)
W/L=0.5/0.04 m
Fig. 5.10 Normalized RTN amplitude (square symbol) and normalized conductance change (circle symbol) versus gate voltage for SiC on S/D device.
-0.2 -0.1 0.0 0.1 0.2 0.00
0.02 0.04 0.06 0.08
0.10 bulk
SiC
V
G-V
th
(volt)
I
D/I
DFig. 5.11 Normalized current amplitude versus overdrive voltage for bulk-Si and SiC on S/D devices.
tensile stress
SiC on S/D S D
Fig. 5.12 Illustration of the strain direction for SiC on S/D device.
Chapter 6 Summary and Conclusion
In this thesis, we are the first to examine the strain-induced trap behavior in MOS devices using the ID-RTN technique [6.1]. The process induced strain among different strained techniques can be investigated by the ID-RTN measurement. The hot carrier stress which induces the current degradation and produces the slow oxide traps are studied for both uniaxial strained n- and p-MOSFETs.
First, the strain induced drain current instability is investigated in the thesis. The oxide traps properties in the stained CMOS devices are analyzed. Then, different process-induced strain effects for uniaxial strained n-MOSFETs and p-MOSFETs have been observed respectively. Experimental results show that, in the CESL devices, vertical compressive strain generates extra oxide defects and induces more scattering after HC stress. The strain techniques would improve the carrier mobility but their hot carrier reliabilities become poorer. Furthermore, the application to the SiC on S/D devices also shows that the uniaxial strain in such device exhibits less impact on the device reliability.
Therefore, this strained SiC device is similar to the SiGe S/D device in terms of the ID-RTN characteristics. As a result, the CESL strain can induce more scattering effect that would contribute to a non-negligible amount of extra device degradation.
In summary, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been justified by the ID-RTN technique. By utilizing the approach, the ID-RTN slow oxide trap produced by the HC stress can be measured in both strained n- and p-MOSFETs. The extra degradation coming from the
stress of CESL device shows a significant amount of the mobility as well as the drain current degradation by the vertical strain. This method also provides a way to measure the slow traps that charge pumping can not achieve (i.e., charge pumping can measure the fast trap only.)
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