Theory of Drain Current Telegraph Noise

Figure 2.3(a) is the schematic showing the carrier trapping and detrapping through the oxide trap. In small devices, only trap energy within a few kT from the Fermi level would make current fluctuation where k and T are the Boltzmann constant and equilibrium temperature, respectively. So far, the drain current fluctuation is generally influenced by two effects: the number fluctuation of free channel carriers ΔNs, and the mobility fluctuation Δμ described by [2.2][2.3].

(2.1)

in the strong inversion. Here Ns is the channel carriers per unit area andα is the scattering coefficient while the sign in front of the mobility fluctuation is determined by the type of the trap (repulsive or attractive scattering center). For an acceptor type trap, the high level corresponds to the neutral state (no captured carrier) while the low level corresponds to the charged state. When the traps in the dielectric are empty and their energy level maintain at a level which is equal to that of the channel carriers or below, traps will capture carriers from the channel. When the carriers are trapped, they will increase the nearby potential and lower the current.

The three major parameters (capture time, emission time, and current amplitude) of the ID-RTN are defined in Fig. 2.3(b), capture time c is the average of the high time constants, emission time _e is the average of the low time constant and current amplitude ΔID is the magnitude of the drain fluctuation. The current amplitude, capture and emission time are the critical parameters of random telegraph noise phenomenon which

1 ]

depend on the trap properties, such as trap depth into dielectrics, trap energy apart from conduction band (valance band if holes are captured and emitted).

Parameter Analyzer HP 4156C

PC

Probe Station

Fig. 2.1 The measurement setup using Analyzer HP 4156C to sampling as RTN processing. Notably there is not switch equipment HP 5250 here.

Fig. 2.2 The terminals setup for sampling by Analyzer HP4156C.

Poly-S i SiON O

Source Drain

Substrat e

+V _G

+V _D

trap

em ission captu re

S D

carrier

(a)

(b)

Fig. 2.3 (a) Carrier trapping and detrapping by the slow trap near the drain side. (b) Illustration of the three parameter of the RTN noise: capture time c, emission time e , and current amplitudeΔID.

D ra in C u rr en t

Time

 c

 e

Δ I _D

Chapter 3 Random Telegraph Noise of Drain Current in

n-MOSFETs

3.1 Introduction

Recently, researches have shown an increasing interest in the strain technology.

Strained silicon technology is essential for the continuation for the scaling of MOSFET devices, owing to its high impact on carrier mobility and thus on drive current improvement [3.1]. When applied to the direction of the channel, tensile strain improves the performance of n-MOSFET devices, while compressive strain is beneficial for p-MOSFET devices. The local strain, such as capping layer, SiGe on S/D, and SiC on S/D are induced by the process. They are usually uniaxial strain. Compared to the global strain usually biaxial strain, the local strain has less dislocation issues.

As the devices being scaled, there are plenty of reliability issues in the strained devices. Besides, trapping of a single carrier charge in traps and related local modulation in carrier density and mobility will have a profound influence in the carrier density and mobility on the drain current. The drain current fluctuation will cause serious drawbacks on the small geometry devices.

In this chapter, the ID-RTN “Drain Current Random Telegraph Noise” for the exploration of strain-induced slow trap properties is presented in strained n-MOSFETs.

Single electron capture and emission could be observed. The analysis of the reliability will be introduced first in Section 3.3. Next, the analysis of drain current instability is

interpreted in Section 3.4. Based on the voltage dependence of single charge effect, the traps parameters are extracted and the strain process induced-effect will be also discussed.

3.2 Device Preparation

The devices were fabricated by the advanced 65nm CMOS technology at UMC.

The schematic cross section diagram of n-MOSFET splits is shown in Fig. 3-1. In this figure, Fig. 3-1(a) is the bulk-Si device, and Fig. 3-1(b) is the CESL (contact etching stopping layer) capped device (uniaxial-strained). Both n-MOSFETs are <100> channel on (100) substrate. All these test devices have 14Å EOT gate oxide with SiON process and with the same dimension (W/L= 0.2/0.12um).

3.3 The Analysis of Reliability in n-MOSFETs

3.3.1 Introduction

The strain technologies can enlarge the mobility to achieve the significant driving current enhancement [3.2] [3.3] [3.4]. However, many technologies have been developed to boost the drive current; the reliability issues have been rarely studied. It is necessary to consider the effects for device characteristics involving uniaxial and biaxial strained effects for CMOS devices.

A large mobility enhancement would adversely affect the device reliability [3.5].

For n-MOSFETs, the CESL device becomes the most promising technology and the better reliability, especially with process simplicity. In 2006, S. S. Chung et al. [3.6] first

published a paper, in which they demonstrated for n-MOSFETs, tensile cap stressor device is much better in terms of reliability and performance. Based on the important results, we will further analyze the reliability issues of strain n-MOSFETs and investigate them by the ID-RTN method after hot carrier stress. They are described in two parts. The first part is to investigate hot carrier degradation and the second part is to analyze the drain current instability after HC stress in bulk-Si and CESL devices. For hot carrier degradation, threshold voltage shift, drain current degradation and transconductance degradation would be observed by electric measurement. These stresses generate the interface trap and fixed oxide charges. For the drain current instability, the stress-induced traps’ properties and the relationship between the strain and the ID-RTN results would be studied.

3.3.2 Drain Current Degradation

The procedure of following experiment is shown in Fig. 3.2. Firstly, in the ID-VG

step, the purpose is to get the basic semiconductor parameters and make sure the devices can work successfully .Then, the devices are subjected to the ID-RTN analysis, to ensure that there is no current fluctuation in the fresh devices (i.e., no process induced traps).

Then, we apply the hot carrier stress, to produce the oxide traps near the drain region which would show a two-level fluctuation of drain current. Subsequently, the ID-RTN measurement is applied to the stressed devices. Under hot carrier stress with injecting hot electrons to destruct gate dielectrics, we could prevent the effect of changing temperature and measure RTN at once. Traps generation for apparent two-level fluctuations is hard to say happening on specific time and its dependence with time on different stress voltage is also not regular. In our measurement, after HC stress (VGS= VDS= 2.5V for 300sec), we

obtain significant RTN appearance in the linear region and continued subsequent analysis.

We show the ID-RTN measurement results for stressed devices and discussed the induced slow traps properties in the coming sections.

Figures 3.3 (a) and (b) show the drain current degradations before and after the HC stress. The drain current degradation in CESL device is 27.16% and in bulk is 15.62%.

The CESL device shows large drain current degradation than bulk device, as result of its higher impact ionization rate (I_B/I_D) caused by the strain effect [3.7]. A large enhancement of the driving current will adversely degrade the device reliability.

3.4 The Analysis of I

D

-RTN in n-MOSFETs

3.4.1 Drain Current Waveform

The stress induced slow oxide trap near the drain side which would cause the drain current instability (ID-RTN) through the trapping and detrapping of channel carriers. The ID-RTN measurements were performed in linear operation at a constant drain voltage VDS= 0.05V for gate voltages VGS between 0.3 - 1 V, in steps of 20mV using HP4156C.

Fig. 3.4 and Fig. 3.5 show the different ID-RTN wave spectra for bulk-Si and CESL devices respectively. The drain current amplitude is about 50nA.

3.4.2 Capture and Emission Time

Fig. 3.6 and Fig. 3.7show the mean capture and emission time gathered statistics from Fig. 3.4 and Fig. 3.5. The decrease of c, as gate bias increases shows the acceptor type of the generated slow oxide trap [3.8]; and the capture time, c, of the slow oxide



trap in the CESL device is larger than bulk-Si device in Fig. 3.6, which implies that the trap is deeper in CESL device is larger than the bulk-Si device. The magnitudes of emission time e are both about 0.01~ 0.1 sec. While, the magnitudes of the emission time

e do not show much difference. From the dependency of e, versus gate bias, the carrier in bulk-Si device detraps via Frenkel-Poole emission while carrier in CESL device detraps via trap-assisted-tunneling to the silicon substrate. Due to the thermal emission for the carrier in the bulk-silicon’s trap, the emission time decreases as gate voltage increasing in Fig. 3.6. This implies that the bulk device’s trap is near the Si/SiO₂ interface.

While the carrier detraps through thermally assist tunneling to the Si for CESL device, emission time increases as gate voltage increases in Fig. 3.7. Furthermore, the trapping and detrapping events happen more frequently in CESL devices so the capture time over the emission time increases more quickly in CESL than bulk device in Fig. 3.8. This also assures that the HC stress produces more damage at the Si/SiO2 for the CESL device and the trap is deeper in CESL device than bulk-Si device ones.

3.5 Discussion

According to the Shockley–Read–Hall statistics [3.9], the capture time c is sensitive to the channel carrier density n, the average carrier velocity v, and the capture cross-section  as Eq. (3.1), where

Here,  is the capture cross section. Here, ₀ is the cross-section prefactor, and E_B is the thermal activation energy for capture. T and v are usually taken to be the equilibrium lattice temperature and average thermal velocity vth. This approximation is invalid at large lateral electric field, and electron heating occurs and affects the electron capture time. As the gate bias increasing, the capture time would be decreased due to the increased carrier density in the channel. Emission time e is given as Eq. (3.3) [3.10],

(3.3)

where g is the degeneracy factor. The term (EF-ET) represents the trap energy with respect to the Fermi energy. k_B is the Boltzmann constant.

3.5.1 Trap Depth

The relationship between the mean capture and emission times and trap parameters can be described as the following [3.11],

and V_FB is the flat-band voltage. We can estimate Z_eff, effective depth from substrate, from measurements of _c/_e by varying VG. The trap depth is extracted from the slope of ln(c/e) versus VG as shown in Eq. 3.5. Zeff is 1.09A for bulk device and 6.70A for CESL device shown in Fig. 3.10. The trap in CESL is deeper than the trap in bulk-Si. The characterized depth of generated traps in Fig. 3.10 shows that CESL device will cause more fluctuations, Fig. 3.5. This also assures that HC stress produces more damage in the Si/SiO2 for the CESL and the trap location is deeper is deeper in CESL than in bulk-Si, Fig. 3.10.

3.5.2 Normalized Drain Current Amplitude

Fig. 3.11 and Fig. 3.12 show the drain current amplitude gathered statistics from Fig.

3.4 and Fig. 3.5 divided by the drain current and take plots as function of gate bias. At very low drain voltages in the strong inversion, the mobility fluctuations term Δμ/μ plays a more dominant role than the number fluctuations Δ Ns / N [3.11], i.e.,

(3.6)

Furthermore, the variation of the RTN amplitude ΔI_D/I_D is proportional to the normalized transconductance change gm/ID ratio[3.12]

(3.7)

carrier fluctuation Δ N_s nor by the mobility Δμ[3.11]. Since a screened Coulomb scatter with very similarαvalues for comparable channel electron densities [3.11][3.13] , the ΔID/ID roll-off quickly in CESL device reveals that an extra carrier scattering is induced.

This will give rise to an additional mobility degradation of the CESL device after the HC-stress.

Gate

n n

(a)

(b)

Fig. 3.1 The cross-section view of the experimental devices. (a) bulk-Si and (b) CESL (contact etching stopping layer) capped devices (uniaxial-strain). Both of them are <100> channel on (100) substrate.

Bulk

CESL

Capping Layer

Procedure

Hot Carrier Stress I

_D

-V

_G

I

_D

RTN

I

_D

RTN

Fig. 3.2 The operating procedure of the following analysis for the devices.

0 . 0 0 .2 0 . 4 0 . 6 0 .8 1 . 0 before and after the HC stress, (a) bulk-Si and (b) CESL devices.

0.5 1.0 1.5 2.0

Fig. 3.4 Drain current waveform of bulk-Si device, T=25℃

0.5 1.0 1.5 2.0

Fig. 3.5 Drain current waveform of CESL device, T=25℃

0.6 0.7 0.8 0.9 1.0 10

^-3

10

^-2

10

^-1

10

⁰

10

¹

Gate Voltage (V) C a p tu re T ime ,  c( se c)

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

E mi ss io n T ime , 

e (s ec )

Tox=14A

W/L=0.2/0.12  m

Capture time Emission tim e

Bulk(n)

Fig. 3.6 Variation of capture time c (filled symbol) and emission time _e (open symbol) as gate voltage increases for bulk-Si device.

0.4 0.5 0.6 10

^-3

10

^-2

10

^-1

10

⁰

10

¹

10

^-3

10

^-2

10

^-1

10

⁰

10

¹

C a pt u r e T im e ,  c (s ec )

Gate Voltage (V)

Tox=14A

W /L =0.2/0.12  m

Capture time Emission time

C ESL

E m is sio n T im e ,  e ( se c )

Fig. 3.7 Variation of capture time c (filled symbol) and emission time _e (open symbol) as gate voltage increases for CESL device.

0.4 0.6 0.8 1.0 1

10 100

 c /  e

G a te V o ltag e (V )

B u lk (n ) C E S L Z eff=6.7A

Z eff=1.09A

Fig. 3.8 Capture time over emission time versus gate voltage plots for n-MOSFETs.

Fig. 3.9 Energy band diagram at the trap position in the channel.

Ec

Ev E

_F

E

_Cd

- E

_T

Z

_eff

　

E

Fg Cg

Trap

　

Channel Dielectric

Gate

φ ₀

q Ψ

_S

(a)

(b)

Fig. 3.10 The effective depth location for the two traps in, (a) bulk-Si and (b) CESL devices.

6.7Α

　

Trap

Channel Dielectric

Gate

1.09Α

　

Trap

Channel Dielectric

Gate

0.6 0.7 0.8 0.9 1.0 0.00

0.02 0.04

Tox=14A W/L=0.2/0.12  m VDS=0.05V

Bulk(n)

 I D

/I D _g

m

/I

_D



I

_D

/I

_D

Gate Voltage (V)

Fig. 3.11 Normalized RTN amplitude (filled symbol) and normalized conductance change (open symbol) versus gate voltage for bulk-Si device.

0.4 0.5 0.6 0.7

gm/ID

 I D /I

D

T ox=14A

W /L =0.2/0.12  m V

_DS

=0.05V

C E SL

 I D

/I D

G ate V oltage (V )

Fig. 3.12 Normalized RTN amplitude (filled symbol) and normalized conductance change (open symbol) versus gate voltage for bulk-Si device.

Chapter 4 Random Telegraph Noise of Drain Current in

p-MOSFETs

4.1 Introduction

Mobility enhancement is a method to improve the CMOS devices performance with the scaling of the device size. The increase of carrier mobility is necessary to realize the high-speed CMOS devices. Recently, various strain technology have been utilized to enhance the drive current. It is necessary to understand the introduced uniaxial and biaxial strains in n-MOSFET or p-MOSFET devices. Initially, the typical mobility enhancement of n-type strained-Si is much larger than that of p-type devices. Several techniques have been further developed to enhance the p-MOSFET performance, i.e., SiGe on S/D device [4.1]. Materials with same crystal structure but different lattice are good candidates for strain engineering. The SiGe has been successfully incorporated in the source and drain of p-MOSFET devices to strain the channel compressively and increase the hole mobility. Furthermore, trapping of a single carrier charge in traps and related local modulation in carrier density and mobility exhibit a profound influence in the carrier density and mobility on the drain current. The drain current fluctuation will cause serious drawbacks on the small geometry devices.

In this chapter, the ID-RTN “Drain Current Random Telegraph Noise” for the exploration of strain-induced slow trap properties is presented. Single electron capture and emission could be observed in strained p-MOSFETs. The analysis of the reliability will be introduced first in Section 4.3. Next, the analysis of drain current instability is

interpreted in Section 4.4. Based on the voltage dependence of single charge effect, the traps parameters are extracted and the strain process induced-effect will also be explained.

4.2 Device Preparation

The schematic cross sections of p-MOSFET splits are shown in Fig. 4-1. In this figure, Fig. 4-1(a) is the bulk-Si device, and Fig. 4-1(b) is the SiGe on source/drain device (uniaxial-strain) with EDB (Embedded Diffusion Barrier). Both p-MOSFETs are

<110> channel on (100) substrate. All these test devices have 14Å EOT of SiON gate oxide and with the same dimensions, W/L = 0.2/0.12 μm. The I_D-RTN was investigated in bulk and SiGe on S/D pMOSFET devices fabricated using a conventional CMOS process flow.

4.3 The Analysis of Reliability in p-MOSFETs

4.3.1 Introduction

For many strained approach to enhance the carrier mobility, the reliabilities are still a serious issue. The biaxial strained SiGe-channel device provides good drive current enhancement, it suffers from the Ge-outdiffusion such that exhibits worse reliability. The SiGe on S/D device is a promising structure for p-MOSFET design since it keeps at about the same reliability as the SiGe-channel ones while exhibits a much higher performance.

In contrast, SiGe-channel has a major concern with lattice misfit [4.2]. Besides, for p-MOSFET devices, the SiGe on S/D device with EDB [4.3] is the most promising in terms of performance and reliability.

In this section, we analyze the reliabilities of strained p-MOSFET devices and investigate them by the ID-RTN method after hot carrier stress. We divide the contents into two main sections. The first part is to investigate hot carrier degradation and the second part is to analyze the drain current instability for p-MOSFETs. In hot carrier degradation, threshold voltage shift, drain current degradation, and transconductance degradation would be observed by electric measurement. These stresses generate the interface trap and fixed oxide charges. For the drain current instability, the stress-induced traps’ properties and the relationship between the strain and the I_D-RTN results would be understood. Finally, the comparison for the strained n- and p-MOSFETs would be discussed according to the previous result.

4.3.2 Drain Current Degradation

Similar experimental procedures have been conducted for SiGe S/D device and bulk-Si p-MOSFET devices. After the hot carrier stress (VGS=VDS= -2.5V 300sec), Figs.

4.2 (a) and (b) show that the drain current degradation before and after the HC-stress. The drain current degradation in SiGe on S/D device is 16% and in bulk-Si device is 7.44%.

The SiGe on S/D device shows large drain current degradation than bulk device, resulting from its higher impact ionization caused by the strain and the Ge out-diffusion [4.4]. The SiGe on S/D device has a larger impact ionization rate and Ge out-diffusion near the drain region which gives rise to larger drain current degradation than bulk device, caused by the impact ionization rate, the SiGe on S/D devices have a worse ID degradation, i.e., worse immunity for hot-carrier stress.

4.4 The Analysis of I

D

-RTN in p-MOSFETs

4.4.1 Drain Current Waveform

The stress induced slow oxide trap near the drain side which would cause the drain current instability (I_D-RTN) through trapping and detrapping the carriers in channel. The ID-RTN measurements were performed in linear operation at a constant drain voltage VDS= -0.05V for gate voltages |VGS| between 0.3 - 1 V, in steps of 20mV using HP4156.

Fig. 4.3 and Fig. 4.4 show the different I_D-RTN wave spectra for bulk-Si and SiGe on S/D device respectively. The drain current amplitude is about 50nA.

4.4.2 Capture and Emission Time

From Fig. 4.3 and Fig. 4.4, we analyzed the capture and emission time for the two devices. In Fig. 4.5 and Fig. 4.6, as the gate bias increases, the capture time, c decreased due to a larger carrier concentration in the channel. While the emission time, e decreased with increasing gate bias which means that the carrier detraps through thermally assist tunneling to the Si. The magnitudes of c and e are both about 0.01~0.1 sec.As a result, both devices show similar behavior of the capture and emission of holes.

4.5 Discussion

4.5.1 Trap Depth

The relationship between the mean capture and emission times and trap parameters can be described as Eq. 3.4. The trap depth is extracted from the slope of ln(c/e) versus VG as shown in Eq. 3.5. Zeff is 9.59A for bulk-Si device and 10.39A for SiGe on S/D

device shown in Fig. 4.7. Also, the depths of generated oxide traps location are about the same (~10A) in Fig. 4.8 for both devices so the capture time over the emission time take no difference in the two oxide traps (Fig. 4.7).

4.5.2 Normalized Drain Current Amplitude

The normalized change of the ID-RTN amplitude is proportional to the normalized conduction change for both devices (Fig. 4.9 and Fig. 4.10). This implies that the generated slow oxide trap in SiGe on S/D follows the same mechanism as that of bulk device.

4.6 The Comparison Between n- and p-MOSFETs

4.6.1 Introduction

The hot carrier degradation of the CMOS devices with various strain technologies were enhanced by high lateral acceleration and larger impact ionization current. The worst case of hot carrier degradation occurs at VGS= VDS condition and the degradation will follow the trend of impact ionization rate and effective mobility. In addition to the discussion on the reliabilities of uniaxial strained CMOS devices, for the first time, the I_D-RTN for the strained-Si devices is analyzed. In order to identify the differences of previous experimental results, the strain effects in CESL device and SiGe on S/D devicecan be identified by Fig. 4.11. The capping layer in the n-MOSFET devices provides the tensile strain along the channel direction and also the compressive strain along the vertical direction [4.5]. The SiGe on S/D devices inducing the compressive strain along the channel region gives rise to the hole mobility enhancement.

4.6.2 Charge Pumping Measurement

The charge pumping (CP) measurement is efficient for the reliability characterization. However, the charge pumping measurement can’t be used reliably in the

The charge pumping (CP) measurement is efficient for the reliability characterization. However, the charge pumping measurement can’t be used reliably in the

在文檔中 隨機電報訊號量測法應用於前瞻CMOS元件應變技術引致的汲極電流不穩定性之研究 (頁 18-0)