I D -RTN: Normalized Drain Current Amplitude

Under the strong inversion, for comparable Ns (carrier concentration), ΔID/ID

(normalized current amplitude) should be proportional to the mobility [4.7]. From Fig.

4.14, the ΔID/ID roll-off more quickly in the CESL device compared to the bulk-Si device, while the SiGe on S/D device and bulk-Si device show comparable trend. Because of the extra vertical strains in the CESL device gate dielectric (Fig. 4.11), this would cause more scattering and degrade the Si/SiO₂ interface quality after the HC stress.

4.6.4 Discussion

The vertical strain on the gate oxide causes higher mobility degradation in CESL device than bulk-Si device, in poly-Si gated devices. We believe that the drain current degradation between n-MOSFET and p-MOSFET could be due to the extra strain stress on the gate dielectric.

The vertical strain causes about 0.43 times of the total drain current degradation (~one-quarter of the total degradation). As a result: (1) the strain techniques can enhance the device performance while on the contrary they show poorer got carrier reliabilities, (2) more scattering is induced by the CESL strain (as observed in n-MOSFET) which can induce the mobility degradation and make worse the device reliability.

Gate

p p

Gate

SiGe SiGe

(a)

(b)

Fig. 4.1 The cross-section view of the experimental devices, (a) bulk-Si and (b) SiGe on S/D device (biaxial-strain). Both of them are <110>

channel on (100) substrate.

Bulk

SiGe on S/D

0 .0 - 0 .2 - 0 .4 - 0 .6 -0 .8 - 1 .0 before and after the HC stress, (a) bulk-Si and (b)SiGe S/D devices.

4.2 4.4 4.6 4.8 5.0 5.2 1.12

1.16 1.71 1.74 2.40 2.44 3.20 3.24 4.12 4.16 5.08 5.12

VG=0.375V VG=0.4V VG=0.425V VG=0.45V

VG=0.475V VG=0.5V

Time (s) D ra in C u rr en t, I D (  A ) 1 0

Fig. 4.3 Drain current waveform of bulk-Si device, T= 25℃.

3.00

0.35 0.40 0.45 10

^-3

10

^-2

10

^-1

10

⁰

Gate Voltage, VG (-V)

C a p tu r e Ti m e , 

c

(s ec)

10

^-3

10

^-2

10

^-1

10

⁰

e E m is si o n T im e ,  (s ec ) Tox=14A

W/L=0.2/0.12  m

Capture time Emission time

Bulk(P)

Fig. 4.5 Variation of capture time c (filled symbol) and emission time e

(open symbol) as gate voltage increases for bulk-Si device.

0.35 0.40 0.45 10

^-3

10

^-2

10

^-1

10

⁰

Capture time Emission time

10

^-3

10

^-2

10

^-1

10

⁰

SiGe S/D

Tox=14A

W/L=0.2/0.12  m

E mi ss io n T ime , 

e

(s e c)

10 10 10 10

C a pt ur e T im e ,  c (s e c )

Fig. 4.6 Variation of capture time c (filled symbol) and emission time e

(open symbol) as gate voltage increases for SiGe on S/D device.

0.36 0.40 0.44 0.48 0.1

1 10

 c /  e

Gate Voltage, V

G (-V)

SiG e Bulk

Zeff=9.59A

Z eff ^=10.39A

Fig. 4.7 Capture time over emission time versus gate voltage plots for p-MOSFETs.

(a)

(b)

Fig. 4.8 The effective depth location for the two traps in, (a) bulk-Si and (b) SiGe on S/D devices.

10.39Α

　

Trap

Channel Dielectric

Gate

9.59Α

　 Trap

Channel Dielectric

Gate

0.35 0.40 0.45 0.00

0.01 0.02

 ID/ID gm/ID

 I D /I D

Tox=14A

W /L=0.2/0.12  m VDS=0.05mV

Gate Voltage, V

_G

(-V)

Bulk(P)

Fig. 4.9 Normalized RTN amplitude (filled symbol) and normalized conductance change (open symbol) versus gate voltage for bulk-Si device.

.

0.35 0.40 0.45

0.00 0.01 0.02 0.03

W/L=0.2/0.12  m VDS=0.05mV

SiGe S/D

 ID/ID gm/ID

Tox=14A

Gate Voltage, V

G

(-V)

 I D /I D

Fig. 4.10 Normalized RTN amplitude (filled symbol) and normalized conductance change (open symbol) versus gate voltage for SiGe on S/D device.

tensile stress

compressive stress

S D

CESL

Capping layer

compressive stress

SiGe on S/D S D

(a)

(b)

Fig. 4.11 Illustration of the various strains for (a) CESL and (b) SiGe on S/D devices.

-0.5 0.0 0.5 1.0 0.0

10.0p 20.0p 30.0p

I c ( A ) p

Gate Voltage,V

gh (V) Bulk_stress

Bulk_fresh CESL_stress CESL_fresh

1300%

1032%

1.26

Fig. 4.12 Comparison of charge pumping current for bulk-Si and CESL devices

0.0 0.2 0.4 0.6 0.8 1.0 0

5 10 15 20

D rain C u rr e n t, I D (  A )

D ra in V o lta g e, V

D

(V ) C E S L_ fresh C E S L _ stress B u lk_ fresh B u lk_ stress

27%

16%

1.69

Fig. 4.13 Comparison of drain current degradation for bulk-Si and CESL devices.

0.0 0.2 0.4 0.6 0.01

0.02 0.03 0.04

 I D /I D

|V

_G

-V

_th

|

Bulk(n) CESL

-0.1 0.0 0.1 0.2 0.3

|V

_G

-V

_th

|

SiGe S/D bulk(P)

Fig. 4.14 Normalized current amplitude versus overdrive voltage. (left) n-MOSFETs (right) p-MOSFETs. Note that the huge drop for CESL device is caused by the vertical strain in CESL device.

Chapter 5 Application to Strained SiC Devices

5.1 Introduction

Strained silicon channel has become an essential component of modern high-performance CMOS technology. In order to overcome the MOSFET device scaling difficulties, various strained-Si schemes have become essential components for 45 nm and beyond. Recently, strained n-MOSFET with embedded Si:C on source and drain has received much interest owing to its good scalability for gate length small than 40nm [5.1].

With the same lattice constant that is smaller than Si, silicon carbon alloy (Si:C) embedded in the source and drain can provide tensile strain along the channel direction and enhance the electron mobility for n-MOSFET. The SiC on S/D is a superior stressor compared to SMT and shows better scalability for high performance thin-oxide short channel n-MOSFET [5.2] [5.3].

In this chapter, the application to the SiC device would be illustrated by the ID-RTN method. The experiment results would also be discussed and compared with the pervious chapters’ result.

.

5.2 Device Preparation

The devices were fabricated by the advanced 40nm technology. The schematic cross section diagram of n-MOSFET splits is shown in Fig. 5-1. In this figure, Fig. 5-1(a) is the bulk-Si device, and Fig. 5-1(b) is the SiC on S/D device (uniaxial-strain). Both

n-MOSFETs are <100> channel on (100) substrate. All these test devices have 12Å EOT gate oxide with SiON process and with the same dimension (W/L= 0.2/0.04um).

5.3 The Analysis of Reliability in SiC devices

5.3.1 Introduction

Comparing to the bulk device, the SiC on S/D device shows good drive current and enhancement of channel mobility. Although SiC on S/D device is an alternative for high current enhancement, its off-state junction leakage is a serious problem for reliability [5.4]. In this chapter, we take similar analysis in the SiC on S/D device for the HC reliability issues and the I_D-RTN experiments after hot carrier stress. In the first part, the HC reliability results would be investigated. In the second part, the ID-RTN in bulk-Si and SiC on S/D devices would be studied for the stress-induced traps’ properties and the relationship between the strain’s directions.

5.3.2 Drain Current Degradation

The HC stress condition is VGS= VDS= 2V 500sec for the two samples. Fig. 5.2 shows that the drain current degradation before and after the HC-stress. The drain current degradation in bulk is 8.06% and in SiC on S/D device is 11.9%. The drain current degradation is enhanced in the SiC on S/D device comparing to the bulk devices, as result of its higher impact ionization caused by the strain.

5.4 The Analysis of I

D

-RTN in SiC Devices

5.4.1 Drain Current Waveform

The stress induced slow oxide trap near the drain side which would cause the drain current instability (I_D-RTN) through trapping and detrapping of the channel carriers. The ID-RTN measurements were performed in the linear operation at a constant drain voltage VDS= 0.05V for gate voltages VGS between 0.64~0.78 V, in steps of 20mV using HP4156.

Fig. 5.3 and Fig. 5.4 show the different I_D-RTN wave spectra for bulk-Si and SiC on S/D device respectively. The drain current amplitude is about 100nA.

5.4.2 Capture and Emission Time

The extracted capture time and emission are shown in Fig. 5.5and Fig. 5.6. We can see the similar behavior of the capture and emission of electrons in the two devices.

5.5 Discussion

5.5.1 Depth

Also, from the _c_e( versus Vg curve), Fig. 5.7, we can calculate the effective trap depth Zeff from the slope. The depth in bulk is about 5.15A and in SiC on S/D device is about 8.45A. The trap location is deeper in SiC on S/D device than in bulk-Si , as shown in Fig. 5.8 which implies that HC stress produces more damage in the Si/SiO2 for the SiC on S/D device.

5.5.2 Normalized Drain Current Amplitude

The RTN amplitude, ΔID divided by the ID becomes the normalized current amplitude. From Fig. 5.9 and Fig. 5.10, the normalized current amplitude is proportional to the normalized conductance change, gm/I_D in the bulk-Si device and SiC on S/D device which implies that the generated slow oxide trap in SiGe on S/D device follows the same mechanism as that of the bulk device. In the SiC on S/D device, the SiC on S/D device will induce the tensile strain along the channel direction to enhance the electron mobility.

As a result, although both CESL and SiC on S/D devices use the uniaxial strain technology to enhance the mobility, there is no extra vertical strain in SiC on S/D device gate dielectric to cause more scattering and degrade the Si/SiO2 interface quality. As a result, the normalized ID-RTN amplitudes have the same trend for SiC on S/D and bulk-Si devices.

Gate

n n

Gate

SiC SiC

(a)

(b)

Fig. 5.1 The cross-section view of the experimental devices, (a) bulk-Si and (b) SiC on S/D devices (uniaxial-strain). Both of them are <100>

channel on (100) substrate.

Bulk

SiC on S/D

0.0 0.2 0.4 0.6 0.8 1.0

0 2 4 6 8 10

Fig. 5.3 Drain current waveform of bulk-Si device, T=25℃.

0 2 4 6 8 10

Fig. 5.4 Drain current waveform of SiC on S/D device, T=25℃.

10/24

0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 1E-3

0.01 0.1 1 10

Emission time Capture time

Gate Voltage (volt) E m is s io n t im e , 

e

( s e c )

1E-3 0.01 0.1 1 10

Bulk (N)

W/L=0.5/0.04 m

C a p tu re ti m e , 

c

(s e c )

Fig. 5.5 Variation of capture time c (filled symbol) and emission time c (open symbol) as gate voltage increases for bulk-Si device.

0.32 0.34 0.36 0.38 0.40 0.42 0.44 1E-3

0.01 0.1 1 10

1E-3 0.01 0.1 1 10

SiC (N)

W/L=0.5/0.04  m

Emission time Capture time

Gate Voltage (volt)

E m is s io n t im e , 

e

( s e c ) Ca p tu re t im e , 

c

(s e c )

Fig. 5.6 Variation of capture time c (filled symbol) and emission time e

(open symbol) as gate voltage increases for SiC on S/D device.

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.1

1 10

Zeff=8.45A

bulk SiC

Zeff=5.15A

 c /  e

VG (volt)

Fig. 5.7 Capture time over emission time versus gate voltage plots for n-MOSFETs.

(a)

(b)

Fig.5.8 The effective depth location for the two traps in, (a) bulk-Si and (b)SiC on S/D devices.

8.45Α

　 Trap

Channel 5.15Α

　 Trap

Channel

0.6 0.7 0.8 0.9 0.00

0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16

 I

D

/I

D



D



D

g

m



D

Gate Voltage (volt) Bulk (N)

W/L=0.5/0.04  m

Fig. 5.9 Normalized RTN amplitude (square symbol) and normalized conductance change (circle symbol) versus gate voltage for bulk-Si device.

0.25 0.30 0.35 0.40 0.45 0.50 0.00

0.02 0.04 0.06

 I

D

/I

D



_D



_D

g

_m



_D

Gate Voltage (volt) SiC (N)

W/L=0.5/0.04  m

Fig. 5.10 Normalized RTN amplitude (square symbol) and normalized conductance change (circle symbol) versus gate voltage for SiC on S/D device.

-0.2 -0.1 0.0 0.1 0.2 0.00

0.02 0.04 0.06 0.08

0.10 bulk

SiC

V

G

-V

th

(volt)

 I

D

/I

D

Fig. 5.11 Normalized current amplitude versus overdrive voltage for bulk-Si and SiC on S/D devices.

tensile stress

SiC on S/D S D

Fig. 5.12 Illustration of the strain direction for SiC on S/D device.

Chapter 6 Summary and Conclusion

In this thesis, we are the first to examine the strain-induced trap behavior in MOS devices using the I_D-RTN technique [6.1]. The process induced strain among different strained techniques can be investigated by the ID-RTN measurement. The hot carrier stress which induces the current degradation and produces the slow oxide traps are studied for both uniaxial strained n- and p-MOSFETs.

First, the strain induced drain current instability is investigated in the thesis. The oxide traps properties in the stained CMOS devices are analyzed. Then, different process-induced strain effects for uniaxial strained n-MOSFETs and p-MOSFETs have been observed respectively. Experimental results show that, in the CESL devices, vertical compressive strain generates extra oxide defects and induces more scattering after HC stress. The strain techniques would improve the carrier mobility but their hot carrier reliabilities become poorer. Furthermore, the application to the SiC on S/D devices also shows that the uniaxial strain in such device exhibits less impact on the device reliability.

Therefore, this strained SiC device is similar to the SiGe S/D device in terms of the I_D-RTN characteristics. As a result, the CESL strain can induce more scattering effect that would contribute to a non-negligible amount of extra device degradation.

In summary, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been justified by the I_D-RTN technique. By utilizing the approach, the ID-RTN slow oxide trap produced by the HC stress can be measured in both strained n- and p-MOSFETs. The extra degradation coming from the

stress of CESL device shows a significant amount of the mobility as well as the drain current degradation by the vertical strain. This method also provides a way to measure the slow traps that charge pumping can not achieve (i.e., charge pumping can measure the fast trap only.)

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Yang, E. Harley, A. Chakravarti, T. Kanarsky, R. Pal, I. Lauer, D. G.. Park, and D. Sadana, “On Implementation of Embedded Phosphorus-Doped SiC Stressors in SOI nMOSFETs,” in VLSI Symp. Tech. Dig., pp. 172-173, 2008.

Chapter 6

[6.1] M. H. Lin, E. R. Hsieh, S. S. Chung, C. H. Tsai, P. W. Liu, Y. H. Lin, C. T. Tsai, and G. H. Ma, “A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement,” in VLSI Symp. Tech. Dig., pp. 52-53, 2009.

在文檔中 隨機電報訊號量測法應用於前瞻CMOS元件應變技術引致的汲極電流不穩定性之研究 (頁 48-0)