Chapter III Design Theories of Two Stages Power Amplifier 21
3.3 The Design of Output Power Combiner
Typically, the operation of a passive transformer is based upon the mutual inductance between two or more conductors, or windings. By magnetically coupling two inductors, we can create a simple coupling transformer and equivalent circuit model shown in figure 3-9.
Figure3-9 transformer equivalent model (a) Low frequency model (b) High frequency model [18]
By using transformer, we can try to improve the quality factor of inductor to make the performance better. There are many variable topologies of transformer; it makes circuit design more creative by using monolithic transformer. There are also some special transformer feedback techniques applying in novelty circuit.
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= =
Eq.3-7The parameter of Lp and Ls are self-inductances of the primary and secondary loops. The strength of the magnetic coupling between windings is indicated by the k factor, as
k=
Eq.3-8M is the mutual inductance between the primary and secondary windings. The self-inductance of a given winding is the inductance measured at the transformer terminals when all other windings are open circuited [18].
Figure 3-10 schematic of the cascade PA with a 1: N transformer The magnetic-coupled transformer shown in figure 3-10 can be modeled with equivalent series resistors, Rp and Rs, and the equivalent net inductance, Lp and Ls. Take into the equivalent net inductance, Lp and Ls,
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⎟ )
from the primary and secondary winding. Take into the effect of the induced voltage through mutual coupling and neglect the equivalent series resistance, from the KVL can write the matrix from as
Eq.3-9
The Zin is the input resistance and Rload is the output resistance, which is typically 50-Ω. From the Eq.3-10 and Eq.3-11, the input impedance of the transformer is given by
2 2
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If the magnetic coupling between windings is less leakage of the magnetic flux, and we can write Eq. 3-16 as
Eq.3-11 shows the correlation between the magnetic coupling and the self-inductance of the primary and secondary windings. We can try to use the relationship Eq.3-16 described to do the output matching. The turn ratio N of the transformer is the parameter that we have to design to match the optimum impedance to the load 50-Ω.
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Chapter IV
Simulation and Measurement Results
4.1 Proposed Design
As we mentioned at Chapter 3.2, the way of improving adaptive body bias is to modulate the quiescent current. It depends on the required output power, or the unnecessary DC power consumption will reduced the power efficiency.
BJT can use the method of adjusting the adaptive bias circuit to modulate the power cells’ base current and change the power cells’
collector current. The only way of changing CMOS transistor is by changing the bias point. So that we try to adjust the body-bias as changing the bias point. As we can see from the Eq.4-1, the threshold voltage increase when the body bias connect to negative bias voltage, therefore the quiescent current will lower down.
Eq.4-1 In order to sense the different amplitude of input power and change the quiescent current of power amplifier. Rectifier is a way that we usually come up with to modulate the AC signal to DC bias.
Figure 4-1(a) (b) are a conventional voltage doubler rectifier with positive and negative input and the node voltages are marked.
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Figure 4-1 (a) conventional voltage doubler rectifier with negative phase input
Figure 4-1 (b) conventional voltage doubler rectifier with positive phase input
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Since the conventional voltage doubler rectifier has 2Vth drop that decrease the efficiency of the rectifier. Therefore the floating gate voltage doubler which I implemented in this design can compensate the threshold voltage drop. The gate of the diode-tied transistor and the gate of the MOS capacitor are connected together to form a high-impedance node to trap charges in the floating gate. The charge in the floating gate is therefore fixed which results in a fixed voltage bias across the MOS capacitor. The charges that are trapped inside the floating gate device act as a gate-source bias to passively reduce the effective threshold voltage of the transistor [19].
Figure 4-2 floating gate voltage doubler rectifier [19]
The input signal change into positive voltage as figure 4-3 and it should be change to negative voltage. Therefore, the negative voltage should add a voltage divider and change the voltage from positive to negative. We implement a NMOS as a voltage divider and bypass capacitor to stable the voltage.
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Figure 4-3 the voltage wave form after signal transform by floating gate voltage doubler rectifier
Figure 4-4 shows the voltage waveform modulate by NMOS voltage divider which is very stable when transistor operate at active region with large Ron and the waveform is going to tremble when the transistor operate in triode region.
-0.5
Figure 4-4 the voltage waveform modulate by NMOS voltage divider
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4.2 Output Impedance Matching Network
We have introduced the output impedance matching network at chapter 3.3. The transformer structure was shown as figure 4-5. In order to increase the ability of enduring high current, I try to parallel the primary coil. Besides, using sidewall coupling the coupling factor can’t reach that high value which is only about 0.5~0.6. Therefore, I try to overlap primary and secondary coils to increase coupling factor and figure 4-6 displayed the coupling factor increased successfully.
Figure 4-5 transformer structure
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1 2 3 4 5 6
0 7
0.75 0.80 0.85 0.90
0.70 0.95
freq, GHz
K
m1 m1
freq=
K=0.872
5.300GHz
Figure 4-6 transformer coupling factor
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4.3 Simulation Result of Overall Circuit
Figure 4-7 is the proposed power amplifier structure, and it can be separated into two stages. The drive amplifier of the first stage is very important to linearity and gain, the power amplifier of the second stage decides how much power that a PA can transmit.
Figure 4-7 proposed power amplifier
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Figure 4-8 pre-simulation gain
Figure 4-9 pre-simulation transducer gain and output power
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Figure 4-10 pre-simulation PAE
2 4 6 8
Figure 4-11 post-simulation gain
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Figure 4-12 post-simulation transducer gain and output power
-15 -10 -5 0 5 10
Figure 4-13 post-simulation PAE
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Table 4.1 the comparisons with others literatures Ref process Freq
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4.4 Measurement Results
Because of the measurement environment can not set differential signal directly and the loss of the balun is too large that can not be ignored, the S parameter can not measure under this condition. Therefore, I can not get the S parameter measurement results and only received power spectrum picture.
Figure 4-14 Layout
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Figure 4-15 Microphotograph
Figure 4-16 Power Spectrum
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Figure 4-17 Measured Output power and transducer gain
Figure 4-18 Measured PAE
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ChapterⅤ
Design Flow
5.1 Design Flow
The simulation software ADS designer is used to design the circuit.
ADS momentum is used to do EM simulation. After the layout of circuit is finished, DRC & LVS & LPE is done to check the correction for the design.
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ChapterⅥ
Future Work
6.1 Conclusion and Summary
Although the designed two-stage CMOS class-AB power amplifier exhibits good linearity and maximum efficiency, it still suffers serious efficiency degradation when operated at low output power levels.
Therefore, detect the input power level to lower down unnecessary DC power waste can improve the power added efficiency. Sensing the input power by rectifier and using NMOS voltage divider to change positive DC level to negative DC level to control the body bias and then achieve the target of enhancing PAE.
6.2 Future Works
Comparing with pre-simulation that we can find the post-simulation performance decreased a lot. Because of power amplifier has to parallel a lot of transistors to transfer high enough output power and that would increase the difficulty of layout and so does the long connecting metal line will give rise to the extra parasitic RLC decreasing the performance.
This power amplifier performance may improve by doing good ground plane such as ground mesh other than strip line to decrease the inductance.
Using asymmetric device to increase the break down voltage and change differential structure to single ended structure to reduce the loss of non-ideal transformer will probable increase PAE.
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Reference
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[10] Nathan O. Sokal, “Switch mode RF power amplifiers”, 2007.
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[19] Triet Le, Karti Mayaram, Terri Fiez, “Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks” IEEE J. Solid-State Circuits ,Vol.43 ,NO.5 ,pp.287 – 1302, May, 2008.
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Vita
姓 名: 李佳芸 性 別: 女
出生日期: 中華民國七十五年九月二十五日
籍貫: 台灣省 學歷:
台北市立第一女子高級中學(2001/09~2004/06)
國立清華大學工程與系統科學系(2004/09 ~ 2008/06) 國立交通大學電子研究所 (2008/09~2010/07)
論文題目： 高效能高頻功率放大器使用控制電路調整基極 電壓之研究