Output Impedance Matching Network

We have introduced the output impedance matching network at chapter 3.3. The transformer structure was shown as figure 4-5. In order to increase the ability of enduring high current, I try to parallel the primary coil. Besides, using sidewall coupling the coupling factor can’t reach that high value which is only about 0.5~0.6. Therefore, I try to overlap primary and secondary coils to increase coupling factor and figure 4-6 displayed the coupling factor increased successfully.

Figure 4-5 transformer structure

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1 2 3 4 5 6

0 7

0.75 0.80 0.85 0.90

0.70 0.95

freq, GHz

K

m1 m1

freq=

K=0.872

5.300GHz

Figure 4-6 transformer coupling factor

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4.3 Simulation Result of Overall Circuit 

Figure 4-7 is the proposed power amplifier structure, and it can be separated into two stages. The drive amplifier of the first stage is very important to linearity and gain, the power amplifier of the second stage decides how much power that a PA can transmit.

Figure 4-7 proposed power amplifier

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Figure 4-8 pre-simulation gain

Figure 4-9 pre-simulation transducer gain and output power

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Figure 4-10 pre-simulation PAE

2 4 6 8

Figure 4-11 post-simulation gain

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Figure 4-12 post-simulation transducer gain and output power

-15 -10 -5 0 5 10

Figure 4-13 post-simulation PAE

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Table 4.1 the comparisons with others literatures Ref process Freq

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4.4 Measurement Results 

Because of the measurement environment can not set differential signal directly and the loss of the balun is too large that can not be ignored, the S parameter can not measure under this condition. Therefore, I can not get the S parameter measurement results and only received power spectrum picture.

Figure 4-14 Layout

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Figure 4-15 Microphotograph

Figure 4-16 Power Spectrum

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Figure 4-17 Measured Output power and transducer gain

Figure 4-18 Measured PAE

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ChapterⅤ   

Design Flow

5.1 Design Flow 

The simulation software ADS designer is used to design the circuit.

ADS momentum is used to do EM simulation. After the layout of circuit is finished, DRC & LVS & LPE is done to check the correction for the design.

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ChapterⅥ 

Future Work

6.1 Conclusion and Summary

Although the designed two-stage CMOS class-AB power amplifier exhibits good linearity and maximum efficiency, it still suffers serious efficiency degradation when operated at low output power levels.

Therefore, detect the input power level to lower down unnecessary DC power waste can improve the power added efficiency. Sensing the input power by rectifier and using NMOS voltage divider to change positive DC level to negative DC level to control the body bias and then achieve the target of enhancing PAE.

6.2 Future Works

Comparing with pre-simulation that we can find the post-simulation performance decreased a lot. Because of power amplifier has to parallel a lot of transistors to transfer high enough output power and that would increase the difficulty of layout and so does the long connecting metal line will give rise to the extra parasitic RLC decreasing the performance.

This power amplifier performance may improve by doing good ground plane such as ground mesh other than strip line to decrease the inductance.

Using asymmetric device to increase the break down voltage and change differential structure to single ended structure to reduce the loss of non-ideal transformer will probable increase PAE.

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Reference

[1]Yongwang Ding, Harjani Ramesh, “ A High-Efficiency CMOS +22-dBm Linear Power Amplifier” IEEE J. Solid-State Circuits, Vol. 40, NO. 9, pp.1895–1900, Sep ,2005.

[2] Jihwan Kim, Hyungwook Kim, Youngchang Yoon, Kyu Hwan An, Woonyun Kim, Chang-Ho Lee, Kornegay, Kevin T., Laskar, Joy, “A discrete resizing and concurrent power combining structure for linear CMOS power amplifier”IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp.387 - 390 , 2010.

[3] Chao Lu, Anh-Vu H. Pham., Michael Shaw, ”Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation” Microwave Theory and Techniques, IEEE Transactions, Vol. 55, NO.11, pp.2320 – 2328, Nov,2007.

[4] Gang Liu, Tsu-Jae King Liu, Ali M. Niknejad, “A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement” IEEE Custom Intergrated Circuits Conference (CICC), pp.141-144, 2006.

[5] Cheng-Chi Yen; Huey-Ru Chuang“A 0.25-m 20-dBm 2.4-GHz CMOS Power Amplifier with an Integrated Diode Linearizer” Microwave and Wireless Components Letters, IEEE Vol.13, NO.2, pp.45 – 47, Feb, 2003.

[6] Behzad Razzavi, “RF Microelectronics”, 1988.

[7] Frederick H. Raab, Peter Asbecj, Steve Cripps, “RF and Microwave Power Amplifier and Transmitter Technologies” High Frequency Electronics, from May 2003.

[8] Steve Cripps, “RF power amplifiers for wireless communications”, 1999.

[9] Steve Cripps, “Advanced techniques in RF power amplifier design”, 2002.

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[10] Nathan O. Sokal, “Switch mode RF power amplifiers”, 2007.

[11] Sanggeun Jeon and David B. Rutledge, “A 2.7-kW, 29-MHz Class-E/Fodd Amplifier with a Distributed Active Transformer” IEEE MTT-S Int. Microwave Symp., Long Beach, pp.1927-1930, June, 2005.

[12] Gray-Myer “Analysis and Design of Analog Integrated Circuits”, 2001.

[13] T. Sowalti and D. Leenaerts,“A 2.4 GHz 0.18um CMOS Self-Biased Cascode Power Amplifier with 23 dBm Output Power” ISSCC Dig. Tech. Papers, PP.294-295, Feb., 2002

[14] 張盛富、張嘉展“無線通訊射頻晶片模組設計－射頻系統篇＂ 全華科技，

2009年03月

[15] B Sahu, GA Rincon-Mora, “A high-efficiency linear RF power amplifier with a power-tracking dynamically adaptive buck-boost supply” IEEE transactions on microwave and techniques,Vol.52, NO.1, pp.114-120 , Jan, 2004.

[16] Gang Liu, Peter Haldi, Tsu-Jae King Liu, Ali M. Niknejad, “ Fully integrated CMOS power amplifier with efficiency enhancement at power back-off” IEEE J.

Solid State Circuits, Vol.43, NO.3, pp.600-609, Mar, 2008.

[17] Y.S. Noh, Chul S. Park, “An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications” IEEE J. Solid-State Circuits, Vol.39, NO.6,pp.967-970, June, 2004

[18] John. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J.

Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.

[19] Triet Le, Karti Mayaram, Terri Fiez, “Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks” IEEE J. Solid-State Circuits ,Vol.43 ,NO.5 ,pp.287 – 1302, May, 2008.

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Vita 

姓 名: 李佳芸 性 別: 女

出生日期: 中華民國七十五年九月二十五日

籍貫: 台灣省 學歷:

台北市立第一女子高級中學(2001/09~2004/06)

國立清華大學工程與系統科學系(2004/09 ~ 2008/06) 國立交通大學電子研究所 (2008/09~2010/07)

論文題目： 高效能高頻功率放大器使用控制電路調整基極 電壓之研究