Chapter II Research Content and Methods 5
2.4 General Technique for Power Amplifier Design
2.4.2 Cascode Structure
The cascade topology is generally used in amplifiers with differential structure. This structure successfully enhances the output resistance comparing to single-transistor gain stage. Besides, the cascode configuration also reduces the impact of Miller effect and enhances the isolation of amplifier that makes impedance matching getting easier.
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Figure 2-6 The cascode structure
In other words, there is no direct connection between the output node and the input node. This is extremely beneficial in the design of a power amplifier, as the impact of oxide breakdown is greatly reduced. If the bias of the gate of the cascode device is set appropriately, the maximum stress on the oxide of the cascode device is
V
ox(max) =V
out(max) −VG
upper Eq.2-8 The VGupper is the bias voltage on the gate of the cascode upper device.In the case of the single device stage, the maximum oxide stress is
V
ox(max)= V
out(max)− V
IN(max) Eq.2-9 This places a severe limitation on the available output voltage swing.In the case of the cascode structure, the oxide stress on the lower device is now limited to
V
ox= VD
below− V
IN Eq.2-1020
That may cause some problems, depending on the voltage excursion of the cascode node voltage. As stated earlier, the maximum stress on the oxide occurs when the input voltage and the drain voltage getting
maximum value.
The cascode node voltage achieves its’ maximum value when the minimum of input signal provided and the transistors shut off. There is no current flow into upper device so does the lower device has no charging to the drain capacitance. Therefore, the maximum voltage on the cascode node will be limited to
VD
below(max)= VG
upper− Vt
Eq.2-11 The maximum voltage stress across the oxide of the lower device is
V
ox(max)= V G
upper− − V
tV
in(min) Eq.2-12 That is a much more reasonable limit than in the single-ended case.The maximum output voltage is now increased to
V
out(max)= VG
upper+ V
ox(max) Eq.2-13 Where Vox(max) is the maximum voltage the oxide can sustain without damaging the oxide. It is apparent that the maximizing the bias voltage of the cascode device will allow for the cascade device will allow for the largest possible output swing, reducing the amount of current that needs to be drawn from the supply in order to deliver required output power, which can lower down the current inducing hot effect. Furthermore, the smaller the sizes of the output devices, the lesser the pre-amplification stages must provide in order to deliver the required output power [13].21
Chapter
III
Design Theories of Two Stages Power Amplifier
3.1 The Concept of Power Amplifier Circuit Design
For power amplifier circuit design, given the required output power and linearity requirement, therefore the transistors are sized to provide the necessary load gain. Load-line theorem can be used to approximately estimating the optimum impedance and transistor sizes. Parallel enough fingers of transistors to achieve the power goal.
Figure 3-1 load-line diagram
The cascode structure we have introduced in chapter 2.4.2 can provide about double value of VDS will not changing the optimum load impedance because of the upper transistor is nothing but a source follower. In this reason the load line should not become flat by enhancing the maximum sustain voltage.
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The stability is also a very important issue to power amplifier, when the transistor numbers are large to offer enough current and get enough output power, the gate resistance is lower down and the input impedance will easy to become negative and lead to oscillate. The stability factor should larger than one and so does the mu factor to make sure the power amplifier is stable. Usually, we will add an RC parallel circuit or using source degeneration method to improve the stability.
In order to transducer the max output power for two stage power amplifier adding a matching network to do the conjugate matching between the load resistance and second stage optimum impedance is necessary. The inter-stage matching has the same situation doing conjugate matching between the second stage input impedance and first stage optimum impedance. In order to avoiding dc disturbance between two stages therefore the inter-stage matching is adopted by T model.
Figure 3-2 two stage power amplifier with inter-stage matching Apparently, for decreasing the input reflection the impedance
matching network between source load and first stage input impedance is also required, the lesser coefficient of S11 the smaller loss when input
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signal transmit to the main circuit.
3.2 The Concept of Power Amplifier PAE Enhancement at Power Backoff
The saturation power is a very important index in power amplifier, the larger the saturation power the farer communication distance it provided.
However, one inherent problem of power amplifier is that conventional PA designs achieve maximum efficiency only at a single power level, around the peak output power. As the power is back off from the peak, the efficiency drops sharply. The need of conserving battery power and to mitigate interference to other users necessitates the transmission of power levels well below the peak output power.
Transmitters only use peak output power when absolutely necessary.
Figure 3-3 probability curves for transmit power level in urban and suburban environment (IS-95CDMA) [15]
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Dynamic Load Modulation is an attractive approach to enhance the efficiency that we can see from figure 3-4. At the peak power, every individual amplifier is on. Now the load, output swing of each active amplifier and RF power seen by each amplifier is:
R
LEq.3-1
V
output=A V
input=gm R
LEq.3-2
P
peak=N P
unit_peak=4=8
Eq.3-3Figure 3-4 conceptual diagram of transformer based power combining amplifier at peak power mode [16]
As peak output is not need, input drive is reduced to lower output power. When power is 2.5dB back off, input swing reduced to 3/4 Vi. As
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a result, the output swing of each individual amplifier is 3/4 Vo. Therefore, the efficiency of each amplifier as well as that of the power combined amplifier drop rapidly. However, if one amplifier is turned off, efficiency could be greatly enhanced. When the operating power amplifier numbers drop to three then the load, output swing of each active amplifier and RF power seen by each amplifier is:
R
LEq.3-4
V
output=A V
input=gm R
LEq.3-5
P
out=N P
unit_peak=3=
Eq.3-6Figure 3-5 conceptual diagram of transformer based power combining amplifier at power back-off mode [16]
As shown in figure 3-5, the input signal can reduced from 2.5dB,
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6dB to12dB power back off that turn off one to three power amplifier individually. And the proposing structure greatly enhanced the efficiency as figure 3-6 shown.
Figure 3-6 comparison of efficiency between the PA based on proposed power combining transformer and the conventional PA.
[16]
The idea of adaptively biased power amplifier is to change the device’s operating point and improve the power added efficiency.
Traditional Class AB power amplifier is difficult to exhibit high efficiency at the low output power level and high linearity at the high output power level. The adaptive bias power amplifier tries to lower down the quiescent current at the low output power level whereas to increase the quiescent current at the output power level.
Figure 3-7 shows the adaptive bias control circuit. Transistor HBT2 will sense the input power and the collector currents increase with the
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function of the input power. Therefore, the collector current increases so that base voltage of the HBT3 decreased. Then, the decreased IC3
increases the base voltage of the HBT4 such that the emitter current of IE4 decreased and the collector current of HBT1 to decrease. Thus, the quiescent current is a function of input power.
Figure 3-7 schematic diagram of the adaptive bias control circuit [17]
As we can see from the figure 3-8, the gain is 6.5dB for the low output power and increases to12.3dB at the output power of 24dBm. The power added efficiency is higher than fix bias mode during the output power -3dBm to 17dBm.
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Figure 3-8 measured gain and power-added efficiency of the power amplifier with the adaptive bias and the fixed bias circuit [17]
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3.3The Design of Output Power Combiner
Typically, the operation of a passive transformer is based upon the mutual inductance between two or more conductors, or windings. By magnetically coupling two inductors, we can create a simple coupling transformer and equivalent circuit model shown in figure 3-9.
Figure3-9 transformer equivalent model (a) Low frequency model (b) High frequency model [18]
By using transformer, we can try to improve the quality factor of inductor to make the performance better. There are many variable topologies of transformer; it makes circuit design more creative by using monolithic transformer. There are also some special transformer feedback techniques applying in novelty circuit.
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= =
Eq.3-7The parameter of Lp and Ls are self-inductances of the primary and secondary loops. The strength of the magnetic coupling between windings is indicated by the k factor, as
k=
Eq.3-8M is the mutual inductance between the primary and secondary windings. The self-inductance of a given winding is the inductance measured at the transformer terminals when all other windings are open circuited [18].
Figure 3-10 schematic of the cascade PA with a 1: N transformer The magnetic-coupled transformer shown in figure 3-10 can be modeled with equivalent series resistors, Rp and Rs, and the equivalent net inductance, Lp and Ls. Take into the equivalent net inductance, Lp and Ls,
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⎟ )
from the primary and secondary winding. Take into the effect of the induced voltage through mutual coupling and neglect the equivalent series resistance, from the KVL can write the matrix from as
Eq.3-9
The Zin is the input resistance and Rload is the output resistance, which is typically 50-Ω. From the Eq.3-10 and Eq.3-11, the input impedance of the transformer is given by
2 2
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If the magnetic coupling between windings is less leakage of the magnetic flux, and we can write Eq. 3-16 as
Eq.3-11 shows the correlation between the magnetic coupling and the self-inductance of the primary and secondary windings. We can try to use the relationship Eq.3-16 described to do the output matching. The turn ratio N of the transformer is the parameter that we have to design to match the optimum impedance to the load 50-Ω.
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Chapter IV
Simulation and Measurement Results
4.1 Proposed Design
As we mentioned at Chapter 3.2, the way of improving adaptive body bias is to modulate the quiescent current. It depends on the required output power, or the unnecessary DC power consumption will reduced the power efficiency.
BJT can use the method of adjusting the adaptive bias circuit to modulate the power cells’ base current and change the power cells’
collector current. The only way of changing CMOS transistor is by changing the bias point. So that we try to adjust the body-bias as changing the bias point. As we can see from the Eq.4-1, the threshold voltage increase when the body bias connect to negative bias voltage, therefore the quiescent current will lower down.
Eq.4-1 In order to sense the different amplitude of input power and change the quiescent current of power amplifier. Rectifier is a way that we usually come up with to modulate the AC signal to DC bias.
Figure 4-1(a) (b) are a conventional voltage doubler rectifier with positive and negative input and the node voltages are marked.
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Figure 4-1 (a) conventional voltage doubler rectifier with negative phase input
Figure 4-1 (b) conventional voltage doubler rectifier with positive phase input
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Since the conventional voltage doubler rectifier has 2Vth drop that decrease the efficiency of the rectifier. Therefore the floating gate voltage doubler which I implemented in this design can compensate the threshold voltage drop. The gate of the diode-tied transistor and the gate of the MOS capacitor are connected together to form a high-impedance node to trap charges in the floating gate. The charge in the floating gate is therefore fixed which results in a fixed voltage bias across the MOS capacitor. The charges that are trapped inside the floating gate device act as a gate-source bias to passively reduce the effective threshold voltage of the transistor [19].
Figure 4-2 floating gate voltage doubler rectifier [19]
The input signal change into positive voltage as figure 4-3 and it should be change to negative voltage. Therefore, the negative voltage should add a voltage divider and change the voltage from positive to negative. We implement a NMOS as a voltage divider and bypass capacitor to stable the voltage.
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Figure 4-3 the voltage wave form after signal transform by floating gate voltage doubler rectifier
Figure 4-4 shows the voltage waveform modulate by NMOS voltage divider which is very stable when transistor operate at active region with large Ron and the waveform is going to tremble when the transistor operate in triode region.
-0.5
Figure 4-4 the voltage waveform modulate by NMOS voltage divider
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4.2 Output Impedance Matching Network
We have introduced the output impedance matching network at chapter 3.3. The transformer structure was shown as figure 4-5. In order to increase the ability of enduring high current, I try to parallel the primary coil. Besides, using sidewall coupling the coupling factor can’t reach that high value which is only about 0.5~0.6. Therefore, I try to overlap primary and secondary coils to increase coupling factor and figure 4-6 displayed the coupling factor increased successfully.
Figure 4-5 transformer structure
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1 2 3 4 5 6
0 7
0.75 0.80 0.85 0.90
0.70 0.95
freq, GHz
K
m1 m1
freq=
K=0.872
5.300GHz
Figure 4-6 transformer coupling factor
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4.3 Simulation Result of Overall Circuit
Figure 4-7 is the proposed power amplifier structure, and it can be separated into two stages. The drive amplifier of the first stage is very important to linearity and gain, the power amplifier of the second stage decides how much power that a PA can transmit.
Figure 4-7 proposed power amplifier
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Figure 4-8 pre-simulation gain
Figure 4-9 pre-simulation transducer gain and output power
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Figure 4-10 pre-simulation PAE
2 4 6 8
Figure 4-11 post-simulation gain
42
Figure 4-12 post-simulation transducer gain and output power
-15 -10 -5 0 5 10
Figure 4-13 post-simulation PAE
43
Table 4.1 the comparisons with others literatures Ref process Freq
44
4.4 Measurement Results
Because of the measurement environment can not set differential signal directly and the loss of the balun is too large that can not be ignored, the S parameter can not measure under this condition. Therefore, I can not get the S parameter measurement results and only received power spectrum picture.
Figure 4-14 Layout
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Figure 4-15 Microphotograph
Figure 4-16 Power Spectrum
46
Figure 4-17 Measured Output power and transducer gain
Figure 4-18 Measured PAE
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ChapterⅤ
Design Flow
5.1 Design Flow
The simulation software ADS designer is used to design the circuit.
ADS momentum is used to do EM simulation. After the layout of circuit is finished, DRC & LVS & LPE is done to check the correction for the design.
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ChapterⅥ
Future Work
6.1 Conclusion and Summary
Although the designed two-stage CMOS class-AB power amplifier exhibits good linearity and maximum efficiency, it still suffers serious efficiency degradation when operated at low output power levels.
Therefore, detect the input power level to lower down unnecessary DC power waste can improve the power added efficiency. Sensing the input power by rectifier and using NMOS voltage divider to change positive DC level to negative DC level to control the body bias and then achieve the target of enhancing PAE.
6.2 Future Works
Comparing with pre-simulation that we can find the post-simulation performance decreased a lot. Because of power amplifier has to parallel a lot of transistors to transfer high enough output power and that would increase the difficulty of layout and so does the long connecting metal line will give rise to the extra parasitic RLC decreasing the performance.
This power amplifier performance may improve by doing good ground plane such as ground mesh other than strip line to decrease the inductance.
Using asymmetric device to increase the break down voltage and change differential structure to single ended structure to reduce the loss of non-ideal transformer will probable increase PAE.
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Reference
[1]Yongwang Ding, Harjani Ramesh, “ A High-Efficiency CMOS +22-dBm Linear Power Amplifier” IEEE J. Solid-State Circuits, Vol. 40, NO. 9, pp.1895–1900, Sep ,2005.
[2] Jihwan Kim, Hyungwook Kim, Youngchang Yoon, Kyu Hwan An, Woonyun Kim, Chang-Ho Lee, Kornegay, Kevin T., Laskar, Joy, “A discrete resizing and concurrent power combining structure for linear CMOS power amplifier”IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp.387 - 390 , 2010.
[3] Chao Lu, Anh-Vu H. Pham., Michael Shaw, ”Linearization of CMOS Broadband Power Amplifiers Through Combined Multigated Transistors and Capacitance Compensation” Microwave Theory and Techniques, IEEE Transactions, Vol. 55, NO.11, pp.2320 – 2328, Nov,2007.
[4] Gang Liu, Tsu-Jae King Liu, Ali M. Niknejad, “A 1.2V, 2.4GHz Fully Integrated Linear CMOS Power Amplifier with Efficiency Enhancement” IEEE Custom Intergrated Circuits Conference (CICC), pp.141-144, 2006.
[5] Cheng-Chi Yen; Huey-Ru Chuang“A 0.25-m 20-dBm 2.4-GHz CMOS Power Amplifier with an Integrated Diode Linearizer” Microwave and Wireless Components Letters, IEEE Vol.13, NO.2, pp.45 – 47, Feb, 2003.
[6] Behzad Razzavi, “RF Microelectronics”, 1988.
[7] Frederick H. Raab, Peter Asbecj, Steve Cripps, “RF and Microwave Power Amplifier and Transmitter Technologies” High Frequency Electronics, from May 2003.
[8] Steve Cripps, “RF power amplifiers for wireless communications”, 1999.
[9] Steve Cripps, “Advanced techniques in RF power amplifier design”, 2002.
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[10] Nathan O. Sokal, “Switch mode RF power amplifiers”, 2007.
[11] Sanggeun Jeon and David B. Rutledge, “A 2.7-kW, 29-MHz Class-E/Fodd Amplifier with a Distributed Active Transformer” IEEE MTT-S Int. Microwave Symp., Long Beach, pp.1927-1930, June, 2005.
[12] Gray-Myer “Analysis and Design of Analog Integrated Circuits”, 2001.
[13] T. Sowalti and D. Leenaerts,“A 2.4 GHz 0.18um CMOS Self-Biased Cascode Power Amplifier with 23 dBm Output Power” ISSCC Dig. Tech. Papers, PP.294-295, Feb., 2002
[14] 張盛富、張嘉展“無線通訊射頻晶片模組設計－射頻系統篇＂ 全華科技，
2009年03月
[15] B Sahu, GA Rincon-Mora, “A high-efficiency linear RF power amplifier with a power-tracking dynamically adaptive buck-boost supply” IEEE transactions on microwave and techniques,Vol.52, NO.1, pp.114-120 , Jan, 2004.
[16] Gang Liu, Peter Haldi, Tsu-Jae King Liu, Ali M. Niknejad, “ Fully integrated CMOS power amplifier with efficiency enhancement at power back-off” IEEE J.
Solid State Circuits, Vol.43, NO.3, pp.600-609, Mar, 2008.
[17] Y.S. Noh, Chul S. Park, “An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications” IEEE J. Solid-State Circuits, Vol.39, NO.6,pp.967-970, June, 2004
[18] John. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J.
Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sep. 2000.
[19] Triet Le, Karti Mayaram, Terri Fiez, “Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks” IEEE J. Solid-State Circuits ,Vol.43 ,NO.5 ,pp.287 – 1302, May, 2008.
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Vita
姓 名: 李佳芸 性 別: 女
出生日期: 中華民國七十五年九月二十五日
籍貫: 台灣省 學歷:
台北市立第一女子高級中學(2001/09~2004/06)
國立清華大學工程與系統科學系(2004/09 ~ 2008/06) 國立交通大學電子研究所 (2008/09~2010/07)
論文題目： 高效能高頻功率放大器使用控制電路調整基極 電壓之研究