CMOS Transconductance

1.3 CMOS Limitation 

Although CMOS is widely use and many RF blocks can also have good performance. There are still have some blocks operate in a better efficiency by using Ⅲ-Ⅴprocess and power amplifier is one of them.

The reasons of CMOS aren’t suit for making PAs are the following.

1.3.1 Breakdown Voltage in CMOS Process 

In recently, process scaling is the trend of integrated circuit that can improve transconductance and increase fT. However, process scaling will lead to the electric field in the oxide become more significant and the critical field that could induce oxide breakdown as an insulator.

The electric field in the oxide is related to the voltage across the oxide by the thickness of the oxide and the relationship equation as

ox ox

ox

V

E

⁼

t

Eq.1-1 Therefore, in order to keep the electric field in the oxide below the critical field, the voltage difference voltage across the oxide must be kept below the corresponding maximum voltage for the transistors still operate in normal function.

1.3.2 CMOS Transconductance 

The MOS transistors available in the CMOS process are used as thansconductance devices which mean an input voltage signal would generate an output current. In the saturation region for n-type MOSFET, the output current is related to input voltage by

4

ID≅

¹ ( ) (

²

¹

2

^{nCox GS T DS}

W V V V

μ L − + λ )

      Eq.1-2 And the transconductance of CMOS process is

g

m If we neglect the channel length modulation coefficient, the Eq.

can rewrite as

In Bipolar process, and the transconductance is

g

m,BJT The VT is thermal voltage, it’s about 25-mV at the room temperature.

In Eq.1-2, the MOS device is a square law relation with respect to its input signal; drive voltage VGS. Typically, the over-drive voltage is about 200-mV of CMOS process [6].Compare the denominator of Eq.1-4 and Eq.1-5, we can discover that BJT has larger amplification ability than CMOS process.

In order to solve the problem of poor current drive capability, one way is to increase V_GS that is increasing input signal to generate more current. The other way is to enlarge device size for the accommodation of parameter W. However, increasing the amplitude of the input signal will also consume more power in creating the input signal.

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Chapter

 

II 

Research Contents and Methods

2.1 Introduction 

In this chapter, some of background information will be provided both on transmitters and power amplifiers. In order to integrate a linear or non-linear system power amplifier in a transmitter that attempts to satisfy a cellular standard or others specifications, transmitter architecture is amenable to power amplifier integration must be used. High efficiency and good linearity are among the important characteristics of a base station power amplifier used in numerous of the communication applications.

In general, PA can be put into two different types; one is the transistors nominally in its amplifying mode and act as a current sources and the other one is the transistors act as switches. These two types have several different sub-classes, which are used to identify the topology used in a particular implementation.

The several problems relate to CMOS process was introduced in last chapter which include oxide breakdown, poor transconductance and large device sizes. Overall select amplifying-mode classes or parasitic problems with CMOS process will face the issues and cause the efficiency drop down. Therefore, several methods will be introduced to solve the problems in circuit design skills.

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2.2 The Basic Knowledge of Power Amplifier 

Power amplifiers are used in the transmit chain of communication systems; the main purpose is to amplify the signal to the desired power level. The desired power level is determined by the communication system specification. For base-stations used in cellular systems, the magnitude of the transmitted power can be on the order of tens to hundreds of watts. However, the transmitted power of the portable wireless communication devices is often significant less; it will vary from tens to hundred milliwatts and in cordless systems from hundreds of milliwatts to a few watts in cellular system. However, the losses in the transmit medium such as air, it must be high enough such that the amount of power that the receiver is able to sense is adequate to recover the desired signal.

The power amplifier should be able to amplify and transmit signals.

The most common unit is used to described the output power magnitude is dBm which is the output power in dB referenced to 1-mW. That is, the output power in dBm is given by

10log

Where Pout is defined in watts, thus 1-W is equivalent to 30dBm;

and0.1-W is equivalent to 20dBm. The power that needs to deliver to its load should need taken from the source which is the power of the pre-amplifier to output stage amplifier. In the case of portable unit, this will be the battery. In essence, the power amplifier converts the DC power from the battery into radio frequency power delivered to the load.

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Unless the power conversion is lossless otherwise the power amplifier will consume power what it should delivers.

The way to represent how much power is consumed by a power amplifier changing the DC to RF power conversion is known as the PA’s efficiency, given by

Power Delivered to load Power Drawn from Supply efficiency

η

= = Eq.2-2

The power efficiency is one of the key characteristic used to judge a power amplifier’s performance. Because of power amplifiers in portable applications are driven from a source with finite amount of available energy and the higher power efficiency can lead to the longer battery lifetime.

Furthermore, we must know more detail about the final stage Pas, there are variations on the metric that give us more information about the power amplifier. The drain efficiency is defined as

Power Delivered to Load drain efficiency

Power Consumed in Final Stage

ηD = = Eq.2-3

The drain efficiency is the ratio between the radio frequency output power and the DC power consumed. This tells us how efficient the final stage, often referred to as the power stage.

When we inspect the PA implementation more close to real situation, we usually use power added efficiency to describe it. Because of the power need to drive the PA is not only including DC power but also power source. The power deliver to the PA should be taken into account and the efficiency given that

8

PAE=Power Added Efficiency

=

( Power Delivered to Load ) ( Power Delivered to PreAmp )

Power Drawn from Supply

−

^{D (1 1 )}

η ^⋅ G

= − Eq.2-4

The PAE is a more practical measure parameter accounts for the power gain of the amplifier. The power added efficiency which can see from upper formula that must less than drain efficiency except the power gain getting higher. Therefore, if the power gain is not enough than more stages should be added .The power amplifier must deliver a large amount of power to the antenna while consuming a minimum amount of power.

In general, in order to maximize the power added efficiency, the magnitude of the input power should also be quite small. The smaller the size of the input, the less power consumed by the previous stage in providing the required signal drive.

The specification of power amplifier calculated based on the link budget of the entire transceiver. Table 2.1 lists the typical PA performance.

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Table 2.1 lists the typical PA performance. [6]

Output Power +20 to +30 dBm

Efficiency 30% to 60%

IMD -30dBc

Supply Voltage 3.8 to 5.8 V

Gain 20 to 30dB

Output Spurs and Harmonics -50 to70dBc

Power control On-Off or 1-dB Steps

Stability Factor >1

Some of the key specifications in the power amplifier design are its frequency of operation, output power level, power gain, efficiency and power consumption. Traditionally, all the impedance of any RF block is

terminated to 50Ω, especially to aid in the testing. However, sometime it

not only to conform to antenna of typical intrinsic impedance used 50Ω.

Since the load impedance are different and the power gain and voltage gain would not be the same.

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2.3 Different Classes Implementation of Power Amplifier 

Generally speaking, PAs can be separated to two different categories;

one is in its amplifying mode and the other is acting as a switch. The amplifying mode device normally acts as a current source and works as linear class of power amplifier. The switching mode category is referred to as the nonlinear power amplifier. And sometimes, we can use the dc bias condition to classify the linear or nonlinear mode of PAs. In general, RF power amplifiers can be specified as class A, B, C, D, E and F that different kinds of power amplifier classes have different transistors conduct cycle. [7]

The generation of significant power for power amplifiers depends on the standards of wireless communication. Each application has its own requirements for operating frequency, bandwidth, power, efficiency, linearity and cost. Besides, power amplifier is not only a simple linear amplifier which operate in small signal, on the other hand, power amplifier operate in large signal and has different properties comparing to traditional operating amplifier.

The phrase “linear” is just a concept to describe how output signal close to the input signal, as stated earlier, this just identifies the group of PAs in which the device is intended to operate in its amplifying region.

For amplification of amplitude-modulated signals, the quiescent current can be varied in proportion to the instantaneous signal envelope. Since the devices are meant to operate in their amplifying region, it should be apparent that there exist some relationship between the magnitude of

11

input and output, regardless how linear that is. And the relationship between linearity and efficiency are mutual trade off [8] [9]. The linearity is direct proportional to conduct angle which means that the longer the conduction cycle the better linearity a PA has. However, the average power is consumed even when no signal is applied that will lead to lower efficiency.

Figure 2-1 Basic Class-A implementation

The above description describes the group of PAs known as Class-A PAs and the device conducts current for entire input sinusoid cycle. The amplifying device is biased in such a way that it always remains in its amplification region, even under maximum input signal conditions. The bias voltage is set to keep the device still operate in saturation region even when the swing of input signal reaches the maximum the gate

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voltage should over threshold voltage. The output voltage swings around its bias point; in general is the supply voltage, VDD. On the ideal situation, the maximum amplitude of the output swing is just V_DD which can help us determine the peak efficiency of the Class-A configuration. If we consider that

I

^o = average current Eq2-5

And the peak efficiency is given by

As we can see that the peak efficiency of class-A PA is 50%. As a result, class-A PAs are used in applications which require low power, high linearity or high gain.

If the bias condition is going to change and make PAs not always operate in saturation region which introduce the idea of class-B PAs.

Class-B PAs sometimes also called push-pull output stage. In standard implementations, two amplification devices are used and used differential input to maintain the original waveform. Each of the devices has only half sinusoidal period that is to say the conducting angel is only half of the class-A PAs. The efficiency of this implementation is greater than that of the class-A implementation and the theoretical peak efficiency of the class-B PAs is given by

78%

4

η = π =

Eq.2-7

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Figure 2-2 Basic Class-B implementation

Although the efficiency will enhance by using class-B implementation the linearity will degrade at the same time. And sometime if the gain through the devices is not exactly the same, the output will not be smooth sinusoid. Therefore, the issue of mismatch between two devices occurs no matter the parameter of threshold voltage or mobility difference. Crossover distortion is the existences of dead-zone during the devices turn on by turns leading to output signal distortion which also decreasing the linearity.

In order to gain better linearity we should obtain the balance between class-A and class-B configurations and this is the reason of class-AB generation. The power amplifier is now based such that it is on for more than half the cycle. In this case, the problem of dead-zone is avoided because there is a portion when both devices in a push-pull implementation are on [6] [7]. In narrowband RF implementations, class-B and class-AB PAs can also be implemented using a single device adding an RF filter at the output to extract the fundamental frequency

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component of the output waveform. Normally, a single device would induce a problem that the device would be off for part of the input cycle and generate a chopped and thus become extreme distortion of output waveform while the input power is large. However, through the use of narrowband RF filters, the component of the output waveform at the fundamental frequency can be extracted and the amount of distortion can be reduced.

The group of “Nonlinear” PAs is also known by a more descriptive name: waveform shaping-mode or switch mode PAs. For RF PAs, the two classes of switched mode PAs which have received the most attention are class-D and class-E PAs.

Figure 2-3: Class-D implementation

The class-D architecture is similar to what is used in a bridge DC-DC converter [10]. In the style of DC-DC converter, the devices acting as switches change the polarity of the input voltage onto the load

15

and the resulting output is averaged to create an output voltage that is some fraction of the input voltage, depending on the duty cycle of the switching. If the implementation of the switch is assumed to be ideal, then no on-resistance and the output voltage will be zero exactly when the switch is closed the ideal maximum efficiency of the power stage can be 100%, as no power will be consumed in the transistor.

The class-E PA, is also used the idea of soft switching in order to further reduce power consumption by the device in the switched-mode PA. This class of power amplifier has also been recently implemented in a CMOS implementation [11] [7] [10]. Basically, the class-E power amplifier tries to force the voltage on the output node becoming zero voltage at the instant that the switch is closed, so there is ideally no time at the transition when both the output voltage and current are non-zero.

Not only is that but also there is no CV² energy loss from the output capacitance discharging as the switch is turned on. In order to account for timing errors in the switching instants, the slope of the output voltage waveform should also be zero at the instant of that the switch closes.

Because of any timing error when the switch closes, the power consumed attribute to any overlap in the output current and voltage waveforms will be minimal; since the slope of the output voltage at the correct instant is zero, the value of the output voltage at instants close to the output voltage will be very small to improve the drain efficiency. So, an ideal class-E power amplifier consists of a single supply voltage Vdd, an RF choke inductor Ldc, a switch with a parallel capacitor Cp, a resonant circuit Lo-Co, and a load RL, or intrinsic impedance 50-Ω.

16

Figure 2-4: Class-E implementation

And like the class-D PA, the theoretical efficiency of the class-E power amplifier is 100%, again, practical considerations, especially in CMOS limitations, have limited the efficiency to about 50%[11], although GaAs implementation have reached close to 60%

efficiency[10].

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2.4 General Technique for Power Amplifier Design 

There are two useful ways that can apply on power amplifier design.

One way is differential structure and the other way is cascode structure.

These two methods are commonly used to improve the overall performance of CMOS power amplifier.

2.4.1 Differential Structure 

Differential topology can immune the common mode signal and prevent any noise that might exist on the power supply impacting the circuit performance. Differential structure, usually add on the transistors with equal load impedance on both sides of the drain. According to superposition, the gain distributed by common-mode and differential-mode could be separated. And the result of CMRR is significant large.

Figure2-5 the differential structure with the tail current source

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For the common source amplifier which is shown in figure 2-5, due to the large output impedance of the tail current source, the node common to the sources of the two transistors acts like a virtual ground for differential signal and a virtual open-circuit for common-mode circuits [6].

Owing to the low-resistivity substrate, signal may travel through one block to another block elsewhere on the chip [12]. These signals will show up as a common-mode signal on the substrate terminal of the devices in another block. In order to ensure the impact of those signal is reduced, the implementation of all blocks, especially noise that deal with small signals or those that are extremely sensitive should use differential structure. The current tail offers the same magnitude as single-ended implementation thus each side of differential pair receives half of the original current. Under this situation, each side provides half power of the original single-ended implementation. Although the maximum voltage swing doesn’t change the output current become half of the tail current.

Summing the powers of each side delivers the full desired power to the load.

2.4.2 Cascode Structure 

The cascade topology is generally used in amplifiers with differential structure. This structure successfully enhances the output resistance comparing to single-transistor gain stage. Besides, the cascode configuration also reduces the impact of Miller effect and enhances the isolation of amplifier that makes impedance matching getting easier.

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Figure 2-6 The cascode structure

In other words, there is no direct connection between the output node and the input node. This is extremely beneficial in the design of a power amplifier, as the impact of oxide breakdown is greatly reduced. If the bias of the gate of the cascode device is set appropriately, the maximum stress on the oxide of the cascode device is

V

ox(max) ⁼

V

out(max) ⁻

VG

upper Eq.2-8 The VGupper is the bias voltage on the gate of the cascode upper device.

In the case of the single device stage, the maximum oxide stress is

V

^ox(max)

= V

^out(max)

− V

^IN(max) Eq.2-9 This places a severe limitation on the available output voltage swing.

In the case of the cascode structure, the oxide stress on the lower device is now limited to

V

^ox

= VD

^below

− V

^IN Eq.2-10

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That may cause some problems, depending on the voltage excursion of the cascode node voltage. As stated earlier, the maximum stress on the oxide occurs when the input voltage and the drain voltage getting

That may cause some problems, depending on the voltage excursion of the cascode node voltage. As stated earlier, the maximum stress on the oxide occurs when the input voltage and the drain voltage getting

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