Channel Soft Breakdown Enhanced Excess Low-Frequency Noise

The gate length of this section is 0.13µm, the gate width is 10µm and the oxide thickness is 1.6nm. All devices were stressed at high constant gate voltages with the source and drain grounded. The stress was stopped immediately after the first breakdown was detected. The current compliance for breakdown detection was chosen to be 10µA. After breakdown, the device on-state characteristics were checked and no difference was observed. Similarly, from others’ study, [4.17-4.21] the impact of the gate oxide SBD is only a noticeable increase in leakage current without degrading any on-state device performance in operation.

The breakdown position was examined by using the method given in Chapter 3.[4.22]

The measurement gate bias is V_g=-1.5V and V_d=V_s=0V in the accumulation region. A significant increase of I_d/I_s+I_d in device indicates that breakdown is located at the drain edge, while the moderate change in Id/Is+Id implies that SBD position is in the channel. By utilizing the aforementioned technique of examining the breakdown location, the device electrical behaviors before and after various soft breakdown modes could be characterized. In Fig. 4.9, the gate current and substrate current as a function of Vg in fresh, channel-SBD, and edge-SBD n-MOSFETs were compared.

This comparison indicates that the substrate current increased drastically in channel-SBD devices, but the change in edge-SBD devices was negligible. The substrate current at a positive gate bias is attributed to channel hole creation resulting from valence-band electron tunneling from Si substrate to the conduction band of the poly gate. The tunneling process is unlikely to occur in the n⁺ drain region since the valence-band edge of the n⁺ drain is aligned with the band-gap of the n⁺ poly-gate. Thus, these findings support the viewpoint that the post c-SBD Ib is enhanced largely at a positive gate bias due to a localized effective oxide thinning [4.23-4.25] while I_b is nearly unchanged after e-SBD. The results provide direct experimental evidence that channel soft breakdown may induce a substrate leakage current increase in device operation, especially at a high gate bias.

According to the above results, c-SBD enhanced substrate tunneling current in PD SOI MOSFETs is proposed as a new body-charging mode.[4.11,4.26-4.27] To further illustrate this point; the low frequency drain noise spectrums of SOI nMOSFET before and after both SBD modes are shown in Fig. 4.10. The measurement drain bias is 0.1V and the gate bias is 1.2V.

The pre-BD noise characteristics of 1.6 nm gate oxide nMOSFET were dominated by a 1/f-like flicker noise component without other noise component of linear kink effect.[4.28]

Suitable channel engineer process can eliminate the excess floating body noise of SOI device in advanced 0.13µm generation SOI technologies.[4.8,4.10] An additional Lorentizian-like spectrum appears only when both channel soft breakdown occurs and body contact is floated.

As body contact is grounded, the excess noise can be effectively eliminated. The excess noise is also not observable in e-SBD devices. It indicates that the additional body charge injection of c-SBD devices not only enhances the Vt hysteresis effect but also degrades the LF noise spectrum.

Now, we would further investigate the gate bias dependence of the c-SBD induced excess floating body noise. Fig. 4.11 shows the normalized noise spectra of a floating body c-SBD SOI nMOSFETs under different gate biases. We observed a typical Lorentzian shift to lower plateau and higher cut-off frequency due to the valance band electron current increase with the gate bias. At Vg=1.6V, only 1/f noise is observed. In fact, we believe there is still a Lorentzian in this case but shifted to lower frequency, below our measurement capability.

Note that the normalized 1/f noise remains almost constant over measurement gate bias in this ohmic region. This could be associated with the number fluctuation dominated in this measurement.[4.29-4.30] The excess noise of a c-SBD SOI devices with floating body shows similar behaviors to the excess noise induced by the kink effect in section 4.3.

Fig. 4.12 illustrates that for a given frequency, the normalized drain current noise of c-SBD floating body SOI devices initially increases with V_g and reaches a peak when gate bias is 1V. This phenomenon is consistent with other research claiming that the RC network of

the body in floating-body PD SOI nMOSFET’s amplifies and filters the shot noise of substrate current, giving rise to a Lorentzian-like spectral density in noise.[4.6-4.9] It can be explained that with an increase in gate voltage, c-SBD induces more substrate current as a result of valance band electron tunneling. Further increase in gate bias leads to a low amplification gain by the floating-body to the shot noise, because the equivalent substrate resistance decreases with the substrate current increase, thus the noise magnitude decreases.[4.7]

4.5 Summary

The significance of soft breakdown position to the low frequency drain current noise in floating body PD SOI nMOSFETs has been evaluated. The excess floating body noise of nMOSFETs would be enhanced if a breakdown path occurs at the channel. The enhanced noise correlates with channel soft breakdown induced large substrate current of valance band electron tunneling. This noise sources origins from the amplification by small white noise of the substrate current. The c-SBD enhanced excess noise may occur even with supply voltage less than 1.0V and would be a serious reliability concern in ultra-thin oxide analog SOI devices.

Fig.4.9 The gate current and substrate current as a function of Vg in fresh, channel SBD, and edge SBD n-MOSFETs were compared.

0 0.5 1 1.5 2 10 ^-5

10 ^-7

10 ^-9

10 ^-11

Gate bias (volts)

Curren t (Am p ) _fresh

post c-SBD post e-SBD

Gate current

Substrate

current ^V

^=0V

0 0.5 1 1.5 2 10 ^-5

10 ^-7

10 ^-9

10 ^-11

Gate bias (volts)

Curren t (Am p ) _fresh

post c-SBD post e-SBD

Gate current

Substrate

current ^V

^=0V

Fig.4.10 The low frequency drain noise spectrums of n-MOSFET before and after two SBD modes. The measurement drain bias is 0.1V and the gate bias is 1.2V.

10

10

10

10

10

10

Fig.4.11 The normalized noise power spectrum of a c-SBD nMOS SOI device with floating body under different gate biases.

10

10

10

10

10

Fig.4.12 Comparison of normalized noise power spectral density with floating body under different gate bias in a fresh device, c-SBD device and e-SBD device at f=100Hz.