Stress Time (sec.)
5.3 Result and Discussion
5.3.1 A Shorter tfail in SOI pMOSFETs
Fig. 5.2 shows the gate leakage current evolution with stress time at a stress gate voltage of Vg=-2.9V for various applied substrate biases (Vb) in pMOSFETs. The oxide tBD is almost the same for different substrate biases. This can be understood because oxide defect generation rate is dependent on injected charge energy and fluence during stress [5.19-5.22], regardless of applied substrate bias. After the onset of BD, the BD growth rate exhibits an apparent dependence on substrate bias. A forward substrate bias can significantly enhance BD growth rate. It should be noted that the SOI device with floating body configuration has the worst BD progression rate in Fig. 5.2. The statistic Weibull distributions of oxide tBD and tfail for SOI (floating substrate) and bulk (grounding substrate) pMOSFETs are plotted in Fig. 5.3.
Although the floating substrate configuration does not affect tBD, it does cause a 2 times shorter tfail than in bulk pMOSFETs.
5.3.2 Mechanism of Enhanced BD Progression in SOI
The floating body configuration of SOI devices may result in a small forward body voltage due to various body charging processes. In an ultra-thin oxide pMOSFET, the gate stress current may have comparable electron and hole components at a negative gate bias. To analyze the polarity of dominant stress current in a pMOSFET, a charge separation technique is utilized to measure electron stress current and hole stress current. The inset of Fig. 5.4 illustrates the carrier flow at a negative gate bias, Ib denotes electron current and comes from valance-band electron tunneling from the gate electrode. Isd stands for hole tunneling current from the inverted channel. The substrate bias dependence of electron current and hole current before and after tBD is shown in Fig. 5.4. Note that the electron and hole currents in a fresh device are independent of substrate bias. Interestingly, the post-tBD hole current, unlike the pre-BD Ib and Isd, exhibits a significant Vb dependence. Furthermore, Fig. 5.5 reveals that the
Vb dependence of the post-tBD hole current increases with BD evolution. Since the hole stress current dominates gate stress during BD evolution and increases with a forward body bias, the enhanced BD progression in a floating body configuration can be understood.
5.3.3 BD Caused Carrier Heating
Since the post-tBD electron current does not exhibit Vb dependence (Fig. 5.4), the possibility that the Vb dependence of the post-tBD hole current is caused by the variation of effective gate-to-channel voltage resulting from Vb modulated channel resistance can be excluded. Otherwise, the post-tBD Ib should have the same Vb effect as the post-tBD Isd. Moreover, substrate impact ionization and negative bias-temperature instability effects are also excluded because the trend of the Vb dependence is opposite.
To further investigate the origin of the Vb dependence of the post-tBD hole current, we measured the spectral distribution of hot carrier light emission before and after tBD (Fig. 5.6).
The light intensity is greatly increased after oxide BD. The high-energy tail of the post-tBD
spectral distribution indicates the rise of the carrier temperature. Similar finding was also reported by other groups.[5.23] The extracted carrier temperature from the high-energy tail of the spectrum is around 1300 o K (Fig. 5.6(b)). There are two possible theories to explain the rise of channel carrier temperature at a BD spot. First, based on the model proposed by Rasras et al [5.23], the gate voltage may penetrate into the substrate after BD and causes lateral field heating of channel carriers. However, this process is unlikely here since the post-tBD electron current and hole current have distinctly different Vb dependence. The second possible reason is that high-dissipated energy, released by valence electrons tunneling from the gate through the BD path, will locally produce a rise of hole temperature. A temperature range of 1000 o K to 2000 o K was estimated in Ref. [5.24]. Electron-hole scattering or Auger recombination is suspected to be the responsible energy transfer process.
To show that the rise of hole temperature may account for the observed Vb dependence,
we calculate the hole tunneling current with hole temperature at 300oK and 1300oK. In our calculation, we solve the coupled Poisson and Schrodinger equations to obtain the sub-band structure for the inversion holes (Fig. 5.7). A simple one-band effective mass approximation is used for simplicity. The hole tunneling current density is calculated according to the Tsu-Esaki formula [5.25] probability of the n-th sub-band. m* is the hole effective mass in Si. Other variables have their usual definitions. It should be emphasized that it is not our intention to consider detailed trap-assisted charge transport in the BD path. It is also not our intension to calculate the precise current value before and after oxide BD, since the BD area and BD caused effective oxide thinning cannot be easily determined. Instead, our purpose is to investigate the effect of hole temperature on the inversion hole distribution in different sub-bands and the corresponding substrate bias effect on hole tunneling current. Therefore, a simple WKB formula for direct tunneling is employed for Dn.
Our result in Fig. 5.8 clearly shows that the hole tunneling current exhibits a larger Vb
dependence at 1300 o K. The simulation can well interpret the measured Vb dependence of the post-tBD Isd by simply using an elevated hole temperature. The trend in Fig. 5.8 is similar to the measured Vb dependence in Fig. 5.5. To explain the temperature effect on the Vb
dependence in more detail, the distribution of inversion holes in the lowest three sub-bands is given in Table. 5.1. At T=300 o K, channel holes mostly reside in the first sub-band no matter of Vb. At T=1300 o K, a large part of holes are thermally excited to higher sub-bands at a
forward body voltage (-0.5V), where the oxide tunneling probability is larger. Thus, a much larger hole tunneling current is obtained at negative body voltages.
Fig.5.2 Oxide breakdown progression in bulk and SOI pMOSFETs. The stress gate bias is –2.9V and temperature is 125o C.
0 100 200 300 400 500 600 700 0
50 100 150
Gate Current (- µA)
Stress Time (sec.)
SOI V
b=-0.5V V
b=0V t
OX=1.6 nm
Bulk
stress V
g=-2.9V
Fig.5.3 The Weibull plots of tBD and tfail distribution for 1.6nm oxide SOI and bulk pMOSFETs. The stress gate bias is –2.9V and the temperature is 125o C. tBD and tfail are defined as the time for gate current to reach 1.5 times and 15 times its pre-stress value, respectively.