3.1 Introduction
Silicon-on-insulator (SOI) technology has emerged as a promising technology for system-on-a-chip applications, which require high-performance complementary metal-oxide-semiconductor (CMOS) field effect transistors (MOSFETs), low power, embedded memory, and bipolar devices. The primary feature of a MOSFET with SOI configuration is that the local substrate of the device is floating electrically, and thus the substrate-source bias (VBS) is not fixed. As VBS changes, the device threshold voltage (Vt) will change due to the body effect. This “instability” in Vt resulting from floating body configuration becomes one of the most challenging tasks in bringing SOI devices into mainstream applications.[3.1-3.4] One manifestation of the Vt variation is the hysteresis effect.
The Vt hysteresis as a result of various floating body charging/discharging mechanisms has been widely investigated.[3.2-3.4] In this work, the influence of gate oxide breakdown position on hysteresis effects in ultra-thin oxide partially-depleted (PD) SOI MOSFETs will be explored.
Several causes of Vt hysteresis in PD SOI MOSFETs have been proposed.[3.5-3.8]
Boudou et al [3.5] reported that Vt hysteresis could be caused by positive feedback of impact ionization due to long time constants associated with body potential charging. Chen et al [3.6]
showed that at high drain biases the floating body effect can lead to hysteresis in the sub-threshold Ids-Vgs characteristics even when the gate is biased well below its threshold voltage. Fung et al [3.7] found that in ultra thin gate oxide devices the gate-to-body tunneling current modulates the body voltage and induces a hysteresis effect. All the above works investigate the hysteresis phenomenon in PD SOI MOSFETs without considering gate oxide
soft breakdown (SBD). Recent studies [3.9-3.13] showed that in bulk CMOS the impact of gate oxide SBD is only manifested in a noticeable increase in gate leakage current without degrading other device characteristics in operation. Crupi et al [3.14] showed that at high gate voltages the substrate current steeply increases after SBD due to localized effective thinning of gate oxide. Chan et al [3.15] presented that in thinner oxides the post-SBD gate induced drain leakage (GIDL) current increases significantly because of the enhancement of band-to-band tunneling. Although the dependence of these excess substrate currents on the location of a SBD spot was widely explored, the influence of SBD location on Vt hysteresis in SOI devices has been rarely investigated.
3.2 Device Structure and Characterization
The devices in this work were made with a 0.13µm standard CMOS process on p-type PD SOI substrate. The gate oxide was grown with rapid plasma nitridation (RPN) process.
The gate length is 0.13µm, the gate width is 10µm and the oxide thickness is 1.6nm. The test devices have an H-gate structure with an additional contact to facilitate the measurement of the body current and voltage. In this chapter, all devices were stressed at high constant gate voltage with the source and drain grounded. The stress was stopped immediately after the first breakdown was detected. The current compliance for breakdown detection was chosen to be 10µA. After breakdown, the device on-state characteristics were checked and no difference was observed.
The breakdown position was examined by using the method proposed by Degraeve et al.[3.16] Table 3.1 shows the ratio of Id to (Is+Id) before and after SBD in four SOI devices.
The measurement is in accumulation region and |Vg|=1.5V and Vd=Vs=0V. A significant increase of Id/(Is+Id) in device B and device D indicates that breakdown is located at the drain edge, while in device A and device C the moderate change in Id/(Is+Id) implies that the SBD position is in the channel. Aside from Id/(Is+Id), Ib/(Is+Id) was measured (also shown in Table
3.1). In the channel SBD (c-SBD) devices, the valence band tunneling leakage in the channel region (Ib) was enhanced, resulting in a larger Ib/(Is+Id). In the case of edge SBD (e-SBD), the breakdown was above the drain edge. As a result, the tunneling leakage current in the channel region remains almost the same as in pre-SBD, and the increased edge leakage current makes Is+Id larger and thus a smaller Ib/(Is+Id). In short, the results in Table 3.1 shows that we can use the change of Id/(Is+Id) or Ib/(Is+Id) to determine the breakdown location in the channel or in the drain edge region.
By utilizing the above technique, the device electrical behaviors in c-SBD and e-SBD devices were characterized. In Fig. 3.1, the gate current and the substrate current as a function of Vg in a fresh, a c-SBD, and an e-SBD nMOSFET were compared. The result shows that the substrate current increases drastically after c-SBD, but has little change after e-SBD. The substrate current at a positive gate bias is attributed to valence electron tunneling from the channel to the gate. The generated holes left behind in the channel then flow to the substrate.
This tunneling process is unlikely to occur in the n+ drain region since the valence-band edge of the n+ drain is aligned with the band-gap of the n+ poly-gate. Thus, Ib is enhanced significantly at a positive gate bias in a c-SBD device due to localized effective oxide thinning [3.14, 3.17-3.18] while Ib in an e-SBD device is nearly unchanged. Fig. 3.2 shows the drain bias dependence of the GIDL current before and after SBD. The substrate current has an apparent increase after edge SBD. This is because at a high drain bias the Ib comes from electron band-to-band tunneling in the drain depletion region and the generated holes flow to the substrate. Since the electrical field in the drain region becomes stronger after e-SBD due to effectively oxide thinning, the GIDL (Ib) in an e-SBD device is enhanced. The same phenomena in p-MOSFETs are also observed and the result is shown in Fig. 3.3.
Table 3.1 The ratio of Id/(Is+Id) and Ib/(Is+Id) before and after soft breakdown in four SOI MOSFETs. The measurement is in the accumulation region and Vg=
|1.5V|, Vd=Vs=0V.