CMOS Constant Current Reference - -5dBm IIP3 UWB Low Noise Amplifier Using

Chapter 4 -5dBm IIP3 UWB Low Noise Amplifier Using

4.6 CMOS Constant Current Reference

According to the broadband complex transconductance analysis, the MGTR technique can use linearity improvement in broadband condition. Simultaneously, we observe the cancellation effect which is sensitive to the process corners. In various process corners, it makes the variation of voltage and current, so the distortion cancellation effect is affected by the various process corners. Therefore, we need a constant current reference to biasing MT and AT for keeping the cancellation effect, the following discuss will present a CMOS constant current reference designing flow.

In this work, a CMOS constant current reference over process variations is presented as shown in Fig. 4.21. During processing, variations in the process parameters like, tox (gate oxide thickness), Nch (channel doping), and others affect the reference current. Therefore, the core of the proposed technique is a CMOS circuit, which generates the reference current as the drain current of a MOS device. This drain current is kept relatively constant by exploiting the physical relationship between K^’ and VT in process variations.

The drain current of MOS device in saturation region can be expressed as Fig. 4.22 CMOS constant current reference

, (4.36) Due to process variations, K^’ and VT, which affect the drain current. The normalized variation in the drain current can be expressed as

∆ ∆ ∆

, (4.37) K^’ and VT are primarily dependent on two process parameters, tox and Nch, and they can be expressed as

, (4.38)

, (4.39) Across the process corners, K^’ and VT vary due to variations in tox and Nch.In Equation (4.38) and (4.39), an increase in K^’ is accompanied by a decrease in VT when tox

decreases, or vice versa. Therefore, this correlation between K^’ and VT can be interpreted as an inverse relationship between them. At this point, it is important to have some understanding about the modeling process corners in typical CMOS processes.

In Equation (4.37), we assume (Vgs −VT) to be equal to VT. Even though the inverse relationship of K^’with VT causes a wide variation in the drain current, the same inverse relationship can also be used to our benefit if we assume for the moment that the expression of the drain current can be expressed as

, (4.40) In Equation (4.40), assuming Vds(sat) can be kept constant, the variation in the drain can be express as

∆ ∆ ∆

, (4.41) For the process corners, the inverse relationship between K^’ and VT will minimize the variation in the drain current given by Equation (4.41). The variation in

the drain current can be minimized to the order of K^’ variations by choosing a large value of Vds(sat). The following discussion will assume that the inverse relationship of ' K and VT exists across process variations.

In this circuit, there are 3 design parameters: Vgs, α and β. The reference current can be expressed as

, , (4.42) Assuming an ideal NMOS current mirror, the reference current can be modified as

, 2 ^I , (4.43)

, 1 2 2 V_GS , (4.44) In Equation (4.44), Vgs is a constant voltage, α and β are the ratios (W/L) of the PMOS devices. In order for the reference current to be constant across process corners

K 0 , (4.45) Substituting Equation (4.44) in (4.45) gives

′

′ , (4.46) Both sides of Equation (4.46) can be integrated, and by eliminating the constant of integration using the nominal values of K^’p and VTP , we will get

′

′.

. , (4.47)

K^’p,nom , and VTP,nom are the nominal (typical) values of K^’p and VTP in any process variations. Equation (4.47) represents the desired inverse relationship between K^’p and VTP for a constant reference current. For the moment, we can get the optimal ratio of α and β in Equation (4.47). Final, the Vgs of the CMOS constant current reference is 1.3V, the ratio of α and β is 5:12. In the simulations, the variation of the CMOS constant current reference was ±0.8% of its nominal value in process corners.

4.7

Table. 4.1 Measure performance summary

This Work [ 1 ] [ 2 ] [ 3 ] [ 4 ]

Technology 0.18um CMOS

0.18um CMOS

0.13um

CMOS 90nm CMOS

Power Supply 1.5V 1.8V 1.5V 1.2V 1.0V

BW (GHz) 3.1 ~ 10.6 2.3~9.2 3.1 ~ 10.6 3.1 ~ 10.6 3.1~10.6

S11,MAX (dB) <-8 -9.4 -11 -9.9 <-10

S₂₁(dB) 8.1 9.3 11 13.7 7.8~12.3

Noise Figure 7.31dB 8 dB 5.1 dB 3.0dB 2.7~3.3dB Power

(w/o buffer) 8.26 mW 9 mW 9 mW 9 mW 2.5mW IIP3 >-5dBm -16dBm -12dBm -8.5dBm -6.4dBm

S11 (dB)

Fig. 4.24 Measured input impedance matching S11

freq (1.000GHz to 15.00GHz)

S11 (dB)

Fig. 4.25 Measured output impedance matching S22

freq (1.000GHz to 15.00GHz)

S22 (dB)

Fig. 4.28 Measured noise figure 61

2 4 6 8 10 12 14

0 16

-15 -10 -5 0 5 10

-20 15

Frequency (GHz)

Fig. 4.27 Measured power gain S21. Fig. 4.26 Measured S12

4.8 Summary

The proposed broadband simultaneous noise and impedance matching technique is employing dual reactive feedbacks and a high-order input matching network to cover a wide bandwidth.

A low-power high-linearity UWB LNA, intended for use in the receiver path of ultra-wideband wireless system, is designed in standard 0.18um CMOS technology.

The MGTR technique is adopted to improve the linearity of the broadband LNA. A common source equivalent circuit using AC complex transconductance analysis provides broadband linearity improvement, IIP3 contour gives the optimal design parameters. Measured data show that the improvement of the linearity is more than 5 dB in broadband condition.

2 4 6 8 10 12

-12 -10 -8 -6 -4 -2 0

IIP3 (dBm )

Frequency (GHz)

w/i MGTR w/o MGTR

Fig. 4.29 IIP3 measurement of w/i MGTR and w/o MGTR broadband LNA

Chapter 5 A Low Power, High Linearity UWB Receiver for Ultra-Wide Band Wireless System

5.1 Introduction

This chapter is aimed at the low power, high linearity UWB RF front-end circuit in wireless receivers. For the concern of low power consumption, Direct Conversion Receiver is chosen as the system architecture. It provides great possibility of better form factor, lower cost, less power consumption, and high linearity. In this work, a low power, high linearity UWB direct down-conversion front-end circuit is implemented. The front-end circuit includes a low noise amplifier, an active balun, and a direct down-conversion mixer, as shown in Fig. 5.1. The UWB LNA is the same in the chapter 4.

Mixer is an essential part of RF front-end circuits. Double balanced type mixer is better than single-ended one for its better port-to-port isolation and even-order terms rejection. The received signal from the antenna is usually single ended. An active

Fig. 5.1 UWB receiver front-end architecture.

balun is needed to transform the signal from the proceeding stage into a differential form to benefit from the double-balanced structure. To avoid unwanted signal loss, an active balun is usually adopted. However, the active balun contributes limited gain and consumes some power. Therefore, in this work the active balun and transconductance stage are combined to a single stage to largely save power consumption as shown in Fig. 5.2. It consists of common gate and common source transistors which is claimed to have averagely good performance over other inspected types. The transconductance stage has been analyzed in the chapter. The NMOS switching stage with large size has been selected for performance consideration.

Fig. 5.2 The active balun mixer

5.2 Principle of the Mixer Circuit Design

In this chapter, the design principle of the low power, high linearity UWB front-end circuit is introduced. Fig. 5.3 shows the schematic of the low power, high linearity broadband down conversion mixer circuit. The principle emphasizes on the features of each block, which include low noise amplifier, active balun, and direct down-conversion mixer.

5.2.1 Transconductance stage

The transconductance stage consists of two transistors, a common gate transistor M1 and a common source transistor M2 as shown in Fig. 5.4. The RF input signal is transformed into differential current by M1 and M2, respectively. The output differential current is then connected to the switching stage for current commutation, which loads the transconductor stage and makes the current into voltage Vo1 and Vo2

at drain nodes. In the analysis, the parasitic capacitance Cgd1 and Cgd2 are not

V

gs1

C

R

IF

LON

LOP

V

bias

V

gs2 M3

C

V

=1.5V

RF

_in

Fig. 5.3 The schematic of the broadband down conversion mixer circuit

neglected and ro1 and ro2 are also taken into consideration.

Applying KCL to the small signal models shown in Fig. 5.5, the equations of output voltages to input voltage Vi is obtained as:

Where ZL models the loading impedance of the switching pairs and Vi’ is assumed close to Vi at the operating frequency for the large capacitance Cb which is added to do the dc blocking. The large resistor Rb is used to give dc bias voltage and neglected in the analysis.

Suppose that Zs2 is equal to zero in (5.2), then (5.2) would be:

(5.1) and (5.3) must be equal in magnitude and out of phase at the operation frequency.

Assume a pure resistance loading, ZL=RL, and equal size for the two transistors. The Fig. 5.4 Common-gate common-source transconductance stage

magnitude and phase of the two equations is extracted:

2 2 the magnitude balance condition without any impact on the phase difference.

Moreover, from (5.5), the phase difference of the two equations could be adjusted by one coefficient Cgd1 by adding a parallel capacitance Cex to the gate to drain capacitance of M1. Since Cgd1 will affect both the phase and gain difference, the Cex is

(a)

(b)

Fig. 5.5 Common-gate common-source transconductance stage (a) small signal model of common gate

(b) small signal model of common source

defined to make the phase balanced first, then to adjust gm1 to meet the magnitude condition. The bias voltages of CG and CS stage are separated, so gm1 can be adjusted by gate voltage independently. The value of gm1 and gm2 would not be far apart, and the values of ro1 and ro2 are expected to be almost equal.

The input admittance Yin of the mixer can also be derived from the small signal model shown in Fig. 5.4:

Where Yin_CG is the input admittance of the common gate transistor M1 only and Yin_CS is the input admittance seen into the gate of the common source transistor M2. The real part of the input impedance is mainly the parallel combination of 1/gm1 and Zs1. By Zs1, the gm value can be much more released, that is the power consumption can be much lower when making the input impedance matches to the source resistance.

Fig. 5.6 shows the gain error in broadband condition. The gain error at the operation frequency is around -0.14~0.3dB. And the phase error is always 178~180degree, as shown in Fig. 5.7.

5.2.2 Mixing stage

In this work, the proposed mixer utilizes current commutation for frequency mixing. A mixing stage is constructed to transform the incoming RF signal to a lower frequency as shown in Fig. 5.8. The non-ideal switching character and noise contribution will alleviate the circuit performance. To make the switching behavior more ideal, MOSFET of larger size is chosen and biasing point is set near threshold voltage. As pointed out in the beginning of this paper, the effort to convert signal into

Fig. 5.7 Simulation result of phase error Fig. 5.6 Simulation result of gain error

differential form is to make mixer in double-balanced structure. The even-order distortion and the LO-IF feedthrough are eliminated in the double-balanced mixer.

Moreover, large MOS device size is chosen for its lower flicker noise. The flicker noise of MOSFET is appeared in low frequency range around DC, much lower than LO frequency, it can be effectively modeled as interference at the gate terminal of switching component. This slowly varying offset voltage disturbs the switching time, advancing or retarding the time of zero crossing. Mixed with the LO signal, the low frequency noise is up-converted to frequency around the LO frequency which degrades the function of mixing. Final, the mixer topology is chosen as NMOS pairs.

5.2.3 Current injection method

In order to increase the mixer linearity and gain, there are only two or three possibilities: to increase the current flowing through the trans-conductors or to increase the load impedance or both of them. At a given current there is a limitation for increasing the load resistors because of the voltage drop along these resistors. On the other hand, higher current of the trans-conductors improves the gain and the linearity of the mixer but forces more current flowing through LO switches. The latter

Fig. 5.8 Mixing stage

effect causes a non ideal switching, which means that both switching transistors are simultaneously in on state for a longer time. Thus more and more RF current is lost as a common-mode signal. For a given LO amplitude, the switching time of the transistors can be reduced by reducing the drain current flowing through them. This can be achieved by the current injection method.

Current injection method is employed to increase the linearity of this mixer. Two dc currents are injected at the drains of the bottom stage transistors. The value of this DC current is optimized, so that it provides the best linearity, gain, power consumption, and bandwidth for the mixer. The other consideration made in designing the current source is that, its output impedance should be large, so that it does not attenuate the RF signal passing through the bottom stage of the mixer to the top transistors. The noise contribution of the switching stage is also reduced, because of the lower DC-current flowing through the switches. So we use the current injection method to improve the mixer linearity and gain.

5.3 UWB receiver Simulation Results and Comparison

The direct down-conversion mixer transforms the radio-frequency (RF) signal into base-band directly and needs high linearity to avoid the distortion of the signal.

Following the previous discussion, a low-power and high-linearity UWB receiver is designed, as shown in Fig. 5.9 and Fig. 5.10.

The simulation input return loss is plotted in Fig. 5.11. The simulation result of conversion gain versus radio frequency (RF) is shown in Fig. 5.12 and DSB noise figure is 6.9dB at IF of 100MHz.

The conversion gain of UWB front-end circuit is 20.3~21.1dB. Linearity analysis is conducted by the two-tone test. Two-tone test is done for measuring third-order intermodulation distortion. The simulation IIP3 is about -4.7~-5.8dB as shown in Fig. 5.13, and the power consumption of active mode is 10.4mW. Complete simulation results are summarized in Table 5.1 together with simulation results for comparison.

Fig. 5.9. UWB receiver architecture

V

_{gs_MT}

V

_{gs_AT}

VDD=1.5V

R

₂

R

₃

M5 M8

M10

M11

M12

V

_gs

α β

β

Fig. 5.10. CMOS constant current reference

Fig. 5.11. The simulation of input return loss S11

freq (1.000GHz to 15.00GHz)

S(1,1)

Fig. 5.12. The simulation of conversion gain

Fig. 5.13. The simulation of IIP3

Table 5.1 Summary of performance and comparison This work Technology 0.18um

CMOS

gain(dB) 20.3~21.1 22.9~26.4 19~21.5 18 19.5~23.3 Noise

Fig. 5.14 The FOM of UWB receiver performance

5.5 Chip Implementation And Measurement Considerations

5.5.1 Circuit Implementations

Following the above-mentioned analysis, a UWB front-end circuit is designed, as shown in Fig. 5.9 and Fig. 5.10. The front-end circuit is fabricated using 0.18um RF CMOS technology. The full chip layout of circuit is shown in Fig. 5.15. The total die area including bonding pads is 0.913 mm by 0.962 mm.

The RF input is placed on the left side, the LO input is placed on the right side, and the IF input is placed on the top side of the chip. The placement of pads is considered for the on-board measurement. In order to minimize the effect of the substrate noise on the system, a solid ground plane, constructed using a low resistive metal material, is placed between the signal pads and the substrate. Besides, there are many ground pads to minimize the effect of the bond-wire.

Fig. 5.15 Chip layout of UWB receiver front-end circuit

5.5.2 Measurement Considerations

Measurement is conducted by mounting the mixer die on FR4 board. Input testing signal is transformed into a differential form at LO ports by GSGSG differential probe.

Fig. 5.16 shows the measurement diagram. A unit gain output buffer is used to transform the differential signal into the single-ended form, and provides high input impedance to reduce loading effect.

5.6 Summary

A low-power, high linearity UWB front-end circuit, intended for use in the receiver path of a wireless local area network, is designed in standard 0.18um CMOS technology. The circuit architecture is chosen available for the application of low power consumption and high linearity. It is composed of a low noise amplifier, a active balun, and a direct down-conversion mixer. The linearity improvement is using MGTR circuit. Simulation results shows that the UWB front-end circuit achieves conversion gain of 20.3~21.1dB, input return loss of -10dB, input third-order intercept point (IIP3) of -4.7~-5.8dBm, and input power consuming only 10.4mW.

Fig. 5.16 Measurement diagram including unit gain output buffer

Chapter 6 Conclusion and Future Work

6.1 Conclusion

In Chapter 2, some architectures of the receiver, noise sources, and the theoretical MOSFET noise model are introduced. In Chapter 3, the design consideration of LNA and mixer is introduced. By analyzing and improving these, a low power, high linearity front end circuit are design and verified.

In Chapter 4, a MGTR UWB LNA is analyzed and verified in standard 0.18um CMOS technology. The MGTR technique is adopted to improve the linearity of the common source amplifier in the broadband condition. A compact equivalent circuit using AC complex transconductance analysis truly gives the optimal design parameters. Measurement results show that the improvement of the linearity is more than 5dB without extra power consumption.

In Chapter 5, a low power, high linearity UWB front end circuit, intended to use in the receiver path of UWB system, is designed in standard 0.18um CMOS technology. It is composed of a low noise amplifier, an active balun, and a Gilbert cell mixer. The UWB LNA provides higher linearity by using MGTR technology, and the single-ended signal is transformed into a differential form by the active balun.

Simulation results shows that the front-end circuit achieves conversion gain of 20.3~21.1dB, input return loss of -10dB, input third-order intercept point (IIP3) of -4.7~-5.8dBm, and power consuming only 10.4mW.

In this thesis, two chips, UWB LNA and receiver were designed and analyzed.

These two circuits, fabricated in TSMC 0.18um RF CMOS technology, are proposed

for the application of UWB communication system. One is a low power, high linearity UWB LNA which is composed of two amplifier stages with MGTR linearity improvement circuit. The IMD3 of the distortion cancellation for the common source amplifier stage have been analyzed and designed. The measured voltage conversion gain is 8.3dB and the total power consumption of it is 8.26mW from a 1.5V power supply.

Another circuit is a UWB receiver front-end circuit whose topology is chosen to suit the application of low power consumption and high linearity. A broadband active balun converts single input signal into differential output. Besides, a broadband mixer is adopted and carefully designed. The simulation results show the voltage conversion gain is 20.3~21.1dB and the total power consumption is only 10.4 mw from a 1.5V supply.

6.2 Future Work

About the work, the linearity can be improved by minimized the distortion of the third order intermodulation in broadband condition. The MGTR technique is an effective way to cancel the G_m^"(ω) of the device. But the second order intermodulation may become important to degrade the IIP2 of LNA in broadband condition, it is especially obvious when the G_m^" (ω)is small. Therefore, we can keep the original performance, such as gain, noise figure, etc. and improve the linearity and fixing IIP2 at the same time. There should be some other methods to look for a better compromise. If this method is realized together with MGTR technique or used to cancel the G_m^' ( )ω , the improvement of the linearity will be obvious.

References

[1] A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers,” IEEE J. Solid-State Circuits, vol.

39, no. 12, pp. 2259-2268, Dec. 2004.

[2] C.-T. Fu and C.-N. Kuo, “3~11-GHz CMOS UWB LNA using dual feedback for broadband matching,” IEEE RFIC Symp. Dig., 2006, pp.67-70.

[3] M. T. Reiha and J. R. Long, “A 1.2-V reactive-feedback 3.1–10.6 GHz low-noise amplifier in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp.

1023-1033, May 2007.

[4] Takao Kihara, Toshimasa Matsuoka, and Kenji Taniguchi, “A 1.0 V, 2.5 mW, Transformer Noise-Canceling UWB CMOS LNA,” IEEE RFIC Symp. Dig., 2008, pp.493-496.

[5] S. Tanka, F. Behbahani, and A. Abidi, “A linearization technique for CMOS RF power amplifier,” in Symp. VLSI Circuit Dig. Tech. Paper, 1997, pp.93-94.

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