Chapter 5 A Low Power, High Linearity UWB Receiver for
5.3 UWB receiver Simulation Results and Comparison
The direct down-conversion mixer transforms the radio-frequency (RF) signal into base-band directly and needs high linearity to avoid the distortion of the signal.
Following the previous discussion, a low-power and high-linearity UWB receiver is designed, as shown in Fig. 5.9 and Fig. 5.10.
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The simulation input return loss is plotted in Fig. 5.11. The simulation result of conversion gain versus radio frequency (RF) is shown in Fig. 5.12 and DSB noise figure is 6.9dB at IF of 100MHz.
The conversion gain of UWB front-end circuit is 20.3~21.1dB. Linearity analysis is conducted by the two-tone test. Two-tone test is done for measuring third-order intermodulation distortion. The simulation IIP3 is about -4.7~-5.8dB as shown in Fig. 5.13, and the power consumption of active mode is 10.4mW. Complete simulation results are summarized in Table 5.1 together with simulation results for comparison.
Fig. 5.9. UWB receiver architecture
V
gs_MTV
gs_ATVDD=1.5V
R
2R
3M4
M5 M8
M6
M7
M9
M10
M11
M12
V
gsα β
β
Fig. 5.10. CMOS constant current reference
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Fig. 5.11. The simulation of input return loss S11
freq (1.000GHz to 15.00GHz)
S(1,1)
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Fig. 5.12. The simulation of conversion gain
Fig. 5.13. The simulation of IIP3
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Table 5.1 Summary of performance and comparison This work Technology 0.18um
CMOS
gain(dB) 20.3~21.1 22.9~26.4 19~21.5 18 19.5~23.3 Noise
Fig. 5.14 The FOM of UWB receiver performance
0
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5.5 Chip Implementation And Measurement Considerations
5.5.1 Circuit Implementations
Following the above-mentioned analysis, a UWB front-end circuit is designed, as shown in Fig. 5.9 and Fig. 5.10. The front-end circuit is fabricated using 0.18um RF CMOS technology. The full chip layout of circuit is shown in Fig. 5.15. The total die area including bonding pads is 0.913 mm by 0.962 mm.
The RF input is placed on the left side, the LO input is placed on the right side, and the IF input is placed on the top side of the chip. The placement of pads is considered for the on-board measurement. In order to minimize the effect of the substrate noise on the system, a solid ground plane, constructed using a low resistive metal material, is placed between the signal pads and the substrate. Besides, there are many ground pads to minimize the effect of the bond-wire.
Fig. 5.15 Chip layout of UWB receiver front-end circuit
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5.5.2 Measurement Considerations
Measurement is conducted by mounting the mixer die on FR4 board. Input testing signal is transformed into a differential form at LO ports by GSGSG differential probe.
Fig. 5.16 shows the measurement diagram. A unit gain output buffer is used to transform the differential signal into the single-ended form, and provides high input impedance to reduce loading effect.
5.6 Summary
A low-power, high linearity UWB front-end circuit, intended for use in the receiver path of a wireless local area network, is designed in standard 0.18um CMOS technology. The circuit architecture is chosen available for the application of low power consumption and high linearity. It is composed of a low noise amplifier, a active balun, and a direct down-conversion mixer. The linearity improvement is using MGTR circuit. Simulation results shows that the UWB front-end circuit achieves conversion gain of 20.3~21.1dB, input return loss of -10dB, input third-order intercept point (IIP3) of -4.7~-5.8dBm, and input power consuming only 10.4mW.
Fig. 5.16 Measurement diagram including unit gain output buffer
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Chapter 6
Conclusion and Future Work
6.1 Conclusion
In Chapter 2, some architectures of the receiver, noise sources, and the theoretical MOSFET noise model are introduced. In Chapter 3, the design consideration of LNA and mixer is introduced. By analyzing and improving these, a low power, high linearity front end circuit are design and verified.
In Chapter 4, a MGTR UWB LNA is analyzed and verified in standard 0.18um CMOS technology. The MGTR technique is adopted to improve the linearity of the common source amplifier in the broadband condition. A compact equivalent circuit using AC complex transconductance analysis truly gives the optimal design parameters. Measurement results show that the improvement of the linearity is more than 5dB without extra power consumption.
In Chapter 5, a low power, high linearity UWB front end circuit, intended to use in the receiver path of UWB system, is designed in standard 0.18um CMOS technology. It is composed of a low noise amplifier, an active balun, and a Gilbert cell mixer. The UWB LNA provides higher linearity by using MGTR technology, and the single-ended signal is transformed into a differential form by the active balun.
Simulation results shows that the front-end circuit achieves conversion gain of 20.3~21.1dB, input return loss of -10dB, input third-order intercept point (IIP3) of -4.7~-5.8dBm, and power consuming only 10.4mW.
In this thesis, two chips, UWB LNA and receiver were designed and analyzed.
These two circuits, fabricated in TSMC 0.18um RF CMOS technology, are proposed
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for the application of UWB communication system. One is a low power, high linearity UWB LNA which is composed of two amplifier stages with MGTR linearity improvement circuit. The IMD3 of the distortion cancellation for the common source amplifier stage have been analyzed and designed. The measured voltage conversion gain is 8.3dB and the total power consumption of it is 8.26mW from a 1.5V power supply.
Another circuit is a UWB receiver front-end circuit whose topology is chosen to suit the application of low power consumption and high linearity. A broadband active balun converts single input signal into differential output. Besides, a broadband mixer is adopted and carefully designed. The simulation results show the voltage conversion gain is 20.3~21.1dB and the total power consumption is only 10.4 mw from a 1.5V supply.
6.2 Future Work
About the work, the linearity can be improved by minimized the distortion of the third order intermodulation in broadband condition. The MGTR technique is an effective way to cancel the Gm"(ω) of the device. But the second order intermodulation may become important to degrade the IIP2 of LNA in broadband condition, it is especially obvious when the Gm" (ω)is small. Therefore, we can keep the original performance, such as gain, noise figure, etc. and improve the linearity and fixing IIP2 at the same time. There should be some other methods to look for a better compromise. If this method is realized together with MGTR technique or used to cancel the Gm' ( )ω , the improvement of the linearity will be obvious.
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