Linearity

As far as cascaded stages are concerned, linearity is a very important performance in mixer stage. In general, it will dominate the distortion of the entire receiver. The detail analysis will be introduced in Chapter 4.

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Chapter 4

-5dBm IIP3 UWB Low Noise Amplifier Using Complex Derivative Cancellation Technique

4.1 Introduction

Linearity plays an important role in broadband RF systems because nonlinearity degrades system performance with the consequence effects such as harmonic generation, cross-modulation and intermodulation. Of these distortions, the third-order intermodulation (IMD3) is one of the critical terms to be solved. The issue is especially serious to the low noise amplifier (LNA) in broadband system as an LNA needs high gain to suppress noise, while facing a broadband spectrum involving external interferers without much filtering. As such, it has been great attention on linearity improvement to RF circuit designers.

In recent years, several techniques have been proposed to improve the linearity of RF amplifier. Most of them are based on negative feedback circuit. One of the most famous ones is using source degeneration by resistor or inductor. Another scheme is the superposition of auxiliary transistors operated in different bias conditions to cancel the derivative of device transconductance. Such method, referred as derivative superposition or multiple gated transistors (MGTR), offers a good opportunity to extend linearity without increasing power consumption. However the conventional derivative cancellation through DC transconductance analysis is inaccurate at RF frequency. A complex transconductance analysis technique was proposed to search for the optimal design parameters. It is also found adequate to improving IIP3 in a broadband LNA design.

33

In this work, a 3.1~10.6GHz CMOS LNA employing the complex transconductance analysis is reported, with linearity improvement of 5 dB. In the next section the IIP3 analysis of a cascode amplifier is provided, followed by the LNA circuit design, fabrication and measurement results in 0.18 μm CMOS technology.

4.2 UWB LNA Design Consideration

A low noise amplifier (LNA) is an important component at receiver path for wireless communication. It provides a high gain with low noise figure for overall wireless communication system. For various LNA circuit topologies, the common source amplifier is generally popular as it provides a better noise performance with low power consumption. It is especially popular for extreme applications in which ultra low power. A widely used one for narrowband LNA design is a CS amplifier with inductive source degeneration, which has been well analyzed. Because the frequency dependency of the derived Zopt is different from that of Zin, broadband LNA is not feasible using that technique. This is observed in the broadband amplifier realized by employing a multi-order LC matching network. The noise performance is still band-limited. We designed the UWB LNA by employing dual reactive feedback topology, and the theory will be detailed in this paper.

In this chapter discussions are given for broadband noise and input matching realization in a CMOS LNA. Starting from the next section, we first analyze the dual reactive feedback circuit is proposed to achieve broadband noise and input matching, we use transformer simplifying the LNA circuit to save chip area. For better linearity, we try to use multiple gate transistors to improve the linearity of UWB LNA. The following section shows a design example of an UWB LNA implemented in TSMC 0.18µm CMOS process, along with simulation and measurement results.

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4.3 Dual Reactive Feedback Technique For Broadband Input Impedance Matching

For this UWB LNA, the proposed solution is a dual reactive feedback topology composing of a capacitive shunt feedback and an inductive series feedback, which individually attain noise and input matching in two different frequency regions to constitute the broadband noise and input matching. These two feedbacks are seamlessly combined by employing an inductor at transistor drain, which conducts different loading conditions for each feedback structure. Then for some reason, three inductors in this circuitry are merged into a transformer to reduce the chip area.

4.3.1 The proposed dual reactive feedback circuit

The proposed dual reactive feedback structure with input matching network is shown in Fig. 4.1. The Zopt* has an equivalent circuit representation shown in Fig. 4.2, as Zopt* is not affected by lossless feedbacks. By employing the ladder filter structure

Fig. 4.1 Dual reactive feedback structure

Fig. 4.2 Equivalent circuit of Zopt*.

35

with L1 and C1, the Zopt* to Z0 matching bandwidth is extended. Following the general filter design guideline,

2 1

1 C (L_g L_s) (C_gs C_gd) 1 (2 f_c)

L ⋅ = + ⋅ + = π , (4.1)

in which fc is the center frequency of pass band. To the optimal wideband matching result the Ropt can be designed slightly less than Z0, not strictly following the standard filter design algorithm. The design of L1 and C1 also takes into account the gain response as described the in next subsection.

After the broadband noise matching is preliminarily achieved, the input impedance is then matched by the proposed dual reactive feedback circuitry, as in the dashed-line box of Fig. 4.1. This circuitry provides different reactive feedbacks in different frequency regions. In the frequency region lower than the Ld-CL series resonance frequency, when looked from the transistor drain, the Ld-CL tank behaves

(a)

(b)

Fig. 4.3 Input impedance changed among the two feedbacks with frequency

(a) capacitive shunt feedback in lower frequency region;

(b) inductive series feedback in higher frequency region.

36

like a capacitor CL' as shown in the left of Fig. 4.3(a). Hence the input impedance can be represented as an equivalent circuit in the right of Fig. 4.3(a), in which

gs

Two noiseless resistances can be found in this circuit: the Rs,IF by the series inductive feedback of Ls, and the Rs,CF by the shunt capacitive feedback of Cgd with CL'. Because the Cs,CF, as in (4.4), is much larger than Cgs, the branch of Cs,CF

dominates the input impedance in the lower frequency region. As such the Rs,CF is the noiseless resistance added on Rg to match to Ropt in this region.

In the higher frequency region where the effect of Cgs is significant, the Ld is designed to resonate with CL to provide a short circuit at the transistor drain, as shown in Fig. 4.3(b). Hence the branch of Cs,CF in the right of Fig. 4.3(b) vanishes and the Rs,IF takes over the role of Rs,CF. Such handover of reactive feedbacks can well minimize the Rg-to-Ropt difference in wide frequency range.

The determination of these relative frequency parameters includes the L1, C1, and Lg in Fig. 4.1. For the capacitive feedback, the Lg in Fig. 4.1 and the Cs,CF and Rg+Rs,CF in Fig. 4.3(a) constitute a low-Q resonance tank with resonance frequency

gd

With its low-Q character, the slight frequency shift of f0,CF by L1 and C1 is ignorable.

For the inductive feedback, the resonance frequency is located at )

37

As mentioned before, at this frequency the Ld is expected to tune out CL. Therefore

2 ,

0 )

2 (

1 _IF

L

d C f

L ⋅ = π . (4.7) The frequency relationship of f0,CF < fc < f0,IF is obtained from (4.1), (4.5)–(4.6).

4.3.2 Gain response

The dual reactive feedback amplifier is expected to have a broadband response to suppress noise by the succeeding stages. The gain response is mainly shaped by the drain network in Fig. 4.4. as the input network is a broadband structure. Based on the low-pass response by CL (the gray curve in Fig. 4.4.), the Ld conducts a series peaking providing gain expansion at frequency

)

||

( 2

, 1

0Peak Ld Cgd CL

f = π ⋅ , (4.8) which is higher than f0,IF. The voltage gain at this frequency can be derived with the circuit approximation, in which

gd m

gd gs

d g C

C

R C +

≈

' . (4.9)

As to the gain in the lower out-of-band frequency, it is suppressed by the input shunt inductor L1. As a result it produces a gain peak at the lower band edge. The magnitude of this peak is designed close to that of gain peak at the higher band edge such that the expected gain response is as the solid curve in Fig. 4.4. Following this design guideline the voltage gain is mainly determined by that at f0,Peak.

If a very wide bandwidth needs to be covered, an additional gain expansion by the next stage is necessary to compensate the mid-band depression. Such a case applies to a 3–11GHz UWB LNA. A flat gain response is obtainable by this stage itself as the two gain peaks can be designed fairly close to each other.

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4.3.3 Dual reactive feedback with Transformer feedback

The proposed dual reactive feedback amplifier as shown in Fig. 4.1 demands four inductors to implement, which occupy huge die area. To reduce the inductor number, the transformer feedback topology is proposed to replace the three inductors Lg, Ld, and Ls, as shown in Fig. 4.5(a). In transformer feedback the Lg' and Ld are overlap sharing the same die area and having a mutual inductance M to constitute a transformer. The mutual inductance M senses the drain current and contributes a series voltage feedback at input, which provides the same function as Ls in the inductive source degeneration amplifier. The input impedance can be expressed in equivalent circuit as shown in Fig. 4.5(b), in which Lg' = Lg+ Ls and

Fig. 4.4 Gain response design of the dual reactive feedback stage.

(a)

(b)

Fig. 4.5 (a) The inductive source degeneration feedback can be substituted by the transformer feedback. (b) Their equivalent circuit for input impedance.

39

gs TF m

s C

M

R g ⋅

, = , (4.10)

which provides the wanted noiseless resistance.

The transformer feedback topology is also advantageous that the transistor source is connected to ground directly. This allows this amplifier be implemented in CMOS inverter structure, which employs both NMOS and PMOS to reuse drain current for a larger transconductance. The final shape of the proposed dual reactive feedback amplifier is therefore shown in Fig. 4.6. Here the mutual inductance is represented in coupling factor k with the relationM =k L_gL_d , and the Lg in Fig. 4.6 represents the Lg' in Fig. 4.5.

Because the M in general is much smaller than Lg and Ld, the coupling factor k is much smaller than 1. Design experience shows the k value between 0.1 and 0.2.

Possible layout schemes of such weak coupling transformer include common-centroid coil and overlapping coil, Generally the common-centroid coil has a better quality factor but consumes more die area. In the design example, the common-centroid coil was adopted for a better result.

Fig. 4.6 The dual reactive feedback amplifier with transformer feedback.

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4.4 A 3-11GHz Ultra-Wideband Low Noise Amplifier

A design example of a 3–11GHz UWB LNA employing the dual reactive feedback is demonstrated, as shown in Fig. 4.7. The inverter amplifier is self biased with a 8kΩ feedback resistor. The Cgs of MT plays the role of CL. The L3 between MT

and M1 further increases the gain expansion at the higher band edge. The body of M1

is biased to its source with another 8kΩ resistor. The L2 and R1 provide a voltage gain with a low-Q peak at the center frequency to compensate the mid-band gain depression by the first stage. The M2 and M3 constitute the output buffer and the 0.1nH output inductor improves the output matching to 50Ω. For broadband input matching, the L1 and C1 increase the order of matching network hence both the S11 and Sopt around the center of Smith Chart and achieve good matching.

The second stage of this LNA plays the role of gain response trimming to have a flat in-band response. The L3 further expands the gain response at the higher band edge with series peaking, and the L2 and R1 provide a low-Q shunt peaking at mid-band, as shown in Fig. 4.8.

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This LNA was designed in TSMC 0.18um CMOS process with aluminum as metal material. In simulation it was designed to target >10dB return loss, < 5dB maximum in-band noise figure, >15dB power gain with less than 1dB in-band variation, while draws <10mW DC power from a 1.5V supply.

4.5 Analysis of Linearity

In UWB RF transceiver design, linearity requirement becomes more and more challenging. Circuit nonlinearity results in various system distortions associated with the even and odd order nonlinearities. Of these distortions, the third-order intermodulation is one of the most critical terms responsible for linearity degradation in general RF systems. Due to the fact, how to improve the linearity of RF circuits without

Fig. 4.8 Gain response

Fig. 4.7 A 3–11GHz UWB LNA as a design example of dual reactive feedback

42

extra power consumption becomes an important topic to be studied.

As far as cascade amplifier stages are concerned, system design calls for high linearity in the LNA to alleviate the distortion issues. Linearity is most limited by the transconductance amplifier, hence we will discuss the nonlinear effect of the common source amplifier in section 4.5.1.

In recent years, several techniques have been proposed to improve the linearity of RF circuits by linearization of the nonlinear transconductance, such as degeneration feedback. Another scheme is the superposition of auxiliary transistors operated in different bias conditions to null the derivative of device transconductance. Combined with the technique of out-of-band impedance termination, circuit linearity can be further enhanced, as indicated by the Volterra series analysis. The scheme, named as derivative superposition or multiple gated transistors (MGTR), offers a good opportunity to extend linearity without increasing power consumption. Further, we try to improve the linearity of broadband LNA using MGTR.

It is proposed that a complex transconductance shall be employed to search for the optimal design parameters for MGTR design consideration. Therefore we propose a compact equivalent circuit for the design of the multiple gated transistors technique in section 4.5.2. In section 4.5.3, we improve UWB LNA using multiple gated transistor technique by complex transconductance analysis.

4.5.1 Nonlinear Effects of Common Source Amplifier

For the common-source amplifier, the nonlinear effect is dominated by the transconductance and the output conductance of the device. The nonlinear effects of the capacitances and substrate can be neglected, and they can be considered as linear elements. Therefore we only consider the transconductance and the output

43

conductance as the nonlinear source for the following analysis.

Fig. 4.9 shows a common-source amplifier, where Z1 is the input impedance, and Z2 is the output impedance. From the above-mentioned introduction and assuming that the common-source amplifier works in the weakly nonlinear region, the equivalent circuit of the common-source amplifier can be shown as Fig. 4.9, where the transconductance (gm) and the output conductance (ro) are the nonlinear elements.

Therefore the I-V curve of the device can be expressed as

....

The nonlinear distortion can be obtained by calculating the Volterra kernels of order one, two and three of voltages.

First-order kernels

In order to obtain the first-order Volterra kernels, the nonlinear elements must be replaced with its linearized equivalent, as shown in Fig. 4.10. Applying Kirchoff’s current law in Fig. 4.10 yields:

Fig. 4.9 The equivalent circuit of the common-source amplifier

44 transfer functions indicates the order of the transfer function, whereas the second subscript corresponds to the numbering of the node voltages. Then the first-order kernels H₁₁(s) and H₁₂(s) can be expressed as

For computing second-order kernels, the input signal v is replaced by a short _in circuit, and the second-order nonlinear current sources are applied to the linearized circuit, as shown in Fig 4.11. Applying Kirchoff’s current law in Fig. 4.11 yields:

Fig. 4.10 Linearized equivalent of the circuit

45

Just as second-order kernels, the third-order ones are computed as the response to the third-order nonlinear current sources, as shown in Fig. 4.12. Applying Kirchoff’s current law in Fig. 4.12 yields:

⎥⎦

Fig. 4.11 The equivalent circuit for the computation of the second-order kernels

46

Of the nonlinear distortions, the third-order intermodulation is one of the most critical terms responsible for linearity degradation in general RF systems. In order to obtain the third-order intermodulation distortion, input signal is replaced by a two-tone test signal (V₁=Asin(ω₁t), V₂ =Asin(ω₂t)), and the fundamental signal at ω and the distortion at 1 2ω₁−ω₂ must be computed by (4-14) and (4-29). By assuming s₁ =s₂ = jω₁ =s , s₃ =−jω₂ ≈−s , and jω₁− jω₂ =Δs , then the third-order intermodulation distortion (IM ) can be expressed as ₃

Fig. 4.12 The equivalent circuit for the computation of the third-order kernels

47

From (4-31). The equation provides good agreement with harmonic-balance simulation. The nonlinear distortions result from the nonlinear effects of the transconductance and the output conductance and vary with different load impedance.

For our case, the linearity is dominated by the device transconductance in the low load impedance.

4.5.2 Multiple Gated Transistors Method Using Complex Transconductance Analysis

The MGTR method improves linearity by cancellation of these effects due to auxiliary transistor (AT) as shown in Fig. 4.13. This negative peak of the main transistor (MT) can be cancelled by the positive peak value of a properly bias and size of AT. Because AT is biased in the sub-threshold region, this linearization method does not consume much extra power.

For typical MGTR, using DC transconductance the conventional analysis lacks of accuracy to predict the high-frequency operating condition. Essentially nonlinear distortion is frequency-dependent. An effective method using complex AC transconductance is therefore used to achieve optimized device size and bias for the auxiliary transistor.

48

Without loss of generality in this nonlinear analysis, the superposed configuration in MGTR can be simply represented by the transconductance element Gm(ω). The transconductance Gm(ω)is defined in the same way as the ratio of the output current to the input voltage, including all the intrinsic and extrinsic frequency-dependency of MOSFET devices. It could be a complex value at high frequencies. Its nonlinearity shall be related to the load impedance and the operation frequency. Consequently the equivalent circuit model of a transconductance amplifier is shown in Fig. 4.14.

The third-order intermodulation product IMD3 in a two-tone test is derived by Volterra series analysis and expressed as

· ·

_| ^{| |·| |·| |} _|, (4.32) where

|i_{NL G} | |H | · |ε , ∆ , 2 |, (4.33) Fig. 4.14 The compact box-type equivalent circuit model

Fig. 4.13 MGTR architecture

49

|ε , ∆ , 2 | ^G" _! ·^G _! 2Z ∆ H ∆ ^G _! Z 2 H 2 ^G _! , (4.34)

Lower IMD3 can be obtained by reducing ε , ∆ , 2 in Equation (4.32). Similarly the major effort is cancellation of G^”m(ω), which is conducted in the complex domain. For the value of G^”m for MT is negative in the gate bias voltage vgs_MT=0.77V and the device sizes of MT is NF=13. It can be cancelled by the positive value of AT with a proper bias voltage. This complex transconductance analysis actually suggests that the proper bias voltage vgs_AT=0.46V, and the device sizes of AT are chosen as NF=11, as can be seen, G^”m appears close to zero at the gate bias voltage vgs_MT=0.77V at 7GHz in the polar plot as shown in Fig. 4.15. From Fig. 4.16, we can get the magnitude of complex transconductance to matching the traditional DC transconductance analysis.

For the optimal device size and bias voltage of AT minimizes the value of G^”m. Using the IIP3 contour as shown in Fig.4.17, we observe the value of IIP3 in the CS amplifier by sweeping the device size and bias voltage of AT for the condition which is the gate bias voltage vgs_MT=0.77V for MT, and the device sizes of MT is finger numbers of 13. Final, we choose the proper bias voltage vgs_AT=0.46V, and the device sizes of AT is finger numbers of 11 for the MGTR optimal parameters.

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single transistor MGTR

0.4 0.5 0.6 0.7 0.8 0.9 0.000

0.005 0.010 0.015 0.020

|G

m"

| ( A/ V

3

)

Main transistor V

_gs

(V)

Fig. 4.16 Cancellation of AC gm” in MGTR configuration Fig. 4.15 Cancellation of complex AC Gm” in polar plot

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4.8 6.4

8.0 13

9.6

4.8 8.0

3.2 6.4

1.6

14 14

14

0.30 0.35 0.40 0.45 0.50 0.55 0.60 6 14 8

10 12 14 16 18 20

Au xi liary tran sistor si ze (n r)

Auxiliary transistor V

_gs

(V)

Fig. 4.17 Search for the optimal device size and bias voltage using IIP3 contour

4.5.3 Broadband Linearity Improvement By Using MGTR

For a single transistor, the third-order intermodulation of the transconductance element G^”m(ω) in a two-tone test is derived by small signal circuit analysis and expressed as

"

" 3

2 2 2

( ) 3( ) ( )

4 3! (1 )(1 )(1 )

m L

m gs

gs s gs L gs s

g Z

G v

C Z j C Z j C Z

ω ^{= −} +ω + ω + ω , (4.35)

Similarly the major effort is canceling the IMD3 of MT, which is conducted in the complex domain. In order to improve the linearity of broadband LNA, lower output IMD3 can be obtained by reducing the negative IMD3 of MT using the positive IMD3 of AT. From Equation (4.35), we get the IMD3 frequency response of a transistor. To keep the perfect cancellation effect in broadband condition, we choose the similar

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