REVIEWS ON FRONT–END RECEIVERS, LOW–NOISE
2.3 CMOS Mixers
To recover the information carried by the RF spectrum at high frequencies, the down-conversion mixer converts the input RF spectrum at high frequencies to an intermediate frequency (IF) at the output through the use of a local oscillator signal (LO). Since the mixer locates immediately after the LNA in the receiver chain as shown in Fig. 2.3, it effects the linearity performance of the complete receiver [62]. A higher linearity allows a larger input power range from LNA. Linearity is the most difficult specification to achieve in designing a low-voltage mixer. Since the headroom is strictly limited in low-voltage mixer, high gain LNA may saturate mixer when a maximum signal or high-power blocking received. To handel the large signal from LNA, sufficient linearity is necessary. Besides the issue of the low-voltage of operation, RF design on advanced CMOS processes has been challenging on the high cost of the chip area, This translates to a need to reduce the design area for achieving a specific function under certain performance requirements [63].
The topology of the mixer at high-frequency, which have been reported in litera-ture [61,63–72], can be classified into active and passive topologies depend on the DC power consummation. The passive mixers include differential pair mixer [61, 68, 71, 72], cascade mixer [63], and the transconductance mixer [67]. While passive mixers include drain-pumped resistive mixer [64], gate-drain-pumped resistive mixer [66], and resistive mixer [69, 70].
In Fig. 2.15 [61], differential pair, which also known as Gilbert cell, consists of transcon-ductance stage M1, differential switching pair M2 and M3, and load RL. The conversion gain of Gilbert cell mixer is proportional to RL, if the RL is large, its conversion gain would be large. With a large voltage drop, the Gilbert cell mixer is modified to the current-reuse bleeding mixer [71]. Bleeding mixer topology, as shown in Fig. 2.16, provides the better performance in terms of conversion gain, linearity, noise figure, and LO isolation. How-ever, in order to drive differential pairs sufficiently to turn on and turn off, the LO signal strength should be large enough.
Cascade mixer is shown in Fig. 2.17 [63]. The mixer consists of two transistors M1 and M2 are connected in series. RF and LO signals are applied through M1 and M2 gates, respectively. The resultant output IF signal is extracted from the drain terminal of M2. A cascade type mixer has the advantage of providing good LO-RF isolation without the use of filter. Besides, the using of double-gate layout to implement M1 and M2, the capacitance at the drain of M1 can be minimized though a careful layout, which improves the conversion gain at mm-wave.
The simple schematic of transconductance mixer is shown in Fig. 2.18. In Fig. 2.18 the LO and RF signals are combined and applied to the gate of M1, to large the conversion-gain of M1, M1 is operated in the saturation region, with gate-source voltage (VGS) of M1 is set close to its threshold Voltage (VT H). However, due to the close operational frequencies of LO and RF signals, the RF-LO isolation is very poor. In order to improve the LO-RF isolation hybrid combiner is used in [67] as shown in Fig. 2.19, Although, the mixer in [67]
required low input LO power, short-circuit drain nodes at LO frequency are required to improve stability. Thus, an open quarter-wave stub at the drain node is used. Besides, to provide DC biasing for M1 and M2 an extra area is required for implementing short quarter-wave stub. All this increase the chip size area.
The active mixer topologies can achieve low conversion loss or even gain, but the lin-earity of these active topologies is low, especially at moderate to low power consumption.
Much higher linearity can be achieved with resistive mixers. Drain-pumped resistive mixer is shown in Fig. 2.20 [64]. In Fig. 2.20 LO and RF signals are applied to drain and gate of M1, respectively. The transconductance of M1 is a time variant function of drain-source voltage VDS and VGS. At proper bias, the nonlinearities of the other elements are weak and can be neglected. The pumped resistive mixer shown in Fig. 2.21 [66]. In gate-pumped resistive mixer LO and RF signals are applied to source and gate of M1, The transconductance of M1 is a time variant function of VGS.
Another passive mixer topology is shown in Fig. 2.22 [69, 70], In this topology LO signal is applied to the gate of M1 via a matching network, a simple diplexer separates the RF and IF signals. The passive mixers have a significant advantage that RF and LO frequencies, which are close in the frequency value, are injected at different ports. Thus, the simplified filtered circuit would improve the LO-RF isolation. However, due to passive and resistive nature of the resistive mixers topologies, its have a relative high conversion loss. In addition they require high LO input power. Table 2.3 summarizes the performance parameters of the recent studies high-frequency CMOS mixers dating from 2004-2007.
Table 2.1
Table2.1:Comparisonofreceiverarchitecture. HeterodyneDirect-ConversionImage-RejectionWide-bandIFLow-IFDouble-Quadrature PerformanceGoodPoorModerateModerateModerateModerate DC-OffsetsNoYesNoNoNoNo 1/fnoiseNoYesNoNoNoNo BalanceI/QNotrequiredAccurateAccurateAccurateAccurateModerate ImageRejectionGoodNotrequiredModerateModerateModerateGood IntegrationAbilityPoorGoodModerateModerateModerateGood PowerDissipationHighLowLowHighLowLow
Table2.2:SummaryofrecentCMOSLNAresults. Ref.NFGainS11/S221dB/IIP3PowerSupplyFreq.ProcessCircuitYear [dB][dB][dB][dBm][mW]voltage[V][GHz]Topology [46]410-15/-17-/-452200.18μCMOSCascode1stage2001 [59]5.212-12/--/-347-170.18μCMOSCascode2stages2003 [59]610-17/--/-347-240.18μCMOSCascode2stages2003 [56]5.612.86-11/-22-11.1/+2.04541.823.50.18μCMOS3stagesCS2003 [45]6.45.8-20/-20-4.8/+3101.52090nmCMOS1stageCS2004 [55]5.612.9-11/-22-11.1/+2541.823.70.18μCMOS3stagesCS2004 [55]6.98.9-14/-12-10.2/+2541.825.70.18μCMOS3stagesCS2004 [61]615-/--/-241.521.80.18μCMOS1CGand2CSstages2004 [54]3.1610.71-15/-12-5/+5.1628.61.3140.18μCMOS2stagesCS2005 [53]3.913.1-15/-20-12.2/+0.54141240.18μCMOS2stagesCS2005 [52]5.59.2-8/-4-/+71912090nmCMOS2stagesCS2005 [51]3.27.5-16/-30-/-10.612490nmCMOS1stagesCS2005 [50]416.2-15/-5-/-26.41.22690nmCMOS2stagesCS2005 [60]4.613-1.5/--/-4.81.2600.13μCMOSCGandCSstages2005 [42]8.812-15/-15-10/-0.5541.5600.13μCMOSCascode3stages2005 [73]3.18.4-5/-10-/+4.8141.42090nmCMOSCascode1stage2006 [58]11.516.5-15/-10-18.5/-16.21.222.50.12μCMOSCascode1stageCS2006 [74]7.120-8/-5+1.8/-792.45790nmCMOSCascode3stages2006 [43]8.217.8-7/-2-16.1/-91.22.4600.13μCMOSCascode4stages2007 [44]612-12/-30+4/-10.416290nmCMOS2stagesCS2007 [57]5.514.6-20/-20-15.6/-6.8241.55890nmCMOSCascode2stages2007
Table2.3:Summaryofrecenthigh-frequencyCMOSmixerresults. Ref.RFFreq.IFFreq.Conversion-gainLOPower1dB/IIP3PowerProcessCircuitYear [GHz][GHz][dB][dBm][dBm][mW]Topology [64]352.5-4.67.5-6/2090nmSOI-CMOSdrain-pumpedresistive2004 [65]302.5-2.65-/0.520.490nmSOI-CMOSactivesinglebalanced2004 [61]21.84.913--/-60.18μmCMOSactivesinglebalanced2004 [66]272.5-9.710-/20090nmSOI-CMOSgate-pumpedresistive2005 [67]602-20-/-3.52.40.13μmCMOSactivesinglebalanced2005 [68]192.71-1-/-26.90.13μmCMOSactivedoublebalanced2005 [69]281.6-11.1513-2.7/80.640.18μmCMOSresistivesingleended2006 [70]602-11.646/16.5090nmCMOSresistivesingleended2006 [63]604-1.21.50.2/--90nmCMOSactivesingleended2006 [71]60028∗ --22.5/-90.13μmCMOSactivesinglebalanced2006 [72]17.22.4-16--1/-270.18μmCMOSactivedoublebalanced2007 *Voltagegain.
Figure2.1:Theblockdiagramofthehomodyne,direct-conversion,orzero-IFreceiver.
Figure 2.2: Two sources of DC offsets in the direct-conversion receiver.
Figure2.3:TheblockdiagramoftheheterodyneorIFreceiver.
Figure2.4:TheblockdiagramoftheHartleyreceiver.
Figure2.5:TheblockdiagramoftheWeaverreceiver.
Figure2.6:Theblockdiagramofthewideband-IFreceiver.
Figure2.7:Theblockdiagramofthelow-IFreceiver.
Figure2.8:Spectraflowofthelow-IFreceiver.
Figure2.9:Theblockdiagramofthedouble-quadraturereceiver.
Figure2.10:Spectraflowofthedouble-quadraturereceiver.
Figure 2.11: a) The common-source amplifier as the input stage, b) The common-source amplifier with source degeneration inductor.
Figure 2.12: The schematic diagram of 3-stage common-source LNA.
Figure 2.13: The schematic diagram of cascode LNA.
Figure 2.14: The schematic diagram of Common-gate with resistive feedback (CGRF)LNA.
newpage
Figure 2.15: The schematic diagram of single-balanced mixer Gilbert cell mixer.
Figure 2.16: The schematic diagram of single-balanced mixer with current bleeding.
Figure 2.17: The schematic diagram of Cascade mixer.
Figure 2.18: The schematic diagram of transconductance mixer.
Figure 2.19: The schematic diagram of transconductance quadrature balanced mixer with hybrid combiner.
Figure 2.20: The schematic diagram of drain-pumped resistive mixer.
Figure 2.21: The schematic diagram of gate-pumped resistive mixer.
Figure 2.22: The schematic diagram of resistive mixer.