互補式金氧半電流操作模式之射頻接收器前端電路設計與分析

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୯!ҥ!Ҭ!೯!ε!Ꮲ

ႝηπำᏢسႝηࣴز܌

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റ!γ!ፕ!Ў

!

ϕံԄߎ਼ъႝࢬᏹբኳԄϐ৔ᓎௗԏ

Ꮤ߻ᆄႝၡ೛ीᆶϩ݋

The Analysis and Design of CMOS

Current-Mode RF Receiver Front-End

Integrated Circuits

!

!!!!!!!ࣴ!ز!ғ!Ǻ຤!!्!!!Fadi Riad Shahroury

ࡰᏤ௲௤ Ǻֆख़ߘ Chung-Yu Wu

!!

!

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ϕံԄߎ਼ъႝࢬᏹբኳԄϐ৔ᓎௗԏᏔ߻

ᆄႝၡ೛ीᆶϩ݋

The Analysis and Design of CMOS

Current-Mode RF Receiver Front-End

Integrated Circuits

!

ࣴ ز ғ

Ǻ຤ ्

Student

_{ǺFadi Riad Shahroury}

ࡰᏤ௲௤

Ǻֆख़ߘ

Advisor

ǺChung-Yu Wu

!

୯ ҥ Ҭ ೯ ε Ꮲ

ႝηπำᏢسႝηࣴز܌

റ γ ፕ Ў

A Dissertation

Submitted to Department of Electronics Engineering and

Institute of Electronics

College of Electrical and Computer Engineering

Nation Chiao Tung University

In Partial Fulfillment of Requirements

For the Degree of

Doctor of Philosophy

In

Electronic Engineering

September 2008

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ϕံԄߎ਼ъႝࢬᏹբኳԄϐ৔ᓎௗԏ

Ꮤ߻ᆄႝၡ೛ीᆶϩ݋

!

ᏢғǺ຤्!!!!!!!!!!!!!!ࡰᏤ௲௤Ǻֆख़ߘറγ!

!

୯ҥҬ೯εᏢ!

ႝηπำᏢسႝηࣴز܌!

!

ᄔ!ा!

!

!!!!ӧ೭ጇፕЎύǴඔॊΑեႝᓸǵႝࢬኳԄడԯݢ৔ᓎ߻ᆄႝၡޑ

೛ीݤϷჴ౜מѯǶ ҁጇፕЎЬाϩΟঁ೽ҽǴх֖Α (1)ճҔႝ৒

ӣ௤ޑϰଛᆛၡמѯǴٰኳಔϯǵ೛ीǵаϷϩ݋եᚇૻܫεᏔǹ(2)

եLOф౗ǵΐΜࡋ࣬ՏৡǵѳᑽࢎᄬǵԾՉ໒ᜢ(self-switching)ޑႝ

ࢬኳԄషᓎᏔޑ೛ीᆶϩ݋ǹ(3) ೛ीᆶϩ݋΋ঁᏱԖӧٿԭѤΜሹ

ᇲ૟ޑൂ඲ТLOૻဦౢғᏔǵаϷޔࢬୃ౽ံᓭޑ1ҷ੝ႝࢬኳԄௗ

ԏᐒ߻ᆄႝၡǶ

२ӃǴ΋ঁଞჹܭեᚇૻܫεᏔޑཥޑᒡΕߔלф౗ϰଛמѯ೏ග

рǶӧ܌ගрޑמѯύǴᒡΕӅྍཱུܫεᏔޑ႔ཱུ-ཱུؕႝ৒Ϸႝ৒ӣ

௤ϰଛᆛၡ೏Ҕٰჴ౜΋ঁჴኧޑᒡΕߔלǴаԿܭૈکᒡΕྍཱུߔ

לϰଛǶ٬Ҕ೭ঁמѯǴૈӕਔၲډᚇૻനλᆶф౗ቚ੻നεǴ٠Ъ

ૈӧό઻ཞጕ܄ࡋΠ٬ҔߚதեޑႝྍႝᓸǶ܌ගрޑեᚇૻܫεᏔ

ޑᚇૻϩ݋җኧᏢ௢ᏤаϷໆෳ่݀ϕ࣬՘᛾ǶӧԜ܌ගрϐ13GHz

եᚇૻܫεᏔ٬Ҕ0.18

Pm 1P6Mߎ਼ъᇙำמೌჴ౜Ƕӧໆෳ่݀

΢Ǵቚ੻(S

21

)ࣁ13.2ϩنǵᚇૻࡰኧ(noise figure)ࣁ4.57ϩنǴаϷന

եᚇૻࡰኧ(F

min

)ࣁ4.46ϩنǶԜեᚇૻܫεᏔϐ႖๊(reverse isolation)

ёၲ-40ϩنǴӧᒡΕϷᒡрߔלϰଛௗեܭ-11ϩنǶӧጕ܄ࡋ೽

ҽǴቚ੻1ϩنᓸᕭᗺࣁ–11 dBm ᆶ Ο໘ϕፓѨ੿ᗺࣁ–0.5 dBmǶӧ

ٮᔈႝᓸ1ҷ੝ਔեᚇૻܫεᏔϐႝࢬ੃઻ࣁ10mAǶ

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ځԛǴගрΑ΋ঁడԯݢ৔ᓎϕံࠠߎ਼ъǵե LO ф౗ǵΐΜ

ࡋ࣬ՏৡǵѳᑽࢎᄬǵԾՉ໒ᜢ(self-switching)ޑႝࢬኳԄషᓎᏔǶ

ԜషᓎᏔޑಔԋǴҗ΋ঁᒡΕભޑӅ႔ཱུܫεᏔǵ΋ঁ࣪य़ᑈޑΐΜ

ࡋϩЍጕషӝጠӝᏔǵаϷߎ਼ъԾՉ໒ᜢ(self-switching)ޑး࿼Ƕ

90 ࡋϩЍጕషӝጠӝᏔ೏೛ीٰೀ౛ӧߚதଯᓎ΢ޑ৔ᓎᆶ LO ૻဦ

ޑ่ӝǶࣁΑჴ౜࣪य़ᑈޑ 90 ࡋϩЍጕషӝጠӝᏔǴ୷ܭ٠ᖄႝ৒ޑ

ଯߔלጠӝᏔݢᏤǴϩЍጕϷ through-line җচٰޑѤϩϐݢߏӚԾ෧

ϿࣁϤᗺѤϩϐݢߏᆶΜϩϐݢߏǶ܌ගрϐషݢᏔ٬Ҕ 0.13–m

1P8M

ߎ਼ъᇙำמೌჴ౜Ƕӧ 58GHz ф౗ࣁ 0dBm ϐ LO ૻဦΠǴ

ૈஒ 60–GHz ৔ᓎૻဦफ़Կ 2–GHz ύᓎૻဦǶӧ೭ԛ೛ीύǴԜషݢ

Ꮤϐൂᆄᙯඤቚ੻(single-end conversion gain)ࣁ 1 ϩنǴځᒡΕቚ੻ 1

ϩنᓸᕭᗺࣁ 2 dBmǶLO ᆶ RF ૻဦ႖๊ёၲډ–37 ϩنǴӧٮᔈႝ

ᓸ 1.2 ҷ੝ਔځႝࢬ੃઻ࣁ 3mAǶ

നࡕǴӧԜว߄π཰-ࣽᏢ-ᙴᏢௗԏᏔᏹբӧ 24GHzǶԜௗԏᐒ

җ΋ঁեᚇૻܫεᏔǵ৔ᓎషᓎᏔǵIF షᓎᏔǴޔࢬୃ౽ံᓭǵႝᓸ

௓ڋਁᕏᏔǵаϷ΋ঁନΒႝၡǶӧፕЎಃ΋೽ҽ܌ගϷޑեᚇૻܫ

εᏔǴӧଅ᝘നλޑᚇૻΠҔٰܫεӧٿԭѤΜሹᇲ૟ޑ৔ᓎૻဦǴ

аቚεௗԏૻဦᆶᚇૻ໔ޑৡຯǶ೏ቚεޑٿԭѤΜሹᇲ૟ޑ৔ᓎᒡ

Εૻဦӆ࿶җፕЎಃΒ೽ҽ܌ගϷޑ৔ᓎషᓎᏔफ़ᓎԿΖΜሹᇲ૟ޑ

IF

ᓎࢤǶᒿࡕޑ IF షᓎᏔϩԋ฻࣬ՏᆶΐΜࡋ࣬Տৡٿచၡ৩Ǵע IF

ᓎ౗ޔௗफ़ᓎԿ႟ǶԜٿ୷ᓎૻဦӆճҔޔࢬୃ౽ံᓭႝၡٰ੃ନӧ

IF

షᓎᏔᒡрᆄҗ LO Ծيషᓎ܌ౢғޑޔࢬୃ౽Ƕ܌ගрϐௗԏᏔ

٬Ҕ 0.13–m 1P8M ߎ਼ъᇙำמೌჴ౜ǴԜௗԏᏔϐቚ੻ࣁ 19.5 ϩ

نǵᚇૻࡰኧࣁ 15 ϩنᆶᒡΕߔלϰଛ(S

11

)ࣣեܭ-13 ϩنǶځᒡΕ

ቚ੻ 1 ϩنᓸᕭᗺࣁ–25dBmǶӧٮᔈႝᓸ 1 ҷ੝ਔځႝࢬ੃઻ࣁ

35mAǶ

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܌ගрޑ৔ᓎႝၡϷௗԏᐒ߻ᆄႝၡ࣬ߞૈ፾Ҕܭ೛ीଯᓎǵଯਏ

ૈǵեႝᓸǵଯ᏾ӝࡋǵӄߎ਼ъޑడԯݢคጕ೯ૻس಍Ƕӧ҂ٰ཮

ӧԏวᐒ΢଺׳຾΋؁ޑࣴزǶ

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The Analysis and Design

Of

CMOS Current-Mode RF Receiver Front-End

Integrated Circuits

StudentǺFadi Riad Shahroury AdvisorǺChung-Yu Wu

!

Department of Electronic Engineering Institute of Electronics

National Chiao Tung University

ABSTRACT

In this thesis, the design methodologies and implementation techniques of low-voltage current-mode high-frequency RF front-end circuits are presented. There are three parts in this thesis, including (1) the modeling, design, and analysis of low-noise amplifier utilizing the technique of capacitive feedback matching network; (2) the design and analysis of low LO-power quadrature balanced self-switching current-mode mixer; (3) the design and analysis of a 1-V current-mode front-end receiver with on chip LO signal generator and DC-offset compensation circuit at 24-GHz RF application.

At first, a new input impedance power matching technique for LNA is proposed and analyzed, In the proposed technique, the gate-drain capacitor of the input common-source amplifier and the capacitive feedback matching network are used to implement a real input impedance in order to match with the input source impedance. Thus the technique is called technique of capacitive feedback matching network. By using this technique, the minimum noise figure and maximum power gain can be

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achieve simultaneously, furthermore, it can be used with very low supply voltage without degraded the linearity. The full noise analysis of LNA utilizing the proposed technique is supported by mathematical derivations and it is complemented and validated by measurements. Where, the proposed LNA which is implemented in a 0.18–m 1P6M CMOS technology is operated at the frequency of 13 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse

isolation S12 of the LNA can achieve –40 dB and the input and output return losses are better than –11 dB. The input 1-dB compression point is –11 dBm and IIP3 is –0.5 dBm. This LNA drains 10 mA from the supply voltage of 1 V.

Secondly, mm-wave RF CMOS low LO-power quadrature balanced self-switching current-mode mixer is proposed. The mixer consists of common-gate amplifier as input stage, an area efficient 90-degree branch-line hybrid coupler, and CMOS self-switching current-mode devices, the 90-dgree branch-line hybrid coupler is designed to deal with the issue on the combination of RF and LO signals at very high frequency, in order to implement area efficient 90-dgree branch-line hybrid coupler, the branch-line and the through-line lengths of the hybrid are reduced from lamda/4 to lamda/6.4 and lamda/10, respectively, based on the methodology of a high-impedance coplanar waveguide with shunt lumped capacitors. The proposed mixer, using 0.13–m 1P8M CMOS technology, can down-convert 60–GHz RF signal to 2–GHz intermediate frequency (IF) signal, with a LO power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1dB and an input-referred 1dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve –37dB while using 3 mA from a supply voltage of 1.2V.

Finally, Industrial-Science-Medical (ISM) receiver operates at 24 GHz is proposed. The receiver consists of transconductance low-noise amplifier (TLNA), RF current-mode mixer, IF current-mode mixers, DC-offset compensation, voltage control oscillator (VCO), and quadrature divided-by-two circuit (QD2). The TLNA proposed in

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the first part of the thesis is used to amplified the RF input spectrum at 24 GHz with minimal noise contribution to enlarge the power difference between the received signal and noise, then the amplified RF input spectrum at 24 GHz is down-converted to an intermmediate frequency (IF) of 8 GHz by using RF current-mode mixer proposed in the second part of the thesis, and a follow-up IF current-mode mixers are used in-phase I and quadrature Q paths to directly convert the spectrum at IF frequency to zero frequency. The baseband signals are then applied to the DC-offset compensation circuit to eliminate DC-offset currents appear at the output of the IF current-mode mixer due to the self-mixing of the LO. The fabricated circuit in 0.13–m 1P8M CMOS technology demonstrates a conversion gain of 19.5 dB, and noise figure of 15 dB, while maintaining an input return loss better than –13-dB. The input-referred 1dB compression point of –25 dBm is measured. This receiver drains 35 mA from the supply voltage of 1 V.

It is believed that the proposed RF circuits and receiver front-end can be applied to the design of high-frequency high-performance low-voltage high-integration all-CMOS wireless communication systems. Future research on transceiver components will be conducted in the future.

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ACKNOWLEDGEMENTS

I would like to express my sincere gratitude to my supervisor, Professor Chung-Yu Wu, President of National Chiao-Tung University, of the thesis, for his continuous sup-port, guidance, encouragement, and involvement during this research. His help is greatly appreciated.

I feel a deep sense of gratitude to my parents, my sisters, and my brothers, for their continuous prayers and encouragement during the course of this work. Without them I cannot achieve my success today.

At National Chiao-Tung University, I am in debt to all who provided support. Special thanks are also due to the fellow graduate students of the Department of Electronics. I wish to thank the following Professors : Prof. Ming-Dou Ker; Prof. Jieh-Tsorng Wu; Prof. Chien-Nan Kuo (for helpful discussions); Prof. Robert Hu (for his wonderful course on microwave circuit and helpful discussions); and Prof. Chao, Hsueh-Yung (for introducing HFSS simulator, which help me a lot in my research).

I had the pleasure of meeting my colleagues in ALab. They are wonderful people all gave me the feeling of being at home. I want to thank them for all their help, support, interest, and valuable hints. Especially Chung-Yun Chou, Wen-Chieh Wang, Chi-Yao Yu, Zue-Der Huang, Hsuan-Yi Su, and Shun-Wei Hsu.

Financial support was provided by National Chiao-Tung University in the form of Research Assistantship and in the form of a graduate Scholarship, and by National Chip Implementation Center (CIC) & National Science Council (NSC), in the form of fabrication of the testing chips. I would like to thank the National Nano Device Laboratories (NDL) staﬀ for both technical support and measure the chips performance, and Ansoft staﬀ in Taiwan for their design environment tools.

Fadi R. Shahroury, Taiwan, Hsin-Chu, August, 8, 2008.

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To My Dear Family & Friends

“I saw that no man writes a book in his day

but said in a next day: if this was changed, it

will be good. If this was added, it will be better.

If this was forward it will be the best. If this was

left, it will beautiful. This is the eloquent proof,

which is evidence of the shortage of human

be-ings.”

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List of Tables

2.1 Comparison of receiver architecture. . . 22 2.2 Summary of recent CMOS LNA results. . . 23 2.3 Summary of recent high-frequency CMOS mixer results. . . 24 3.1 The measured performance parameters of the fabricated LNA and

compar-isons with other published LNAs. . . 56 4.1 The performance summaries of the proposed mixer and comparisons with

other published mixers. . . 73 5.1 The measured performances and comparisons results of published 24-GHz

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List of Figures

1.1 Wireless communication landscape. . . 6

1.2 The unlicensed bandwidth available at 60 GHz. . . 7

1.3 The scenarios for short-range and long-range backbone wireless communi-cation networks for home-RF applicommuni-cations. . . 8

1.4 The reduction of supply voltage and threshold voltage in accordance with the scaling of channel length of CMOS technologies. . . 9

2.1 The block diagram of the homodyne, direct-conversion, or zero-IF receiver. 25 2.2 Two sources of DC oﬀsets in the direct-conversion receiver. . . 26

2.3 The block diagram of the heterodyne or IF receiver. . . 27

2.4 The block diagram of the Hartley receiver. . . 28

2.5 The block diagram of the Weaver receiver. . . 29

2.6 The block diagram of the wideband-IF receiver. . . 30

2.7 The block diagram of the low-IF receiver. . . 31

2.8 Spectra ﬂow of the low-IF receiver. . . 32

2.9 The block diagram of the double-quadrature receiver. . . 33

2.10 Spectra ﬂow of the double-quadrature receiver. . . 34

2.11 a) The common-source ampliﬁer as the input stage, b) The common-source ampliﬁer with source degeneration inductor. . . 35

2.12 The schematic diagram of 3-stage common-source LNA. . . 36

2.13 The schematic diagram of cascode LNA. . . 37

2.14 The schematic diagram of Common-gate with resistive feedback (CGRF)LNA. 38 2.15 The schematic diagram of single-balanced mixer Gilbert cell mixer. . . 39

2.16 The schematic diagram of single-balanced mixer with current bleeding. . . 40

2.17 The schematic diagram of Cascade mixer. . . 41

2.18 The schematic diagram of transconductance mixer. . . 42

2.19 The schematic diagram of transconductance quadrature balanced mixer with hybrid combiner. . . 43

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2.21 The schematic diagram of gate-pumped resistive mixer. . . 45

2.22 The schematic diagram of resistive mixer. . . 46

3.1 The common-source ampliﬁer as the input stage. . . 57

3.2 The small-signal equivalent circuit for noise calculations. . . 58

3.3 The design steps for capacitive feedback matching network LNA. . . 59

3.4 The complete circuit diagram of proposed LNA. . . 60

3.5 The measured and simulated S₁₁ and S₂₁ results of the proposed LNA. . . 61

3.6 The measured and simulated S₂₂ and S₁₂ results of the proposed LNA. . . 62

3.7 The measured stability K-factor and B-factor of the proposed LNA. . . 63

3.8 The measured and simulated noise ﬁgure N F and minimum noise ﬁgure N Fmin of the proposed LNA. . . 64

3.9 The LNA measurement results of Pin versus Pout. . . 65

3.10 The LNA measurement results of two-tone test. . . 66

3.11 The chip photograph of the proposed LNA utilizing the technique of capac-itive feedback network. . . 67

4.1 The circuit diagram of self-switching current-mode mixer. . . 74

4.2 The 4m+1-point analysis applied on HSPICE simulated of ac current gain. 75 4.3 circuit diagram of CMOS quadrature balanced current-mode mixer. . . 76

4.4 (a) Quarter-wavelength transmission line; (b) Shorted transmission line equiv-alent to the quarter-wavelength transmission line; (c) Coplanar waveguide. 77 4.5 The chip photograph of fabricated current-mod quadrature balanced down-conversion mixer. . . 78

4.6 The measurement setup for the diagram 60 GHz down-conversion mixer setup. 79 4.7 The measured and simulated IF output power versus RF input power. . . . 80

4.8 The measured and simulated conversion gain versus LO power. . . 81

4.9 The measured LO-RF isolation characteristics. . . 82

5.1 The block diagram of the 24-GHz current-mode receiver front-end. . . 94

5.2 The circuit diagram of the TLNA. . . 95

5.3 The simpliﬁed circuit diagram of the self-switching mode RF current-mode mixer. . . 96

5.4 The circuit diagram of the double-balance self-switching current-mode RF current-mode mixer. . . 97

5.5 The simulated gain of TLNA with and without notch ﬁlter. . . 98

5.6 The circuit diagram of the quadrature IF current-mode mixers. . . 99

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5.8 The sensitivity of the rectiﬁer circuit to the variation of the M52 width. . . 101

5.9 The circuit diagram of VCO with quadrature divided-by-two circuit. . . 102

5.10 The interconnections within the circuits in the receiver are simulated by HFSS.103 5.11 The chip micrograph of the fabricated current-mode receiver front-end. . . 104

5.12 The measured and simulated input reﬂection coeﬃcient of the proposed receiver. . . 105

5.13 The measured gain and N F of the proposed receiver. . . 106

5.14 The receiver measurement results of Pin versus Pout. . . 107

5.15 The measured and simulated tuning range of the VCO. . . 108

5.16 The microphotograph of the VCO and quadrature divided-by-two circuits after laser-cut . . . 109

6.1 National Chiao Tung University on-waver probe analytical station test setup 2008. . . 114

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Chapter 1 INTRODUCTION

1.1 Background

In the late of 1990s, wireless communications represent a major step forward in the dra-matic story that began ten years earlier with the arrival of cellular and cordless telephones. When people spend billions of dollars to buy and use these new kinds of telephones, they demonstrate a strong desire to control their information. Mobility is at the heart of wireless communications, people transmit and receive information wherever they are and whenever they choose, even when they are moving. They want to produce and acquire information in formats they choose, including sounds, text, still pictures, moving pictures, keyboard operations, mouse movements, and pen strokes. The promise of wireless communications is to make all kinds of information available anywhere, anytime, at low cost to a large mobile population.

Although this promise has widespread appeal, practical systems that deliver it remain several years in the future, At the moment, Bluetooth, HiperLAN, HiperLAN/2, Wireless Personal Area Network (WPAN), Wireless Local Area Network (WLAN), Ultra-Wideband (UWB), WiMAX, etc. have a collection of services, each capable of performing some of the goals of the wireless communications. However, to achieve the aftermentioned goals, this needs access network with very high capacity. High data-rate requires broad frequency bands, and a suﬃciently broadband spectrum can be obtained in the high GHz regime (> 10 GHz) such as 24 GHz (K–Band) and 60 GHz (V–Band)as shown in Fig. 1.1. The high GHz regime oﬀers several advantages

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1. Providing in general high bandwidth and clean RF spectrum with low cast. For example, the Federal Communications Commission (FCC) has allocated the 24-GHz frequency band for unlicensed industrial, scientiﬁc, and medical (ISM) application. Where for the 60-GHz frequency band is largely globally available, and a large amount of spectrum is available on an unlicensed basis in many regulatory domains as shown in Fig. 3.5.

2. Large spectral capacity and compact benefits of reduced co-channel interference pro-viding dense, short reach (1 km) wireless communication due to shorter cell re-use dis-tance [1], as well as access to worldwide allocated nonregulatory frequency bands [2]. 3. Supporting system-on-chip designs. With the high-frequency of operation, passive components such as transmission lines, RF combiner, passive filters, and even anten-nas, can be efficiently implemented on chip [3–12].

Fig. 1.3 shows such scenarios with clusters for short ranges and a long range backbone wireless communication networks for home-RF applications at 17 GHz, 24 GHz, and 60 GHz in the near future. Although the standardizations of both applications have not been accomplished, the possibilities of new mass wireless market lead to the interest of the communication industries.

To implement new hardware for wireless communication systems, low manufacturing costs are of paramount importance to be competitive in the stringent wireless markets. Thus, the goal of the designers of personal wireless communicational devises is to design a low cost communicational device with high performance. To reach this goal, highly in-tegrated semiconductor chips must be design, so both of the analog RF front-end and the digital baseband signal processing should be design on the same die without any external components. Due to their high unit current gain frequency (f_T) and maximum operating (or oscillation) frequency (fmax) SiGe(C), BiCMOS, and III-V technologies are used to realize analog RF front-end circuits. However, these technologies suﬀer from high cost and great diﬃculties to integrate with complex digital systems which are usually realized by CMOS technologies. Driven by the development trend of highly integrated semicon-ductor chips for wireless communication system, research on the CMOS RF front-end has accelerated.

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With the continual scaling down of CMOS technology, a transit frequency (fT) of up to 400GHz has been reported in sub-10nm technology nodes [13]. As a result, the CMOS tech-nology has become a potential choice for the implementation of high-frequency front-end circuits. Furthermore, nanometer RF-CMOS technology oﬀers high quality factor of pas-sive components, like transmission lines and inductors, have been provided by the thicker metal in the highest metallization layers. Besides nanometer CMOS technology oﬀers great potential to achieve high performance, small chip area, low cost, low power dissipation, and long battery life-time for implementing analog and digital parts of baseband signal processing of potable devices.

The aggressive of scaling down of CMOS technology has prominent effects on supply voltage, where the maximum supply voltage is significantly reduced. Unlike the supply voltage, the threshold voltage of MOSFET devices (VT) is reduced at a slower pace, as shown in Fig. 1.4. As results, the effective gate voltage (VGS − VT) becomes small. In digital circuits this increases the leakage current and delay time of the logic circuits. While, in analog circuit, the intrinsic gain of the MOSFET devices is reduced, due to fact that effective gate voltage is directly proportioned in MOSFET devices to transconductance (gm). Moreover, with low–voltage, the required linearity of the RF circuits is hard to achieve. Consequently, the performance of the entire RF front-end will degrade. This situation would become worse and worse as CMOS technologies continue to scale down.

1.2 Research Motivation

Motivated by the issues arise from the continually scaling of CMOS technology on RF circuits, the study on exploring new diﬀerent circuit topologies and design techniques is presented in this thesis. The newly low-voltage fully integrated CMOS circuits, which can be adopted for high GHz regime (> 10 GHz) RF front-end receivers, are designed, analyzed, and measured. Furthermore, a fully integrated 1-V current-mode front-end re-ceiver with on chip LO signal generator and DC oﬀset compensation circuit at 24-GHz RF application, is designed, analyzed, and measured by using the proposed circuits and techniques in this thesis.

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1.3 Organization Of This Thesis

This thesis contains six chapters, which include analyses, designs, and implementations of CMOS low-noise ampliﬁer (LNA), CMOS down-conversion mixer, and ISM RF front-end receiver.

Chapter 1 introduces the background, describes the research motivation, and explains the main topics of this thesis.

In Chapter 2, begins with brief introductory overviews of receiver architectures. The key building blocks of RF receiver front-end is also discussed. The performance of the CMOS high-frequency front-end circuits in the public domains is reviewed.

In Chapter 3, the technique of capacitive feedback matching has been presented to design an RFIC LNA, where the presented technique can be used with very low–voltages to achieve maximum power-gain and minimum NF simultaneously at any given amount of power dissipation. The full noise analysis of the LNA is supported by mathematical derivations and it is complemented and validated by measurements.

In Chapter 4, the design of low LO-power mm-wave RF CMOS quadrature balanced self-switching current-mode mixer has been presented, The presented mixer has high linear-ity with low-voltage supply, Besides, an area eﬃcient 90-dgree branch-line hybrid coupler is designed to deal with the issue on the combination of RF and LO signals at mm-waves frequencies.

In Chapter 5, 1-V current-mode front-end receiver with on chip LO signal generator and DC offset compensation circuit at 24-GHz RF application, is designed, and analyzed. The receiver composes of a transconductance low noise amplifier (TLNA), RF current-mode mixer, IF current-current-mode mixers, DC offset compensation, voltage control oscillator (VCO), and quadrature divided-by-two circuit(QD2). The TLNA proposed in presented in chapter 3 is used to amplified the RF input spectrum at 24 GHz with minimal noise contribution to enlarge the power difference between the received signal and noise, then the amplified RF input spectrum at 24 GHz is down-converted to an intermmediate frequency (IF) of 8 GHz by using RF current-mode mixer presented in chapter 4, and a follow-up IF current-mode mixers are used in-phase I and quadrature Q paths to directly convert the

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spectrum at IF frequency to zero frequency. The baseband signals are then applied to the DC oﬀset compensation circuit to eliminate DC oﬀset currents appear at the output of the IF current-mode mixer due to the self-mixing of the LO.

Finally, the main results and conclusions of this thesis are summarized in Chapter 6. Some suggestions and future works about the implementations of current-mode receiver.

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Figure 1.3: The scenarios for short-range and long-range backbone wireless communication networks for home-RF applications.

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Figure 1.4: The reduction of supply voltage and threshold voltage in accordance with the scaling of channel length of CMOS technologies.

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Chapter 2 REVIEWS ON FRONT–END

RECEIVERS, LOW–NOISE

AMPLIFIERS, AND MIXERS

Because of the impossibility of digitizing RF spectrum at high GHz regime (> 10 GHz), The RF spectrum should be down-converted to a low frequency. Besides, all the unwanted RF signals adjacent to wanted RF spectrum have to be suppressed, so that they do not eﬀect the operation of the down-converted devices. Moreover, in order to obtain the highest possible performance, the RF spectrum has to be ampliﬁed before it down-converted to minimize the noise contribution of the down-converted devices. All these tasks are what must be carried out by receiver.

From the above tasks the receiver should have an RF amplifier that can amplify the RF input spectrum with minimal noise contribution to enlarge the power difference between the received signals and noise. This amplifier is known as low-noise amplifier (LNA), and a down-converted device to change the center frequency of the RF spectrum, this device is known as mixer. In addition, to eliminating the interference of unwanted signal on the wanted RF, extra building blocks are required depending on the architecture of the receiver. In the following sections, it will be attempted to present the most important receivers architectures, Moreover, a brief overview of LNA and mixer circuits implemented in CMOS technology at high GHz regime will be described.

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2.1 Receiver Architectures

2.1.1 Homodyne, Direct–Conversion, or Zero–IF Receiver

In a homodyne or direct-conversion receiver (DCR) which is depicted in Fig. 2.1 [14–21], the desired RF signal is directly down-converted to zero-IF in one-step frequency mixing with single LO signal. Therefore, in this type of the receiver, the LO frequency is equal to the RF frequency. The baseband signal is then ﬁltered with a low-pass ﬁlter to select the desired channel.

For frequency- and phase-modulated signals, the down-conversion must provide quadra-ture outputs in order to avoid loss of signal information. The main advantage of DCR is that is does not possess the image problem when the incoming RF signal is directly down-converted to baseband without any IF stage. Another advantage is its simple architecture. However, the major disadvantage is DC offsets [22]. As shown in Fig. 2.2, the severe DC offsets can be generated at the output of the mixer when the leakage from the local os-cillator is self-mixed with LO signal. The second source of DC offsets is the large nearby interferers leaking to the VCO and then self-mixing. This effect could saturate the fol-lowing stage. The DC offsets can be removed by capacitive coupling. However, the signal power near DC will be lost. Hence, the size of capacitors should be chosen quite large. Feedback loops from the baseband or the digital part are also proposed to reduce the DC offsets. But these methods will increase the complexity of the direct-conversion receiver.

Equally critical is the flicker noise of the mixer since the mixer output is the baseband signal and can be easily corrupted by large noise. It is because that the flicker noise of active devices becomes the dominant noise source as the frequency below 1 MHz. The flicker noise should be considered in designing DCR. Active devices with large dimension can be chosen to reduce flicker noise. In addition, PMOS contributes less flicker noise than NMOS.

2.1.2 Heterodyne or IF Receivers

The most straightforward receiver architecture for implementing a cellular receiver front-end is evidently the heterodyne receiver, which is shown in Fig. 2.3 [23–28]. The

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main feature is the use of an Intermediate Frequency (IF). For this reason, the heterodyne is often also called the IF receiver.

The received RF signals from the antenna are first filtered by a band select filter, BPFRF1, which suppresses interferences residing outside of the application band. By removing these out-of-band blocking signals, which could saturate the following stages, the requirement of the dynamic range of the receiver can be relaxed considerably. A low noise amplifier (LNA) amplifies the received RF signals, which are then filtered by an image-reject filter, BPFRF2, to remove the image. The image has an offset of twice the intermediate frequency by the mixer. The received RF signals after BPFRF2 are down-converted to IF by the down-conversion mixer, and then passed through the channel-select filter BPFIF to remove the interferences at the adjacent channels. Finally, the channel-selected is demodulated into baseband I/Q signals to retrieve the desired signal information. The high-frequency noise and distortion from inter-modulation and high-order harmonics are removed by baseband low-pass filter LPFBB.

In the frequency translation, both the desired signal and image signal are mapped to the IF frequency after mixing. Although the image-reject filter BPFRF2 is used to attenuate the image signal, suitable attenuation of the image may not be practical unless the IF frequency is selected relatively high. The trade-off is that filtering at a high IF requires more complicated filters in order to maintain selectivity. It is difficult to realize an on-chip high-Q filter at the RF frequency. The required high-Q, high frequency image-reject filter is therefore placed off-chip. Consequently, the integration ability of the heterodyne or IF receiver is limited, and the cost is increased because of several off-chip filters are needed. Additional buffers to drive off-chip filters also require high power and reduce the gain of this kind of receivers.

The path mismatch is implied not a big issue because the image rejection does not rely on any matching between two signal paths, but is mainly done by the image-reject filter. Also LO feed-through and DC offset do not affect the signal quality since the desired signal frequency is never close to these frequencies. The same applies to self-mixing of either RF or LO signal. Another important property is that the channel selection occurs before the ADC. Hence, the ADC only requires handling minimum dynamic range. Due to the

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bandpass nature of the channel, even the sub-sampling ADC can be used. Additionally, the number of bits can be kept low since both the out-of-band and in-band blocking signals have already been removed.

2.1.3 Image–Reject Receiver

The primary advantage of the image-reject receivers [29–33] is that they do not need image-reject filters. Without the image-reject filters, the IF frequency can be placed very low to reduce the design difficulty of the IF channel-select filter. Hartley [32] and Weaver [33] receivers are two famous image-reject receivers.

The architecture of Hartley receiver is shown in Fig. 2.4. The desired signal and the image signal are down-converted in both upper and lower paths. However, the desired signals at the points B and C are in-phase, while the image signals at the points B and C are out-of-phase. When the spectrum at the points B and C are combined, the image signals will be cancelled and the desired signals will be left.

The architecture of Weaver receiver is shown in Fig. 2.5. The Weaver receiver is diﬀerent from the Hartley in that the quadrature mixers are used to the replace 90-degree phase shifter in the signal path. The purpose of this replacement is to perform phase shifting not on the signal path, but on the second LO which is only a single sinusoidal tone. Therefore, the phase shifting accuracy can be well controlled.

The Image-Reject Ration (IRR) of the Hartley and Weaver receivers is limited by the gain mismatches between I- and Q-path, the phase inaccuracy of quadrature LO signals, and the imperfect quadrature phase shifting. The IRR can be expected by

IRR = 1 + (1 + ε)

2_{− 2(1 + ε) cos(θ)}

1 + (1 + ε)2+ 2(1 + ε) cos(θ) (2.1.1) where ε and θ are the gain and phase mismatch, respectively. For ε = 5% and θ = 5◦, the IRR is 26 dB. Existing implementations of image rejection receivers typically achieve 30∼ 40 dB for image rejection.

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2.1.4 Wideband–IF Receiver

Shown in Fig. 2.6 [34, 35] is the architecture of wideband-IF receiver. The architecture of this receiver is similar to a combined technique of heterodyne receiver and Weaver image-reject receiver. In heterodyne receiver in Fig. 2.3, the channel selecting is performed using the RF local oscillator. However, the wideband-IF receiver uses a fixed RF local oscillator at the first mixing stage, and the entire received bands are translated to the fixed IF. In the second mixing stage, a tunable IF local oscillator is used to select the desired channel from the received entire bands, and the desired channel is translated to the baseband. Simultaneous image rejection is performed in the second mixing stage which uses quadrature frequency conversion.

Since the RF local oscillator is at fixed frequency, the phase noise performance of the oscillator can be optimized. Besides, it is relatively easier to design the IF VCO with a low phase noise. Nevertheless, the disadvantage is that the blocking signals at adjacent channels are translated to the baseband without filtering. Hence, the dynamic range or linearity shall be carefully considered. Take the linearity requirement into consideration, the gain of the receiver is mostly provided from the IF section. Leaving the gain to the IF section may increase the Noise Figure of the receiver. Besides, the image signal still interferes with the desired signal if I- and Q-path at the first stage have mismatches. Sometimes, an off-chip RF filter is required for high IRR.

2.1.5 Low–IF Receiver

The architecture of low-IF receiver is shown in Fig. 2.7 [36–38]. The low-IF receiver combines the advantage of heterodyne and direct-conversion receivers. The desired RF sig-nals are down-converted to IF in one mixing step, which is similar to the direct-conversion receiver. Since the IF is higher than DC, DC offsets and flicker noise do not affect the desired signals. In low-IF receivers, poly-phase filters are used to remove the image; hence, the high-Q image-reject filter is not required. Because the polyphase filters are operated at the low intermediate frequency and are possible to be realized on-chip, low-IF receivers are obvious to have better integration capability than heterodyne receivers.

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The IRR of the low-IF receiver is limited by the gain mismatches between I-path and Q-path, phase inaccuracy of the quadrature LO. The spectra flow of the low-IF receiver before and after down-conversion is shown in Fig. 2.8. The spectrum of complex signal (I+jQ) is represented. SIGpRF and IMpRF represent the spectrum of the desired signals and image signals. LOp represents the spectrum of the quadrature local oscillator. However, SIGnRF and IMnRF represent the crosstalk image signals of SIGpRF and IMpRF, respectively. LOn represents the crosstalk image signal of LOp. After the frequency conversion, the SIGpRF, SIGnRF, IMpRF, and IMnRF are down-converted to SIGnIF, SIGpIF, IMpIF, and IMnIF, respectively. As shown in Fig. 2.8, the image IMpIF mixes with the signal SIGpIF at the positive IF frequency ωIF, and hence cannot be removed following polyphase filter. Only the signals IMnIF and SIGnIF at the negative IF frequency −ωIF can be removed by the following polyphase filter. Since mismatches in RF circuits are inevitable even in modern IC process, it is difficult to achieve high IRR without special and complicated techniques for low-IF receivers.

2.1.6 Double–Quadrature Receiver

Shown in Fig. 2.9 [39–41] is the architecture of Double-Quadrature Receiver (DQR) which is used to improve the IRR. The DQR shifts the phase of RF signal to quadrature and then the quadrature RF signals are downconverted to IF signals by mixing with quadrature LO signals. The DQR is less sensitivity to the imbalance of LO signals of I- and Q-path because the RF and LO signals are both put into quadrature phases. Since the RF signals are down-converted to IF, it is also immunity from the problem of DC oﬀsets and ﬂicker noises.

The spectra ﬂow of the DQR before and after down-conversion is shown in Fig. 2.10. The spectrum of complex signal (I+jQ) is represented. SIGp_RF and IM pRF represent the spectrum of the desired signals and image signals at the output of the quadrature generator.

LOp represents the spectrum of the quadrature local oscillator. However, SIGnRF and

IM nRF represent the crosstalk image signals of SIGpRF and IM pRF, respectively. LOn represents the crosstalk image signal of LOp. After the frequency conversion, the SIGpRF,

SIGnRF, IM pRF, and IM nRF are down-converted to SIGnIF, SIGpIF, IM pIF, and

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IM pIF mixes with the signal SIGpIF at the positive IF frequency ωIF, and hence cannot be removed following polyphase filter. Only the signals IM nIF and SIGnIF at the negative IF frequency −ωIF can be removed by the following polyphase filter. However, the main difference between DQR and low-IF receiver can be seen from the value of IM pIF of DQR which can be represented as

IM pIF = IM nRFLOp(ISRQGISRLO+ ISRmixers) (2.1.2) where ISRQG, ISRLO, and ISRM ixers denote the Image-to-Signal Ratio (ISR) of the quadrature generator, the local oscillator, and mixers, respectively. For ISRQG, ISRLO, and ISRM ixers 1, the ISRQGISRLO term in (2.1.2) is negligible relative to ISRM ixers Therefore, IM pIF is determined by the gain/phase errors of the mixers and IM nRFLOp The DQR exhibits better image-reject performance than the conventional low-IF receiver, because IMpIF is smaller and almost unaﬀected by ISRLO. To achieve high IRR of the DQR, the symmetry of the layout in mixers between I/Q-paths should be regarded as reducing the amplitude of crosstalk image signals. Additionally, the polyphase ﬁlter must have a high capacity for rejecting images at the intermediate frequency.

The comparisons of the afore-mentioned receiver are listed in Table 2.1. The hetero-dyne receiver can achieve the best performance because it is immunity from the problem of I/Q-mismatches, DC offset and flicker noise. The expenses of the heterodyne receiver are high power consumption and poor integration ability. The DCR has the advantage of high integration ability and low-power consumption. However, the high performance is difficult to achieve because of the problems of DC offsets and flicker noise. Image-rejection, wideband-IF, and low-IF receivers achieve better performance than direct-conversion re-ceiver, but the imbalance of LO signals will limit the IRR. Hence, off-chip high-Q RF filters are still required for high IRR. The DQR down-converts the RF signal to IF, so it will not be affected by DC offsets and flicker noise. Besides, the DQR is less sensitive to I/Q-imbalances, and off-chip high-Q RF filters are not required.

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2.2 CMOS Low–Noise Ampliﬁers

The Low-Noise Ampliﬁer (LNA) is one of the most important and critical parts in the receiver front-end. It is the ﬁrst active circuit in the receiver part following the antenna as shown in Fig. 2.3, Due to its location in the receiver chain, it dominates the noise performance of the complete system.

In the design of RF-CMOS LNAs, it is known that the key performance parameters are power-gain and noise ﬁgure (N F ) besides the stability, linearity and isolation. The goal of LNA design is to achieve maximum power-gain and minimum N F simultaneously at any given amount of power dissipation. To reach this goal, the input impedance (Zin) of a LNA must be kept close enough to the optimum source noise conjugate impedance (Z_n,opt∗ ). In order to illustrate the diﬃculties in achieving the above goal at frequencies above 10 GHZ, we study a number of CMOS LNAs circuit topologies.

Consider the common-source stage shown in Fig. 2.11(a) [42–46]. the Zin and Zn,opt of M1 are given as [47]: Zin = 1 jωCgs (2.2.1) Zn,opt = α2δ 5γ (1− |c|2) + j 1 + α|c| δ 5γ ω(Cgs + Cgd) α2 δ 5γ(1− |c| 2_{) +}_{1 + α}_|c| δ 5γ 2 (2.2.2) where ωo is the operating angular frequency, Cgs is the gate-source capacitance of MOSFET device, γ is the thermal noise coeﬃcient, δ is the gate induced current noise factor, c is the correlation coeﬃcient theoretically equal to j0.395 [48], and α ≡ gm/gd₀ where gd₀ is the zero-bias drain conductance.

By comparing (2.2.1) and (2.2.2), it can be seen that the optimum source impedance for input matching is inherently diﬀerent from that of the noise matching in both real and imaginary parts. Thus, one cannot obtain both input matching and minimum NF simultaneously. For this reason N F of CS topology is generally high.

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In Fig. 2.11(b), source degeneration inductor introduces a real part into the input impedance seen looking into the gate of M2. It is not hard to show that input impedance of M2 has the following form:

Zin = jωLs+ 1 jωCgs + gm Cgs Ls (2.2.3) While the Zn,opt can be expressed as [49]:

Zn,opt = α2δ 5γ (1− |c|2) + j 1 + α|c| δ 5γ ω(Cgs+ Cgd) α2 δ 5γ(1− |c| 2_{) +}_{1 + α}_|c| δ 5γ 2 − jωLs (2.2.4)

As can be seen from (2.2.3), the source degeneration generates the real part at the input impedance. This is important because there is no real part in Zin without degeneration, while there is in Zn,opt. Therefore, if not excessive, Ls helps to reduce the discrepancy between the real parts of Zn,opt and of Zin the LNA [50–59]. Furthermore, from (2.2.3), the imaginary part of Zin is changed by jωLs, and this is followed by the same change in

Zn,opt, as shown in (2.2.4).

For stability reason [47], the drain of the input stage common-source should be con-nected to the low input impedance node. This inevitably decreases the power gain of the LNA, To retain the power-gain, multi-stage CS amplifiers topology is used in [44–46,50–56], The 3-stage common-source amplifier used for K-band in [55, 56] is shown in Fig. 2.12. In Fig. 2.12, source-degeneration inductor at first stage provides minimum noise figure with a real input impedance. In order to increase the stability of the LNA the source-degeneration inductor at following stages is used to provide low impedance. This topology is suitable for low–voltage application [44, 51–53]. However it consumes large power.

Another method of providing stable CS amplifier is illustrated in Fig. 2.13 [42,43,57–59]. The gate amplifier is often used as cascade in the combination with the common-source amplifier, since the common-gate amplifier has low input impedance when it is driven from the current source, it can pass current through it to the load with near unity current gain. However, the difficulties in this topology are twofold. First, the pole at the

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drain of M1 of the cascade LNA, as shown in Fig. 2.13, shunts a considerable portion of the RF current to ground, thereby lowering the gain and raising the noise contributed by M2. Second, with low–voltage, the cascade LNA has low linearity because of the required large voltage headroom.

Although common-gate (CG) ampliﬁer can be design to exhibit an real input resistance for input power match at mm-wave [60], the minimum N F and maximum power-gain cannot be achieved simultaneously. Due to the constrains of the input matching, the common-gate LNA has a lower bound of N F equal to 1 + γ for perfect match, where γ is the channel thermal noise coeﬃcient.

A Common-gate with resistive feedback (CGRF) topology shown in Fig. 2.14 [61]. In This topology an external resistance Rp is added to the traditional CG LNA in parallel with the input transistor to improve its noise performance. In order to implement Rp, shunt inductor Lshuntis used, while Cshuntis used to isolate the DC level of the source and drain. However, an extra area is required to implement Lshunt. Table 2.2 summarizes the performance parameters of the recent studies CMOS LNAs dating from 2001-2007.

2.3 CMOS Mixers

To recover the information carried by the RF spectrum at high frequencies, the down-conversion mixer converts the input RF spectrum at high frequencies to an intermediate frequency (IF) at the output through the use of a local oscillator signal (LO). Since the mixer locates immediately after the LNA in the receiver chain as shown in Fig. 2.3, it effects the linearity performance of the complete receiver [62]. A higher linearity allows a larger input power range from LNA. Linearity is the most difficult specification to achieve in designing a low-voltage mixer. Since the headroom is strictly limited in low-voltage mixer, high gain LNA may saturate mixer when a maximum signal or high-power blocking received. To handel the large signal from LNA, sufficient linearity is necessary. Besides the issue of the low-voltage of operation, RF design on advanced CMOS processes has been challenging on the high cost of the chip area, This translates to a need to reduce the design area for achieving a specific function under certain performance requirements [63].

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The topology of the mixer at high-frequency, which have been reported in litera-ture [61,63–72], can be classified into active and passive topologies depend on the DC power consummation. The passive mixers include differential pair mixer [61, 68, 71, 72], cascade mixer [63], and the transconductance mixer [67]. While passive mixers include drain-pumped resistive mixer [64], gate-drain-pumped resistive mixer [66], and resistive mixer [69, 70]. In Fig. 2.15 [61], differential pair, which also known as Gilbert cell, consists of transcon-ductance stage M1, differential switching pair M2 and M3, and load RL. The conversion gain of Gilbert cell mixer is proportional to RL, if the RL is large, its conversion gain would be large. With a large voltage drop, the Gilbert cell mixer is modified to the current-reuse bleeding mixer [71]. Bleeding mixer topology, as shown in Fig. 2.16, provides the better performance in terms of conversion gain, linearity, noise figure, and LO isolation. How-ever, in order to drive differential pairs sufficiently to turn on and turn off, the LO signal strength should be large enough.

Cascade mixer is shown in Fig. 2.17 [63]. The mixer consists of two transistors M1 and M2 are connected in series. RF and LO signals are applied through M1 and M2 gates, respectively. The resultant output IF signal is extracted from the drain terminal of M2. A cascade type mixer has the advantage of providing good LO-RF isolation without the use of ﬁlter. Besides, the using of double-gate layout to implement M1 and M2, the capacitance at the drain of M1 can be minimized though a careful layout, which improves the conversion gain at mm-wave.

The simple schematic of transconductance mixer is shown in Fig. 2.18. In Fig. 2.18 the LO and RF signals are combined and applied to the gate of M1, to large the conversion-gain of M1, M1 is operated in the saturation region, with gate-source voltage (V_GS) of M1 is set close to its threshold Voltage (VT H). However, due to the close operational frequencies of LO and RF signals, the RF-LO isolation is very poor. In order to improve the LO-RF isolation hybrid combiner is used in [67] as shown in Fig. 2.19, Although, the mixer in [67] required low input LO power, short-circuit drain nodes at LO frequency are required to improve stability. Thus, an open quarter-wave stub at the drain node is used. Besides, to provide DC biasing for M1 and M2 an extra area is required for implementing short quarter-wave stub. All this increase the chip size area.

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The active mixer topologies can achieve low conversion loss or even gain, but the lin-earity of these active topologies is low, especially at moderate to low power consumption. Much higher linearity can be achieved with resistive mixers. Drain-pumped resistive mixer is shown in Fig. 2.20 [64]. In Fig. 2.20 LO and RF signals are applied to drain and gate of M1, respectively. The transconductance of M1 is a time variant function of drain-source voltage VDS and VGS. At proper bias, the nonlinearities of the other elements are weak and can be neglected. The pumped resistive mixer shown in Fig. 2.21 [66]. In gate-pumped resistive mixer LO and RF signals are applied to source and gate of M1, The transconductance of M1 is a time variant function of VGS.

Another passive mixer topology is shown in Fig. 2.22 [69, 70], In this topology LO signal is applied to the gate of M1 via a matching network, a simple diplexer separates the RF and IF signals. The passive mixers have a significant advantage that RF and LO frequencies, which are close in the frequency value, are injected at different ports. Thus, the simplified filtered circuit would improve the LO-RF isolation. However, due to passive and resistive nature of the resistive mixers topologies, its have a relative high conversion loss. In addition they require high LO input power. Table 2.3 summarizes the performance parameters of the recent studies high-frequency CMOS mixers dating from 2004-2007.

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T a ble 2.1: Comparison o f receiv er a rc hitecture. Hetero dyne Direct-Con v ersion Image-Rejection Wide-band IF Lo w-IF Double-Quadrature P erformance Go o d Po o r Mo derate Mo derate Mo derate Mo derate DC-Oﬀsets No Ye s No No No No 1/f noise No Ye s No No No No Balance I/Q Not required Accurate Accurate Accurate Accurate Mo derate Image Rejection Go o d Not required Mo derate Mo derate Mo derate G ood In tegration Abilit y Po o r G ood Mo derate Mo derate Mo derate G ood Powe r D is si p a ti o n High Lo w Lo w High Lo w Lo w

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T a ble 2.2: Summary of recen t CMOS L NA results. Ref. NF Gain S11/S22 1dB/I IP3 Powe r Supply Fr eq . Pro cess Circuit Ye a r [dB] [dB] [dB] [dBm] [mW] v o ltage [V] [GHz] T o p o logy [46] 4 10 -15/-17 -/-45 2 20 0 .18 μC M O S Casco de 1 stage 2001 [59] 5.2 12 -12/--/-3 47 -17 0 .18 μC M O S Casco de 2 stages 2003 [59] 6 10 -17/--/-3 47 -24 0 .18 μC M O S Casco de 2 stages 2003 [56] 5.6 12.86 -11/-22 -11.1/+2.04 54 1.8 23.5 0 .18 μC M O S 3 stages C S 2003 [45] 6.4 5.8 -20/-20 -4.8/+3 10 1.5 20 90 nm C M O S 1 stage CS 2004 [55] 5.6 12.9 -11/-22 -11.1/+2 54 1.8 23.7 0 .18 μC M O S 3 stages C S 2004 [55] 6.9 8.9 -14/-12 -10.2/+2 54 1.8 25.7 0 .18 μC M O S 3 stages C S 2004 [61] 6 15 -/-24 1.5 21.8 0 .18 μC M O S 1 C G a nd 2 C S stages 2004 [54] 3.16 10.71 -15/-12 -5/+5.16 28.6 1.3 14 0 .18 μC M O S 2 stages C S 2005 [53] 3.9 13.1 -15/-20 -12.2/+0.54 14 1 24 0 .18 μC M O S 2 stages C S 2005 [52] 5.5 9.2 -8/-4 -/+7 19 1 20 90 nm C M O S 2 stages C S 2005 [51] 3.2 7.5 -16/-30 -/-10.6 1 24 90 nm C M O S 1 stages C S 2005 [50] 4 16.2 -15/-5 -/-26.4 1.2 26 90 nm C M O S 2 stages C S 2005 [60] 4.6 13 -1.5/- -/-4.8 1.2 60 0 .13 μC M O S CG and C S stages 2005 [42] 8.8 12 -15/-15 -10/-0.5 54 1.5 60 0 .13 μC M O S Casco de 3 stages 2005 [73] 3.1 8.4 -5/-10 -/+4.8 14 1.4 20 90 nm C M O S Casco de 1 stage 2006 [58] 11.5 16.5 -15/-10 -18.5/-16.2 1.2 22.5 0 .12 μC M O S Casco de 1 stage CS 2006 [74] 7.1 20 -8/-5 +1.8/-79 2.4 57 90 nm C M O S Casco de 3 stages 2006 [43] 8.2 17.8 -7/-2 -16.1/-91.2 2.4 60 0 .13 μC M O S Casco de 4 stages 2007 [44] 6 12 -12/-30 +4/-10.4 1 62 90 nm C M O S 2 stages C S 2007 [57] 5.5 14.6 -20/-20 -15.6/-6.8 24 1.5 58 90 nm C M O S Casco de 2 stages 2007

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T a ble 2.3: Summary of recen t high-frequency CMOS mixer results. Ref. RF F req. IF F req. Con v ersion-gain LO P o w er 1dB/I IP3 Powe r Pro cess Circuit Ye a r [GHz] [GHz] [dB] [dBm] [dBm] [mW] T o p o logy [64] 35 2.5 -4.6 7.5 -6/2 0 90 nm SOI-CMOS drain-pump ed resistiv e 2004 [65] 30 2.5 -2.6 5 -/0.5 20.4 90 nm SOI-CMOS activ e single balanced 2004 [61] 21.8 4.9 13 - -/-6 0 .18 μm CMOS activ e single balanced 2004 [66] 27 2.5 -9.7 10 -/20 0 90 nm SOI-CMOS gate-pump ed resistiv e 2005 [67] 60 2 -2 0 -/-3.5 2.4 0 .13 μm CMOS activ e single balanced 2005 [68] 19 2.7 1 -1 -/-2 6.9 0 .13 μm CMOS activ e double balanced 2005 [69] 28 1.6 -11.15 13 -2.7/8 0.64 0 .18 μm CMOS resistiv e single ended 2006 [70] 60 2 -11.6 4 6/16.5 0 90 nm CMOS resistiv e single ended 2006 [63] 60 4 -1.2 1.5 0.2/ -90 nm CMOS activ e single ended 2006 [71] 60 0 28 ∗ - -22.5/-9 0 .13 μm CMOS activ e single balanced 2006 [72] 17.2 2.4 -16 - -1/-27 0 .18 μm CMOS activ e double balanced 2007 * V oltage gain.

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Figure 2 .1: T he blo ck diagram of the h omo d yne, direct-con v ersion, or zero-IF receiv er.

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Figure 2 .3: T he blo ck diagram of the h etero d yne o r IF receiv er.

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Figure 2 .4: T he blo ck diagram of the H artley receiv er.

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Figure 2 .5: T he blo ck diagram of the W ea v er receiv er.

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Figure 2 .6: T he blo ck diagram of the w ideband-IF receiv er.

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Figure 2 .7: T he blo ck diagram of the lo w -IF receiv er.

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Figure 2 .8: S p ectra ﬂo w o f the lo w-IF receiv er.

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Figure 2 .9: T he blo ck diagram of the d ouble-quadrature receiv er.

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Figure 2 .10: Sp ectra ﬂo w o f the double-quadrature receiv er.

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Figure 2.11: a) The common-source ampliﬁer as the input stage, b) The common-source ampliﬁer with source degeneration inductor.

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Figure 2.14: The schematic diagram of Common-gate with resistive feedback (CGRF)LNA.

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Figure 2.19: The schematic diagram of transconductance quadrature balanced mixer with hybrid combiner.

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Chapter 3 CMOS LOW–NOISE AMPLIFIER

UTILIZING THE TECHNIQUE OF

CAPACITIVE FEEDBACK

NETWORK

In this chapter, a CMOS low-noise ampliﬁer (LNA) with a new input matching topology has been proposed, analyzed, and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18− μm 1P 6M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise ﬁgure (N F ) of 4.57 dB and an N Fmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve −40 dB and the input and output return losses are better than −11 dB. The input 1-dB compression point is

−11 dBm and IIP3 is −0.5 dBm. This LNA drains 10 mA from the supply voltage of 1

V.

The proposed input matching method is discussed in Section 3.1 and its eﬀect on the noise ﬁgure (N F ) is presented in Section 3.2. The details of the designed CMOS circuit of the LNA are presented in Section 4.2. While in Section 3.4, it describes the experimental results. Finally, the summary is given in Section 4.4.

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3.1 Proposed Input Matching Method

The input impedance of the LNA is designed to match with the antenna, in order to pre-vent the incoming signal from reﬂecting back and forth between the LNA and the antenna. Generally, the antenna has 50-Ω load to the LNA. Unfortunately, the input impedance of a MOSFET device is inherently capacitive, so the matching with 50-Ω resistive input impedance is not an easy task. Thus, a capacitive feedback matching technique is proposed to overcome this problem [75].

The common-source ampliﬁer as the input stage is shown in Fig. 3.1, where Zs is the impedance seen from the right node of the input matching inductor Lg, Zin is the input impedance of M1, Cgd is the gate-drain capacitance, Cgs is the gate-source capacitance,

Cout is the output loading capacitance which is the input capacitance of the next stage, Rs is the signal-source resistance, and Vs is the input signal voltage source. By using Millers theorem on Cgd, the input impedance Zin can be derived as

Zin = Rf (Q2_f + 1) + 1 jωo(Cgs+ Cgd)(_Q12 f + 1) (3.1.1) where Qf = ωo(Cgs+ Cgd)Rf (3.1.2) Rf = 1 gm Cout Cgd , (3.1.3)

gm is the transconductace of M1, and ωo is the operating angular frequency. As it can be seen from the above equations, both Cgd and Cout with gm together providing a real term

Rf which contributes to the real input impedance in Zin. They are called the capacitive feedback matching network.

3.2 The Noise Analysis of the Proposed Input

Match-ing Method

In the LNA design, input power match is essential but not suﬃcient. It is also vital for a LNA to satisfy the noise performance requirement, so that the circuit itself does not

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degrade the output signal-to-noise ratio (SNR) to an unacceptable level. Thus, a careful noise analysis on the capacitive feedback matching technique is developed to establish the principle of operation clearly and ﬁnd the limits on noise performance. A brief review of the standard CMOS noise sources will facilitate the analysis.

3.2.1 Noise Sources

Fig. 3.2 shows the small-signal model of the equivalent circuit for the noise analysis. Three noise sources have been considered in Fig. 3.2. They are the thermal noise of the source resistance in,Rs, the thermal noise of the channel current in,d, and the gate induced current noise in,g. They can be expressed as [48]

i2n,Rs = 4kT 1 Rs Δf (3.2.1) i2n,d = 4kT γgd0Δf (3.2.2) i2n,g = 4kT δ ω2C_gs2 5gd0 Δf, (3.2.3) where k is the Boltzmann’s constant, T is the absolute temperature, Rs is the source resistance, gd₀ is the zero-bias drain conductance, γ is the thermal noise coeﬃcient, Δf is the noise bandwidth in hertz, and δ is the gate induced current noise factor.

According to [48], there is a correlation between the gate induced current noise in,g and the thermal noise of the channel current in,d. This correlation can be treated by separating

in,g into two parts. in,gc is the part that fully correlated with thermal noise of the channel current in,d, whereas in,gu is the uncorrelated part. Hence, the gate induced current noise can be written as i2n,g = 4kT δ ω2C_gs2 5gd₀ (1− |c|2)Δf in,gu + 4kT δω 2_C2 gs 5gd₀ |c| 2_Δf in,gc , (3.2.4)

where the correlation coeﬃcient c is deﬁned as [48]

jc = in,gi ∗ n,d i2_n,g i2_n,d . (3.2.5)

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Because of the correlation, special attention must be paid to the reference polarity of the correlated component. The value of c is positive for the polarity shown in Fig. 3.2.

3.2.2 Capacitive Feedback Matching Network Noise Analysis

Noise performance is usually evaluated with noise figure (N F ) which indicates the noise suppression ability of the circuit. Noise figure is defined as

N F = 10log(F ), (3.2.6) where F is the noise factor which is deﬁned as the total output noise power divided by the noise power at the output due to the input source. F can be expressed as

F = i 2 n,o,tot. i2_n,o,Rs = i2_n,o,Rs+ i2_n,o,g_+d i2_n,o,Rs , (3.2.7)

where i2_n,o,tot. is the mean-squared of the total output noise current, i2_n,o,Rs is the mean-squared output noise current due to in,Rs, and i2_n,o,g_+d is the mean-squared output noise current due to in,d and in,g. Considering correlation, i2n,o,g+d can be re-expressed as

i2_n,o,g_+d = (i∗_n,o,d+ i∗_n,o,g)(in,o,d + in,o,g)

= i2_n,o,d+ 2Re(in,o,di∗n,o,g) + i2n,o,gu. (3.2.8) From (3.2.5), (3.2.7), and (3.2.8). Noise factor can be expressed as

F =

A2i2_n,d+ 2Re(AB∗c

i2_n,g i2_n,d) + B2i2_n,gu

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where A = in,o,d in,d = 1 (3.2.10) B = in,o,g in,g = RS+ SLg Rs+ SLg+ Zin Zingm (3.2.11) D = in,o,Rs in,Rs = RS Rs+ SLg+ Zin Zingm. (3.2.12) Finally, the noise factor for a capacitive feedback matching network is obtained from (3.2.9)-(3.2.10) as F = 1 + γ α 1 gmRs |c|α δ 5γ ₂ +R2_s− s2L2_g 1 R2_f − α2δ 5γ (1− |c| 2_)s2_C2 t −sCtRs ₂ 1 +|c|α δ 5γ ₂ + 2Rs Rf , (3.2.13) where Ct = Cgs+ Cgd and α ≡ gm/gd0. By taking the derivatives of (3.2.13) with respect to Rs and Lg and let the derivatives equal to zero, optimum source noise impedance,

Zn,opt = Rsn,opt+ jωLgn,opt, corresponding to minimum noise ﬁgure can be written as

Z_n,opt = α2δ 5γ (1− |c|2) + 1 Q2_f + j 1 + α|c| δ 5γ α2 δ 5γ(1− |c| 2_{) +} 1 Q2_f + 1 + α|c| δ 5γ ₂ × 1 ω(Cgs+ Cgd) . (3.2.14)

Using (5.1.1), (3.2.14) can be re-expressed in Z_n,opt∗ as