VCO and Divider

For the purposes of testing, a high performance VCO with quadrature divided-by-two operating at 16 GHz and 8 GHz, respectively are integrated. The schematic of the proposed VCO and quadrature divided-by-two circuit are shown in Fig. 5.9. The core structure of the VCO in Fig. 5.9 consists of cross-coupled transistors M56 and M55 with center tap inducer L11. In order to provide tuning capabilities varactors C14 and C15 are used, where the oscillation frequency of VCO is controlled by voltage V1. The quadrature divided-by-two circuit is consists of two pairs of cross-coupled transistors M57-M58 and M59-M60 with two center tap inductors L12 and L13. To increase the locking range varactors C18-C19 and C17-C16 are used, and controlled by voltage V2. In the VCO topology, the bias current is

defined by current source I_vco, which mirrored through M64 to the tail transistor M63 for a stable output power level.

5.2 Experimental Results

The designed 24-GHz current-mode receiver front-end circuit was fabricated in 0.13− μm 1P 8M CMOS technology. The top metal of this process is with the thickness of 3.35 μm. The equivalent relative dielectric constant ε_{ef f} is about 4.2. Based on the technology information of the backend process, the electromagnetic (EM) tool HFSS is used to evaluate and extract the characteristics of the interconnections within the circuits as shown in Fig. 5.10.

The floor plans of the proposed receiver front-end are depicted in Fig. 5.11. four on-chip octagonal spiral inductors, and seven center tap octagonal inducer are used. The distances of each inductor are more than 100 μm to mitigate the magnetic coupling between on-chip inductors. In addition, the distances of the active devices of TLNA, RF current-mode mixer, IF current-mode mixer, DC–offset compensation circuit, VCO, and quadrature divided-by-two circuits are arranged far, the noise influence between these circuits are kept small. The signal path between input pad and the input of the TLNA is drawn as short as possible to avoid additional signal losses and increase of NF. Besides, large on-chip decoupling capacitors are used between the biases and ground, such that high frequency noises can be bypassed to ground and consequently stable biases and supplies of the receiver can be achieved. The performance of each circuit block in this 24-GHz current-mode receiver is over-designed to overcome process variations. This chip occupies the active region of 1.850× 1.806 mm² including testing pads.

The measurement setups of this fabricated receiver are described as follows. The on-wafer probing measurement is adopted to verify the performance of the receiver frontend.

one GSG RF probes with the pitch of 100 μm, two GSGSG RF probes with the pitch of 150 μm, and a 12-pin dc probe with the pitch of 150 μm are applied to probe the testing pads. The S parameters are measured to analyze the input matching characteristics by the network analyzer. To measure conversion gain and linearity, two signal generators are used to provide a RF and a LO signals for the device under test (DUT). The spectrum analyzer

is used to monitor the spectrum to verify the linearity and conversion gain of the receiver.

The NF analyzer with a broadband noise source is used to measure the performance of NF of the receiver. Owing to the frequency shift of the VCO in fabricated chip, the laser cut is used to modify operational frequency of the VCO. Moreover, the measured current consumption of the receiver is 35 mA from the supply voltage of 1 V.

From Fig. 5.12 the measured and simulated input reflection coefficient of the proposed receiver is better than −13 db, Fig. 5.13 presents the measured gain and NF versus RF input frequency. The losses from cables, probes and adaptors are compensated. Moreover, the LO is set to the frequency of 16 GHz, and the the output is observed at the fixed IF frequency of 100 MHz. The measured conversion gain of the RF frequency is 19.5 dB, while the N F is 15 dB. In addition, due to DC–offset compensation circuit, when the input RF at 24 GHz the gain of 10.5 is measured. Thus, The DC–offset compensation circuit reduces the DC gain by 10 dB. The measured output power versus the input power is shown in Fig. 5.14 where the input referred 1-dB compression gain is −25 dBm.

The measured output frequency of VCO versus control voltage V1 from 0 to 1 is mea-sured by the observation of the VCO leakage from IF output port. It can be seen from Fig. 5.15 that the VCO output frequency is shift to lower frequency about 2-GHz. Be-cause the model of the two-turn symmetric inductor is calculated by the interpolation from one-turn and three-turn symmetric inductors, the accuracy of the interpolation method is verified by the 3D EM CAD tools HFSS. The whole EM simulation result can be closer to measurement result with frequency offset of 0.5 GHz. In order to measure the receiver in the desired band, laser-cut technique is adopted to cut off a part of the varactors. Thus, the varactors at each output terminals of VCO and quadrature divided-by-two are reduced so that the oscillation frequency of the VCO is shifted upward. After coping with several tested chips with this procedure, a resultant oscillation frequency tuned from 15 GHz to 16.5 GHz under a tuning voltage of 0 V to 1 V. The microphotograph of the VCO and quadrature divided-by-two circuits after laser-cut is shown in Fig. 5.16

Table 5.1 summaries the performance of the proposed current-mode receiver front-end.

In addition, some comparison results of published 24-GHz receiver front-end circuits are also provided. Compared to the works published in [61], [31],and [82]. The proposed

24-GHz CMOS current-mode receiver front-end has the advantage of high level of integra-tion with smaller power dissipaintegra-tions and can be operated under low–voltage with a good linearity performance.

5.3 Summary

In this chapter, the current-mode design techniques of CMOS RF circuits are developed and are applied to realize the 24-GHz CMOS current-mode receiver front-end. The receiver integrated with TLNA, RF current-mode mixer, IF current-mode mixer, DC–offset com-pensation circuit, VCO, and quadrature divided-by-two circuits. The TLNA proposed in chapter 3 of the thesis is used to amplified the RF input spectrum at 24 GHz with minimal noise contribution to enlarge the power difference between the received signal and noise, then the amplified RF input spectrum at 24 GHz is down-converted to an intermediate frequency (IF) of 8 GHz by using RF current-mode mixer proposed in chapter 4 of the thesis, and a follow-up IF current-mode mixers are used in-phase I and quadrature Q paths to directly convert the spectrum at IF frequency to zero frequency. The baseband signals are then applied to the DC–offset compensation circuit to eliminate DC–offset currents appear at the output of the IF current-mode mixer due to the self-mixing of the LO. The fabricated circuit demonstrates a conversion gain of 19.5 dB and noise figure of 15 dB while maintaining an input return loss better than−13 dB. The input-referred 1dB compression point of −25 dBm is measured. This receiver drains 35 mA from the supply voltage of 1 V.

Table5.1:Themeasuredperformancesandcomparisonsresultsofpublished24-GHzreceiverfront-endcircuits. Thiswork[61][31][82] Tech.0.13μmCMOS0.18μmCMOS0.18μmCMOS0.13μmCMOS LevelofLNA,double-balanceRFmixer3-stageLNA3-stageLNA2-stageLNA IntegrationI/QdifferentialIFmixer,single-balancedsingle-balancedmixer DC–offsetcompensation,GilbertmixerGilbertmixer,twoIFA VCOwithquadraturedivider TopologyCurrent-modeVoltage-modeVoltage-modeCurrent-mode FreqRF[GHz]2421.82424 FreqLO[GHz]16∗ 16.919.1819 FreqIF[GHz]04.94.825 GainRX[dB]19.527.528.412 NFRX[dB]15(6∗∗ )8613.3 P1dB[dBm]-25-23-23.2-12 ImageRejection[dB]423144.8– Power[mW]3564.55449.8 supply[V]11.51.81.2 Chiparea[mm2 ]1.850×1.8060.4×0.51.1×1.21.45×0.72 *on-chipVCO. **thesimulatedNFofLNAandRFcurrent-modemixer.

Figure 5.1: The block diagram of the 24-GHz current-mode receiver front-end.

Figure 5.2: The circuit diagram of the TLNA.

Figure 5.3: The simplified circuit diagram of the self-switching mode RF current-mode mixer.

Figure 5.4: The circuit diagram of the double-balance self-switching current-mode RF current-mode mixer.

Figure 5.5: The simulated gain of TLNA with and without notch filter.

Figure5.6:ThecircuitdiagramofthequadratureIFcurrent-modemixers.

Figure 5.7: The circuit diagram of DC–offset compensation circuit.

Figure 5.8: The sensitivity of the rectifier circuit to the variation of the M52 width.

Figure 5.9: The circuit diagram of VCO with quadrature divided-by-two circuit.

Figure 5.10: The interconnections within the circuits in the receiver are simulated by HFSS.

Figure 5.11: The chip micrograph of the fabricated current-mode receiver front-end.

Figure 5.12: The measured and simulated input reflection coefficient of the proposed re-ceiver.

Figure 5.13: The measured gain and N F of the proposed receiver.

Figure 5.14: The receiver measurement results of P_in versus P_out.

Figure 5.15: The measured and simulated tuning range of the VCO.

Figure 5.16: The microphotograph of the VCO and quadrature divided-by-two circuits after laser-cut .

Chapter 6

CONCLUSIONS AND FUTURE