CMOS SELF–SWITCHING CURRENT–MODE MIXER
4.1 Operational Principle Of Self–Switching Current- Current-mode Mixer
The concept of self-switching current-mode circuit is shown in Fig. 4.1 where Ma is an nMOS device. In Fig. 4.1, both the RF signal current irf and the LO signal current ilo are applied to the source together through a combiner, usually a filter or directional coupler.
IT H is a DC current added with irf to control the conversion gain. The resonator at the output port (capacitor CT and inductor LT) is used as bandpass filter to reject all signals except IF. When ilo+ IT H is high enough in the direction of the source current is, Ma is
switched on, and remains on only as long as this condition lasts, after which it is switched off. This property is adopted to form the down-conversion mixer.
Assuming that the local oscillator current ilois much larger than the input signal current irf, the ac current gain Ai = id/irf of Ma can be considered as a function of the sinusoidal LO current only, as shown in Fig. 4.2. Ai can, therefore, be considered as periodically varying at the LO frequency and represented by a Fourier series as
Ai = α0+ α1sin ωLOt + α2sin 2ωLOt + . . . + αjsin jωLOt + . . . + αnsin nωLOt coefficients. When a small RF current signal irf = IRFcos ωRFt is applied to the source of M1, the alternating drain current id= Aiirf can be written as
id = α0IRFcos ωRFt +1 where ωRF is the radian frequency of RF signal, and IRF is the RF signal amplitude.
From (4.1.3), the jth harmonic conversion current gain Acj at the jth harmonic of the LO is αj
2 . By substituting the value of the Fourier coefficient αj in (4.1.2), can be rewritten as Acj = αj
For the special case n = 1, the fundamental down-conversion current gain is Ac1 and ωIF is equal to ωRF− ωLO. Fourier analysis is applied to Ai, where a sinusoidal waveform of ilo with 4m+1-points from -2m to 0 and from 0 to 2m. As derived in the Appendix, Ac1 can be expressed as
can be found that to achieve a higher conversion gain, C−2m to C−1 should be set to 0.
Therefore, Ac1 = 0 in approximate one half of a LO period. In addition, C1 to C2mshould be maximized this can be done through controlling IT H as shown in Fig. 4.2.
4.2 Circuit Implementations
The schematic diagram of the proposed 60-GHz CMOS down-conversion quadrature balanced mixer is shown in Fig. 4.3. In Fig. 4.3, Ma5 and Ma6 are the self-switching devices, each biased by 12IT H. IT H is controlled by I1 and I2 (IT H = I2 − I1) through diode-connected transistors M3 and M2, respectively. The two parallel LC resonant tanks (L1, C2) and (L2, C3) at the output ports are used to select the IF frequency at 2 GHz.
The 90◦ branch-line hybrid coupler, which consists of transmission-lines T3-T6, each with the characteristic impedance of 60 Ω at 60 GHz, are used to provide a 90◦ phase delay and achieve isolation between the LO and RF ports. The common-gate amplifier, consisting of M1, transmission-lines T1 and T2 with a total length equal to 300 μm, and bypass capacitors C4 and C5, is used to match with the RF input port impedance of 50 Ω. C1 is the DC blocking capacitor to isolate the LO port from DC source. Moreover, the two output source-follower buffers M7 and M8 are designed for measurement purposes to drive the 50 Ω input port of the network analyzer.
The proposed mixer offers two advantages. First, it has a self-switching device at its triode region with low operating power and high linearity. Second, the gate node is connected to VDD, an AC ground, and the drain node is short-circuited at LO frequency, which reduces the required LO power [78] and improves the stability at LO frequency [70].
And because the design of the proposed mixer must deal with the issue on the combination of LO and RF signals, a 90◦ branch-line hybrid coupler [78] and the quadrature balanced mixer architecture are designed in.
At high operating frequencies, the hybrid can be easily integrated onto a chip, but it suffers from a large insertion loss due to the high substrate loss of the standard CMOS. In order to reduce the effect of the substrate loss, the branch-line and through-line lengths of the hybrid are reduced from λ/4 to λ/6.4 and λ/10, respectively, based on the methodology [79] of a short high-impedance transmission line with shunt lumped capacitors.
In the methodology proposed in [79], the maximum transmission line length reduction depends on the maximum characteristic impedance of the transmission line. Convention-ally, both microstrip-line (MSL) and coplanar waveguide (CPW) are used to implement the transmission line. However, the maximum characteristic impedance of MSL depends on the distance between the top-layer and bottom-layer metals, which is fixed for a given CMOS technology. In the CPW transmission line shown in Fig. 4.3, the signal-to-ground spacing W can be used to increase the impedance of CPW, while the signal width d con-trols the conductor loss. Additionally, the underpass metal, which connects the two planar grounds to suppress unwanted odd CPW mode, is used with intrinsic device capacitances to implement the required shunt capacitors. Moreover, CPW is more area efficient than MSL. In MSL the isolation between the adjacent lines must be considered because the cou-pling between two adjacent lines changes the characteristic impedance. Consequently, an extra separation distance between the adjacent elements should be considered to eliminate the unwanted coupling effects. This drawback can be avoided in CPW by surrounding the signal line with two adjacent well-grounded lines. For these reasons, the CPW is used to design the 90◦ branch-line hybrid.
4.3 Experimental Results
The proposed mixer operated at 60 GHz was designed and fabricated in 0.13 μm 1P 8M CM OS technology. The chip photograph is shown in Fig. 4.5, and the total die area is 1400μm× 1040μm including all test pads and dummy metals. The performance of the fabricated mixer circuit was tested through an on-wafer probing technique.
The test setup is shown in Fig. 4.6, where a signal generator with an external source module are used as 58 GHz LO source followed by 10 dB directional coupler. A power sensor followed by a power meter is connected to the coupler’s coupled port to monitor the LO power levels of the through port. The coupler’s through port is connected through the waveguide connector of 100 μm V-band microwave probe to the DUT.
The 60− GHz RF signal is generated by the signal generator and followed by a source module. However, because this source module output power level is fixed and not ad-justable, a variable attenuator is added to the RF port while the rest of test setup is
identical to the LO port. The output IF signal is measured using differential 150 μm probes through the bias-Tee, where one IF port is connected to 50 Ω for termination, while the other IF port is connected to a spectrum analyzer. The loss of probes, bias-Tees, coax-ial cables, and the waveguide connecters were measured separately and used to correct the measured results. The measured results are accurate to within ±1 dB.
The measured and simulated output IF power versus the input RF power at 0 dBm LO power is shown in Fig. 4.7, where the input referred to as 1dB compression again is up to 2 dBm. The measured and simulated conversion gain values versus the LO power at 58 GHz with RF signal at 60 GHz are shown in Fig. 4.7, which shows that the single-ended conversion gain is 1 dB at 0 dBm LO power. The discrepancy of 2 dB between measurement and simulation is likely due to the accuracies of the measurement system (±1 dB), and the modeling of MOS transistor at high frequencies. The measured LO-RF isolation is better than −37 dB, as shown in Fig. 4.9. Besides, the measured 3 dB RF and IF bandwidth of the mixer are 6.3 GHz and 400 M Hz, respectively. The fabricated mixer drains 3mA from a power supply of 1.2 V.
Finally, the measured performance of the fabricated mixer is summarized in Table 4.1, where comparisons with other published 60-GHz mixers are also provided. From Table 4.1, the proposed current-mode mixer can achieve high linearity and a higher conversion gain with low LO power, while at the same time achieving a smaller chip area by reducing the transmission lines used in the proposed mixer.
4.4 Summary
This chapter has proposed the fabrication and analysis of a CMOS quadrature balanced current-mode mixer based on a self-switching device. An area-efficient on-chip 90◦ branch-line hybrid coupler is designed to combine the LO and RF signals with an isolation better than−37 dB. The measurement results have shown that the proposed current-mode mixer is suitable for the applications of low-voltage and lower-power RF communication systems.
Table 4.1: The performance summaries of the proposed mixer and comparisons with other published mixers.
Ref. This work [67] [70] [71]
Tech. 0.13μm 0.13μm 90 nm 0.13μm
CM OS CM OS CM OS CM OS
Topology Current-mode; Voltage-mode; Voltage-mode; Voltage-mode;
active single active single resistive single active
ended ended ended balanced
RF Freq. 60 GHz 60 GHz 60 GHz 60 GHz
IF Freq. 2 GHz 2 GHz 2 GHz 0
Conv. gain 1 dB −2 dB −11.6 dB 28∗ dB
LO Power 0 dBm 0 dBm 4 dBm −−
P1dB 2 dBm −3.5 dBm 6 dBm −22.5 dBm
Power diss. 3 mW 2.4 mW −− 9 mW
Area (mm2) 1.4× 1.0 1.6× 1.7 2.0× 2.0 0.3× 0.4∗∗
* Voltage gain ** Active area only (not include balun and DC & RF pads)
Figure 4.1: The circuit diagram of self-switching current-mode mixer.
Figure 4.2: The 4m+1-point analysis applied on HSPICE simulated of ac current gain.
Figure 4.3: circuit diagram of CMOS quadrature balanced current-mode mixer.
Figure 4.4: (a) Quarter-wavelength transmission line; (b) Shorted transmission line equiv-alent to the quarter-wavelength transmission line; (c) Coplanar waveguide.
Figure 4.5: The chip photograph of fabricated current-mod quadrature balanced down-conversion mixer.
Figure4.6:Themeasurementsetupforthediagram60GHzdown-conversionmixersetup.
Figure 4.7: The measured and simulated IF output power versus RF input power.
Figure 4.8: The measured and simulated conversion gain versus LO power.
Figure 4.9: The measured LO-RF isolation characteristics.