Chapter 2 Concurrent Dual-Band Low-Noise Amplifier
2.8 Comparisons
Table 2.8.1 shows the comparisons of this work and recent dual-band LNA papers.
It can be seen that the concurrent dual-band LNA presented in this chapter achieves a good performance with low power consumption. The circuit will be applied to a concurrent dual-band receiver front-end in the next chapter.
Table 2.8.1 Comparisons of concurrent dual-band LNA
Ref Process Power
Frequency
Chapter 3
Concurrent Dual-Band Receiver Front-End
3.1 Wireless LAN Standard Review
In this section, we will review the wireless LNA standard, IEEE 802.11a, IEEE 802.11b and IEEE 802.11g. The IEEE 802.11b standard at the 2.4GHz ISM (industrial, scientific, and medical) band provides data rate up to 11Mbits/s with the direct sequence spread spectrum (DSSS). The standard was released by IEEE in 1999. The 802.11a standard at 5GHz U-NII band provides data rate up to 54Mbits/s using OFDM (orthogonal frequency division multiplexing) modulation. Released in 2003, the IEEE 802.11g standard, operating at the same band of 802.11b, uses OFDM modulation and provides data rate up to 54Mbits/s. In this section these three wireless LAN standards will be briefly described respectively.
3.1.1 IEEE 802.11a
As shown in Figure 3.1.1 the 802.11a standard has three U-NII (Unlicensed National Information Infrastructure) bands, including the lower band (5.15GHz~5.25GHz), the middle band(5.25~5.35GHz) and the upper band (5.725GHz~5.825GHz). The lower and middle sub-bands accommodate eight channels in a total bandwidth of 200MHz. The upper band accommodates four
channels in a bandwidth of 100MHz. The centers of the outermost channel shall be at a spacing of 30MHz from the edge of band for the lower and middle bands, and 20 MHz for the upper band. The bandwidth of each channel is 20MHz, and each channel has 52 sub-carriers for OFDM modulation with each sub-carrier has bandwidth of 312.5 KHz. Each sub-carrier can be either a BPSK, DQPSK, 16QAM, 64QAM signal.
The data rate versus modulation is shown in Table 3.1.1. The input signal dynamic range is from -82dBm to -4dBm [15].
5150 5250 5350 5725 5825 MHz
30 30 20 20
20
….
20MHz 52 carriers, each
BW= 312.5KHz
Figure 3.1.1 Channel allocation of IEEE 802.11a standard
Table 3.1.1 IEEE 802.11a modulation versus data rate
Modulation Data Rate (Mbps)
BPSK 6 , 9
DQPSK 12 , 18
16QAM 24 , 36
3.1.2 IEEE 802.11b
IEEE 802.11b standard can be discussed by two operation areas: North American and European. The frequency range for North American is from 2400MHz to 2472MHz while the range for European is from 2400MHz to 2483.5MHz. Here we will discuss the North American operation. For non-overlapping operation three channels are used and the channel center frequencies are: 2412MHz, 2437MHz, and 2462MHz. As for overlapping operation, six channels are selected. The center frequency of each channel has a distance of 10MHz from others. Figure 3.1.2 shows the channel location of 802.11b standard. IEEE 802.11b provides a data rate up to 11Mbps and uses direct sequence spread spectrum (DSSS) and complementary code keying (CCK) modulation [16].
2400 2412 2437
Non-overlapping
2462 2483.5 MHz
2400 2412 10 2462 2483.5
Overlapping
MHz
Figure 3.1.2 Channel allocation of 802.11b standard
3.1.3 IEEE 802.11g
The operation frequency of 802.11g is from 2412MHz to 2483MHz, and the
bandwidth of each channel is 20MHz. It extends the data rate of 802.11b to 54Mbps in the 2.4GHz band using OFDM modulation. Similar to 802.11b, 802.11g has three non-overlapping channels [17]. Table 3.1.2 lists the overview of IEEE 802.11a/b/g.
Table 3.1.2 Overview of wireless LAN standard
Mode Data Rate
3.2 Review of Receiver Architecture
The aggressive design goals of radio frequency transceivers may include low cost, low power dissipation, and small chip size. The architecture and frequency plan of the RF transceiver play an important role in the complexity and performance of the overall system. The base band signal feed into the transmitter is sufficiently strong, so there are fewer transmitter architectures thane those of receivers which small input signal is feed into. Some important issues such as noise, interference rejection, and band selectivity are serious discussed in the design of receivers. In this section we review some of recently popular receiver architectures, including heterodyne, homodyne, and low-IF. The benefits and drawbacks of them will be discussed in the following pages.
3.2.1 Heterodyne Architecture
The first kind of receiver architecture is the heterodyne receivers shown in Figure 3.2.1. The RF input signal is firstly amplified, and then converted to a lower intermediate frequency (IF) by a local oscillator signal (LO). The low-noise amilifier (LNA) in front of the down-conversion mixer is used to amplify the RF signal and to reduce the noise figure of the following stage because of the high noise mixer. The IF filter suppress out-of-channel interferes and performs channel selection. This architecture suffers from a number of drawbacks. The problem of image is serious in heterodyne receivers. The most common approach to suppressing the image is through the use of an image-reject filter placed before the mixer. However the choice of IF becomes a trade-off between the image noise and the designs of IF filter. If the IF is high the image can be suppressed but complete channel select becomes difficult, and vice versa. In other word, the designer has to trade-off between selectivity and sensitivity.
Figure 3.2.1 Heterodyne receiver architecture
RF
Figure 3.2.2 Super-heterodyne receiver architecture
To solve the trade-off between selectivity and sensitivity, the super-heterodyne receiver, as shown in Figure 3.2.2, are presented. Most RF communication receivers use this conventional architecture. To release the requirement of filters’ Q- value we can down convert the RF signal by two steps, and perform the image rejection and channel selection between these stages. The drawback of super-heterodyne architecture is the numerous components. The filters which are commonly implemented with external SAW filters will be difficult to be integrated into a single chip while the on-chip filters would occupy unreasonable large areas.
3.2.2 Homodyne Architecture
Homodyne receivers, also called direct-conversion receivers or zero IF receivers, translates the RF signal directly to zero frequency. Figure 3.2.3 shows the architecture of the homodyne receivers. It has two important advantages over heterodyne architecture. First, the problem of image is circumvented because of zero IF. As a result, on image filter is required in front of the LNA. Second, the IF filters and subsequent down-conversion stages are replaced with low-pass filters and base-band amplifiers that are easy to monolithic integration. The drawbacks of the homodyne architecture may include the dc offset, I/Q mismatch, even-order distortion and flicker noise problem and the LO leakage to the antenna. The details about these problems and some possible solutions have been discussed in [18].
RF
Filter LNA
LO
LPF VGA A/D
RF
IF
3.2.3 Low-IF Architecture
Comparing with the homodyne architecture converting the RF signal to zero IF directly, the other architecture converts the RF signal to low IF signal, which is so called low-IF architecture. Low-IF receiver architecture has gained much interest recently because it avoids the use of expensive discrete components such as image-reject filters, allowing a higher level of integration. As a non-zero IF receiver architecture, dc offset and LO self-mixing problems in low-IF receivers are not so severe compared to those in zero-IF receivers. On the other hand, low-IF receivers do have image problems. The most common techniques to remove the image in low-IF receivers are to use image reject architecture or polyphase filters [19]. The comparisons of these receiver architectures are summarized in Table 3.2.1
RF
Figure 3.2.4 Low-IF receiver architecture
Table 3.2.1 Comparisons of different receiver architectures
Architecture IF frequency
(Superheterodyne) High Off-chip No Low
Homodyne Zero None High High
Low-IF Low On-chip No High
3.3 Design of Concurrent Dual-Band Receiver Front-End
In this section a new concurrent dual-band receiver using only one frequency synthesizer with tuning range of around 2.4 GHz for WLAN applications is introduced first. Figure 3.3.1 shows the concurrent dual-band receiver block diagram which has been proposed in [4]. It provides a RF concurrent dual-band receiver solution for IEEE 802.11a/b/g. The receiver consists of a differential concurrent dual-band LNA, a sub-harmonic mixer for 2.45GHz, a Gilbert-cell mixer modified from sub-harmonic topology for 5.25GHz, a quadrature voltage-controlled oscillator (VCO) and a multi-modulus frequency synthesizer. Appling such mixer operating at 2.45 GHz or 5.25 GHz with the same architecture can reduce the design complexity significantly. On-chip IF Gm-C filters are used for noise bandwidth limiting and anti-aliasing reasons. The concurrent dual-band receiver front-end is designed for this receiver block diagram as the marked area in Figure 3.3.1, which is designed and implemented cooperatively by the author and the other one [21].
Based on the comparisons of differential receiver architectures in last section, we choose low-IF receiver architecture in this work because of high degree of integration.
The IF frequency is chosen at 10MHz because of the noise and receiver architecture considerations. The receiver frequency plan is shown in Figure 3.3.2. It can be seen that the tow LO frequencies are very close because of the usage of sub-harmonic mixer. Hence one frequency synthesizer is enough to provide the tuning range of LO signals around 2.4GHz. Compared with traditional topology with two Gilbert-cell mixers two frequency synthesizers may be needed owning to large frequency difference of two LO signals for two bands.
Dual-Band
Figure 3.3.1 New concurrent dual-band receiver and concurrent dual-band front-end
Figure 3.3.2 Receiver frequency plan (a) 2.45GHz (b) 5.25GHz
The architecture of concurrent dual-band LNA for receiver front-end is shown in Figure 3.3.3. It has a similar architecture as the one discussed in last chapter except the spiral inductor Ls is replaced by the bondwire inductor Lbondwire1. Two other bondwires are needed in the RF input pad and power supply pad, so the input matching network and output matching network must be redesigned by considering the effect of the parasitic inductor from the bondwire. The inductance of bond wire is predicted as 1nH per 1mm length. Figure 3.3.4 illustrates the comparison of operation principles of conversional mixer and sub-harmonic mixer. The role of switching transistor (Qs) is evenly distributed to two parallel-connected transistors (Qs1, Qs2) in sub-harmonic mixer, thus it needs only half LO frequency compared to conversional mixer. Figure 3.3.5 and 3.3.6 show the topologies of the two mixers for receiver front-end. The design details about sub-harmonic mixer and Gilbert-cell mixer modified from sub-harmonic mixer can be found in [21].
The challenge of integrating LNA and mixers comes from the inter-stage design. In the design procedure we try to match the output matching of differential dual-band LNA and RF input matching of two mixers to the same impedance, for instance, 500 ohms parallel with 100pF, rather 50ohms. Large coupling capacitors are added between LNA and mixers for RF signal coupling and dc isolation. Some other circuits, like quadrature balun, balun, LO port matching network, and IF low-pass-filter, are implemented on PCB with lumped elements. The chip layout occupies area of 1.45mm x 1.45mm, and is shown in Figure 3.3.7. Figure 3.3.8 is the chip photograph of this work.
Vdd=1.8V
Figure 3.3.3 Concurrent dual-band LNA for receiver front-end
LNA
Figure 3.3.4 Basic concept of (a) conversional mixer (b) sub-harmonic mixer
M1 M2
Figure 3.3.5 Gilbert-cell mixer for 2.45GHz front-end
M1 M2
Lop_5g Lon_5g
Lop_2g Lon_2g Figure 3.3.7 Chip layout of concurrent dual-band front-end
Figure 3.3.8 Chip photo of concurrent dual-band front-end RFp
RFn
IFn_2g IFp_2g IFp_5g IFn_5g LOpj_5g
LOnj_5g
3.4 Experimental Results and Discussions
The concurrent dual-band receiver front-end is measured by two PCB boards, 2.45GHz and 5.25GHz, rather one PCB board, because of large size off-chip passive baluns, too many on-board decoupling capacitors, and complicated dc bias routing for circuits. As shown in section 3.3, a balun for 2.44GHz and a quadrature balun for 2.62GHz are needed to provide differential and quadrature LO signals, which are shown in Figure 3.4.1 and 3.4.2, respectively.
Figure 3.4.1 Balun for 2.44GHz
The measured transmission coefficients of the 2.44GHz rat-race is
[ ]
0.029 117.4 0.678 135.56 0.689 135.4 0.016 94.2 0.678 135.14 0.045 0.2 0.024 161.7 0.675 42.5 0.688 134.95 0.023 162.5 0.029 34.6 0.677 137.62 0.016 93.8 0.675 42.1 0.678 138.15 0.057
rat race
when all other ports are terminated with matched loads. The measured transmission coefficients of the quadrature balun composed of two rat-races and quadrature hybrid from port1 to port 2-port 5 are
21 0.444 125.75
S = ∠ − ° ; S31 =0.442 54.82∠ ° ;
41 0.452 142.04
S = ∠ ° ; S51 =0.452∠ −35.27° Selecting port 3 as phase reference we have phase relationship as
Port 2：179.43∘ ; Port 3：0∘ ; Port 4：87.22∘ ; Port5：269.91∘
The characteristic of quadrature balun satisfies the requirement for the LO port of sub-harmonic mixer though there are small phase and magnitude errors.
PCB layouts and practical FR4 PCB circuits with SMA connectors are shown in Figure 3.4.3 and 3.4.4. There are some comments on PCB boards. Firstly the width of RF and LO signal paths on PCB are drawn as 50 ohms-line for impedance matching.
Lumped Coupling capacitors (1uF) are placed in the RF paths for dc isolation. To filter out the ineluctable noise and spur from the power supplies we add four lumped decoupling capacitors (100pF, 10nF, 100nF, and 1uF) between each dc voltage and ground. IF low-pass-filters composed of lumped capacitors and resistors are placed at the IF outputs to depress the high frequency noise. The signal lines for differential or quadrature signals should be symmetric to avoid the phase error caused by the PCB transmission lines.
The block diagram of PCB on board testing for dual-band receiver front-end is
shown in Figure 3.4.5. LO port has two paths for 2.45GHz front-end because of differential balun and four paths for 5.25GHz front-end because of quadrature balun.
Two RF baluns are needed in the measurement, one for 2.45GHz and the other for 5.25GHz, to convert the RF signal from single to differential. The oscilloscope will be connected to the IF port to measure the output waveform because of 1M high input impedance.
LO IN
RF IN IF OUT
(a)
LOi IN RF IN
IF OUT
LOj IN
(b)
Coupling Capacitors Decoupling Capacitors IF LPF Figure 3.4.3 PCB layout for (a)2.45GHz (b) 5.25GHz front-end
(a) (b)
Figure 3.4.4 Photograph of PCB board for (a)2.45GHz (b)5.25GHz front-end
Figure 3.4.5 Block diagram of PCB on-board testing for dual-band front-end
Table 3.4.1 summaries the performance of this work, including simulation and measurement results. The concurrent dual-band receiver front-end was fabricated using 0.18um CMOS 1P6M process. The RF input return loss of LNA are -15.9 dB and -15.8 dB at 2.45GHz and 5.25GHz, as shown in Figure 3.4.6. The LO port input return loss of two mixers are -13.4 dB and -13.1 dB, as shown in Figure 3.4.7 and 3.4.8. Figure 3.4.9 ~ Figure 3.4.12 show the measured linearity of the front-end characterized by the overall RF-to-IF -21.0 dBm and -15.3 dBm P1dB and the overall RF-to-IF -4.2 dBm and 4.9 dBm IIP3 for RF signals in two frequency bands. It demonstrates 17.2 dB and 11.8 dB voltage gain, 7.22 dB and 10.78 dB noise figure concurrently at two frequency bands with 28.8mw power dissipation. Finally the 10MHz output waveforms measured by oscilloscope are shown in Figure 3.4.13.
Here are some discussions about the experimental results. The good RF input return loss may be owing to the accurate prediction of bondwire inductance and on-chip
circular spiral inductors which were designed, measured, and modeled by our group, rather foundry. The good LO input return loss comes from the accurate LO matching network composed of lumped inductors and capacitors. It may take great efforts to tune the matching network from the finite lumped element libraries. Although this work has good port input return loss, the performance of gain and noise figure does not meet our anticipation. There are three major factors. First, the inter-stage design may be interfered by the parasitic capacitors and resistors, causing the impedance mismatch between the output of differential dual-band LNA and RF input of mixers.
Second, the quality factor Q values of the inductors are not good enough due to parasitic resistances. The Q-values of these inductors involved in this work is from 7.08 to 8.27. The gain and output matching of the concurrent dual-band LNA will be seriously affected by the poor Q-value of inductors. Finally the absence of output buffers at IF output impacts the driving capability of the front-end. These factors may depress the gain and increase noise figure of the concurrent dual-band receiver front-end.
Table 3.4.1 Performance summary of dual-band receiver front-end 2.45GHz Front-End 5.25GHz Front-End
Sim. Mea. Sim. Mea.
LO Power (dBm) -3 8 -3 7
RF Return Loss (dB) -18.4 -15.9 -13.4 -15.8 LO Return Loss (dB) -13.2 -13.4 -18.3 -13.1 Conversion Gain (dB) 14.7 6.0 2.57 -12.0 Voltage Gain (dB) 26.5 17.2 19.9 11.8 Noise Figure (dB) 3.77 7.22 7.28 10.78
P1dB (dBm) -20.6 -21.0 -22.1 -15.3
IIP3 (dBm) -7.8 -4.2 -4.5 4.9
Power (mw) 17.9 28.8 17.9 28.8
0 1G 2G 3G 4G 5G 6G 7G -25
-20 -15 -10 -5 0
RF P ort Re turn Los s (dB)
Frequency (Hz)
Simulation Measurement
Figure 3.4.6 Comparison between simulation and measurement RF input return loss
2.0G 2.2G 2.4G 2.6G 2.8G 3.0G
-20 -15 -10 -5 0 5
LO Port Ret urn Loss (dB)
Frequency (Hz)
Simulation Measurement
Figure 3.4.7 Comparison between simulation and measurement LO input return loss of 2.45GHz Gilbert-cell mixer
2.0G 2.2G 2.4G 2.6G 2.8G 3.0G
L O P ort I nput Retur n Los s ( dB)
Frequency (Hz)
Simulation Measurement
Figure 3.4.8 Comparison between simulation and measurement LO input return loss of 5.25GHz sub-harmonic mixer
-40 -35 -30 -25 -20 -15 -10
Conversion Power Gain (dB)
Input RF Power (dBm)
Simulation Measurement
Figure 3.4.9 Comparison between simulation and measurement of P
-40 -35 -30 -25 -20 -15 -10
Conversion Power Gain (dB)
Input RF Power (dBm)
Simulation Measurement
Figure 3.4.10 Comparison between simulation and measurement of P1dB
of 5.25GHz front-end
-30 -25 -20 -15 -10 -5 0
IF Ou tp ut Po wer (d Bm)
RF Input Power (dBm)
Sim_Fundamental Sim_IM3
Mea_Fundamental Mea_IM3
Figure 3.4.11 Comparison between simulation and measurement of IIP3 for 2.45GHz front-end
-30 -25 -20 -15 -10 -5 0 5
IF Output Pow er (dBm)
RF Input Power (dBm)
Sim_Fundamental Sim_IM3
Mea_Fundamental Mea_IM3
Figure 3.4.12 Comparison between simulation and measurement of IIP3 for 5.25GHz front-end
VIFp = Figure 3.4.13 Output waveform of (a) 2.45GHz (b) 5.25GHz front-end
3.5 Comparisons
Table 3.5.1 shows the comparisons of this work and other recently dual-band receiver front-end papers. Compared with other dual-band front-end this work achieves comparable performances with nearly equal chip area and lower power dissipation under concurrent operation for two frequency bands.
Table 3.5.1 Comparisons of dual-band receiver front-end Ref [2] 2004 [22] 2004 [23] 2005 This Work
Condition Mea. Mea. Mea. Sim. Mea.
Architecture
*：IF mixer is included
Chapter 4
Low-Voltage Micromixer
4.1 Review of Basic Micromixer
The down-conversion mixer is a key building block in a receiver system. Its main function is to translate the incoming RF signal to an intermediate frequency for further processing. It dominates the system linearity and determines the performance requirements of its adjacent blocks. Among many proposed active mixers the Gilbert-cell mixer has been widely used because of it’s LO suppression at the IF output. However the circuit linearity is limited by MOSFET transistor linearity, which is the common source MOSFET transconductance [24]. The small-signal linearity of the input stage, and thus the third-order intercept point, can be greatly improved using several techniques, notably, source degeneration, the multi-tanh doublet and triplet.
However the 1-dB gain compression point still falls short of what may be required in handling large input signals without significant intermodulation. Further these RF stages do not provide an accurate match to the source [25]. Therefore the micromixer was proposed in [25] to overcome these problems. The topology of the basic micromixer is shown in Figure 4.1.1.
The micromixer follows the general form of Gilbert-cell mixer except for the use of a bisymmetric class-AB RF stage based on the translinear principles while the mixer core is identical to the Gilbert-cell mixer. The class-AB RF stage provides
Figure 4.1.1 Basic micromixer
Although the micromixer does not have inherent gain compression in RF stage, the 1-dB compression point of the micromixer will often be determined by limitations on the output IF signal amplitude, rather than by the RF stage. The noise figure of the micromixer depends on design details and is acceptable for many receiver applications although it is generally not as low as in mixers specially optimized for
Although the micromixer does not have inherent gain compression in RF stage, the 1-dB compression point of the micromixer will often be determined by limitations on the output IF signal amplitude, rather than by the RF stage. The noise figure of the micromixer depends on design details and is acceptable for many receiver applications although it is generally not as low as in mixers specially optimized for