Physical Origins

Analogous to the ESR on (100) Si/SiO2 interface[6.8], the interface defects investigated here can be attributed to the group of Pb centers as a result of the mismatch between the Si substrate and SiO2 network. The network/lattice mismatch primarily originates from the volume expansion upon oxidation of Si. Obviously, with an enhanced tensile stress to relax the intrinsic interface strain, the network/lattice mismatch is diminished, leading to a reduction in Pb centers.

Another physical interpretation can be established by directly quoting the earlier works by Deal, et al. [6.9], as illustrated in Fig. 6.6. More tensile strain produces augmented lattice spacing or equivalently reduced excess silicon density per unit area, which in turn gives rise to decreased interface-state density.

6.5 Conclusion

The noise measurement on p-MOSFETs has revealed that an enhanced tensile stress in the channel narrowing direction can improve the gate oxide integrity. Its physical origins were related to relaxed interface strain and reduced excess silicon per unit area during the oxidation.

72

References

[6.1] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T.

Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.

Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S.

Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy,

“A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron

Devices, vol. 51, pp. 1790–1797, Nov. 2004.

[6.2] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C.

Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., 2003, pp. 73–76.

[6.3] E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C.

Claeys, “On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor transistors,” Appl.

Phys. Lett., vol. 86, p. 223509, May 2005.

[6.4] M. P. Lu, W. C. Lee, and M. J. Chen, “Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal-oxide-semiconductor transistors,”

Appl. Phys. Lett., vol. 88, p. 063511, Feb. 2006.

[6.5] G. Ghibaudo, “New method for the extraction of MOSFET parameters,” Electron.

Lett., vol. 24, pp. 543-545, Apr. 1998.

[6.6] M. J. Chen, T. K. Kang, Y. H. Lee, C. H. Liu, Y. J. Chang, and K. Y. Fu,

“Low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors undergoing soft breakdown,” J. Appl. Phys., vol. 89, pp. 648–6533 Jan.

2001.

73

[6.7] G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestraf, and J. Brini, “Improved analysis of low frequency noise in field-effect MOS transistors,” Phys. Status Solidi

A, vol. 124, pp. 571–581, Feb. 1991.

[6.8] A. Stesmans, P. Somers, V. V. Afanas'ev, C. Claeys and E. Simoen, “Inherent density of point defects in thermal tensile strained (100)Si/SiO2 entities probed by electron spin resonance,” Appl. Phys. Lett., vol. 89, p. 152103, Oct. 2006.

[6.9] B. E. Deal, M. Sklar, A. S. Grove, and E. H. Snow, “Characteristics of the surface-state charge (Qss) of thermally oxidized silicon,” J. Electrochem. Soc., vol.

114, pp. 266-274, Mar. 1967.

74

0.1 1 10

0 10 20 30 40 50

Δ J

d,app.

( σ )/ Δ J

d,app.

( σ

ref

) (%)

Channel Width ( μ m)

V

_OV

= - 0.8 V, V

_D

= - 1 V

ΔW = 35nm

k

= -80 MPa

Fig. 6.1 Measured drain saturation current enhancement factor versus channel width. The inset shows the schematic illustration of STI mechanical stress in the width direction.

W

L

Tox

STI Mechanical Stress

Dielectric

75

0.05 0.1 0.15 0.2 0.25 0.3

10

^-10

10

^-9

WLS

id

/I

D2

( μ m

2

/H z)

-(V

_GS

-V

_T

) (V)

W = 10

μ

m W = 1

μ

m W = 0.6

μ

m W = 0.24

μ

m W = 0.11

μ

m

L = 0.5

μ

m, f = 100 Hz, V

_D

= -0.05 V

Fig. 6.2 Normalized experimental drain current noise spectral density versus gate overdrive for different channel widths.

76

0.00 0.05 0.10 0.15 0.20 0.25

0.0 2.0x10

^-6

4.0x10

^-6

6.0x10

^-6

8.0x10

^-6

1.0x10

^-5

L = 0.5

μ

m, f = 100 Hz, V

_D

= -0.05 V

S

Vg0.5

(V/H z

0.5

)

-(V

_GS

-V

_T

) (V)

W = 10

μ

m W = 1

μ

m W = 0.6

μ

m W = 0.24

μ

m W = 0.11

μ

m

Fig. 6.3 Square root of measured input-referred noise voltage spectral density versus gate overdrive.

77

0.1 1 10

10

¹⁷

10

¹⁸

L = 0.5

μ

m, f = 100 Hz, V

_D

= -0.05 V

Trap D ensity (cm

-3

eV

-1

)

Channel Width ( μ m)

Fig. 6.4 Extracted effective interface-state density from Fig. 6.3.

78

0.1 1 10

7x10

⁴

8x10

⁴

9x10

⁴

10

⁵

1.1x10

⁵

1.2x10

⁵

Scattering Coe fficient (Vs/C)

Channel Width ( μ m)

Fig. 6.5 Extracted effective scattering coefficient from Fig. 6.3.

79

Distance

Concent ration

SiO

₂

O

₂

Si

Excess Silicon

Excess Oxygen

Distance

Concent ration

SiO

₂

O

₂

Si

Excess Silicon

Excess Oxygen

Fig. 6.6 Schematic illustration of the distribution of the excess species in an oxide film during oxidation [6.9].

80

Chapter 7

Conclusions and Future Work

7.1 Conclusions

This dissertation concerns the assessment of mechanical stress and modeling of physical behaviors in strained MOSFETs. Brief summaries of this work are listed as follows:

First of all, with known process parameters and published deformation potential constants as input, fitting of gate direct tunneling current versus gate voltage data has led to the value of the underlying channel stress. A link with the mobility measurement on the same device has been conducted. The resulting piezoresistance coefficient has been in good agreement with literature values. The layout technique has also been validated.

Second, we have systematically examined the delta width and channel stress effects on gate direct tunneling current of narrow n-MOSFETs under STI compressive stress. Both effects have been decoupled using a new analytic direct tunneling model. The validity of the extracted transverse channel stress and delta width has been confirmed. The effect of varying longitudinal channel stress due to the narrowing action has also been addressed. The corroborating evidence in terms of the drain current variation has further been established.

Then, with the aid of the layout technique, the source/drain extension corner stress has been for the first time extracted by using the subthreshold current measurement, and has been compared with the channel stress obtained by the additional measurements on the gate direct tunneling in inversion and mobility. The validity of the layout technique has been confirmed as well. With known process parameters and published deformation potential constants as input, fitting of the gate edge direct tunneling data has led to the value of the underlying

81

lateral diffusion. The retarded lateral diffusion length and the strain induced activation energy both have been quantitatively consistent with those of the process simulation. A physically oriented analytic model has been reached, expressing the lateral diffusion as a function of the corner stress.

Finally, the noise measurement on p-MOSFETs has revealed that an enhanced tensile stress in the channel narrowing direction can improve the gate oxide integrity. Its physical origins were related to relaxed interface strain and reduced excess silicon per unit area during the oxidation.

7.2 Recommendation for Future Work

In this work, uniaxial stress along longitudinal or transverse direction has been successfully extracted. Here, the dimension length in one direction is larger than the other one.

However, when the device dimension shrinks drastically in both, the uniaxial hypothesis would not work properly. Thus, a study extending to 2D or 3D case is needed.

Intentional strain technology such as SiGe stressor, contact etch stop layer has also widely applied in the industry. Usually, the magnitude of stress will exceed 1GPa and may reach 3GPa. Hence, the shear term in k‧p method incorporating with deformation potential theory must be adopted for calculating the conduction bands considering the band distortion which is neglected under moderate stress in this research.

In this work, the isotropic stress-dependent diffusion model for uniaxial stress case has been developed and is sufficient to explain the experimental data. However, even stronger anisotropic stress can be expected in future technologies, and therefore a generalized anisotropic stress-dependent diffusion model for arbitrary stress conditions is necessary.

The impact of stress on interface states has been discussed. However, a quantitatively

82

analytical model has not been well established yet. It has been reported that the defects strongly depends on the stress states during the oxidation and passivated processes. With well-developed model, the oxide integrity can be controlled by carefully selecting process steps.

83

Vita

(博士候選人經歷表) 姓 名: 謝振宇

性 別: 男

出生日期: 1979/08/19

出 生 地: 高雄市

學 歷: 國立清華大學材料科學與工程學系畢業 (1998/09 ~ 2002/02)

國立交通大學電子研究所固態組畢業 (2002/02 ~ 2004/06)

國立交通大學電子研究所固態組 (2004/09 ~2009/03)

論文競賽: 第三屆台灣積體電路製造公司傑出學生研究獎

論文題目: 應變金氧半場效電晶體機械應力萃取與其相關物理模型建立之研究

Mechanical Stress Assessment and Physical Model Development in Strained MOSFETs

84

Publication List

Journal and Letter

[1] M. J. Chen, S. G. Yan, R. T. Chen, C. Y. Hsieh, P. W. Huang, and H. P. Chen,

“Temperature-oriented experiment and simulation as corroborating evidence of MOSFET backscattering theory,” IEEE Electron Device Lett., vol. 28, no. 2, pp.

177–179, Feb. 2007.

[2] C. Y. Hsieh and M. J. Chen, “Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs,” IEEE Electron Device Lett., vol. 28, no. 9, pp. 818–820, Sep. 2007.

[3] C. Y. Hsieh and M. J. Chen, “Electrical measurement of local stress and lateral diffusion near source/drain extension corner of uniaxially stressed n-MOSFETs,”

IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 844–849, Mar. 2008.

[4] C. Y. Hsieh, Y. T. Lin, and M. J. Chen, “Distinguishing between STI stress and delta width in gate direct tunneling current of narrow n-MOSFETs,” IEEE Electron

Device Lett., accepted and in press, 2009.

[5] C. Y. Hsu, C. C. Lee, Y. T. Lin, C. Y. Hsieh, and M. J. Chen, “Enhanced hole gate diirect tunneling current in STI uniaxial compressive stress in p-MOSFETs,”

submitted to IEEE Trans. Electron Devices, under review, 2009.

Conference

[6] C. Y. Hsieh, Y. T. Lin, T. H. Liang, W. C. Lee, J. B. Bouche, and M. J. Chen,

“Effect of STI mechanical stress on p-Channel gate oxide integrity,” in IEEE

Semiconductor Interface Specialists Conference, Dec. 2007.

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