Confirmative Evidence and Discussion - Measurement of Channel Stress Using Gate Direct Tunnelin

Chapter 3 Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially

4.4 Confirmative Evidence and Discussion

Extra measurement of drain current was carried out on the same devices. The change percentage of the apparent drain current per unit width at Vd = 1V and Vg = 1V is inserted to Fig. 4.2. The existing piezoresistance coefficients were cited for the fractional mobility change [4.12]:

Δμ(σ)/μ( 0 ) = π

σ

+ π

σ

y where

π

x = -3.16 × 10 ^-10 and

π

y = -1.76 × 10 ^-10 m²/Nt. The measured threshold voltage shift was less than 5 mV, indicating that the gate voltage minus the threshold voltage Vth remains unchanged. Thus, according to the long-channel saturation drain current expression: Idsat

= μ C

inv

(W+ Δ W)(V

-V

)

/2L where C

inv

is the gate capacitance in inversion, another analytic model, having the same expression as

(4.2) but with ax and ay replaced by

π

x and

π

y, respectively, can be created for the apparent drain current variation. Although the mobility in near-equilibrium may be not the same as that in the saturation regime of operation, the same piezoresistance coefficients can essentially apply to the relative mobility change due to the applied mechanical stress. This argument remains reasonable for the long-channel devices as used in this work. The calculated results agree with data as shown in the Fig. 4.5. Analogous to gate current case, the measured drain current was separated into the delta width only and the channel stress only. However, these two distinct effects exhibit opposite trends. Again, the effect of varying

σ

due to the

narrowing action appears to be weak, as demonstrated in Fig. 4.4.

4.5 Conclusion

We have systematically examined the delta width and channel stress effects on gate direct tunneling current of narrow n-MOSFETs under STI compressive stress. Both effects have been decoupled using a new analytic direct tunneling model. The validity of the extracted transverse channel stress and delta width has been confirmed. The effect of varying longitudinal channel stress due to the narrowing action has also been addressed. The corroborating evidence in terms of the drain current variation has further been established.

References

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Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, Jan. 2005.

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STI Si STI

Polysilicon W

W

_eff

= W + ΔW

STI Si STI

Polysilicon W

W

_eff

= W + ΔW

Fig. 4.1 The cross-sectional view of the device in the channel width direction, which can be schematically drawn from the existing simulated device structure in a state-of-the-art manufacturing process [4.3]. The effective channel width designated Weff is the drawn width

W plus the delta width Δ W.

Fig. 4.2 The relative change of the apparent gate current per unit width at Vg = 1V versus drawn gate width. The lines represent the calculated results. It is worth noting that for the narrowest case W = 0.11 μm, the delta width effect contributes 52% while the remaining (7.3%) stems from the stress induced SiO2/Si barrier lowering. The combination of both effects produces a 63% change in the apparent gate current density. For sufficiently large W, however, the delta width and channel stress effects become comparable.

Δ W = 58 nm, σ

x = -107 MPa, and k = 130 MPa.

Fig. 4.3 Comparison of experimental data (symbols) corresponding to Fig. 4.2 with the calculated results.

Δ W = 58 nm, σ

x = -107 MPa, and with k from 0 to 300 MPa.

Delta Width and Stress Stress

Delta Width

Fig. 4.5 The relative change of the apparent drain current per unit width at Vd

= 1V and V

=

1V versus drawn gate width, along with the calculated results. Note that the piezoresistance coefficients used are the typical bulk values, which are close to those of the inversion-layer ones of state-of-the-art strained n-MOSFETs [4.12], valid only for the channel <110>

direction on (001) wafer as studied in this work.

Chapter 5 Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs

5.1 Introduction

Mechanical stress has been widely recognized to be one of the key issues in the area of highly scaled MOSFETs. So far, there have been two distinct directions concerning the significance of the mechanical stress. On the one hand, the mechanical stress experienced during the manufacturing process can enhance or retard the dopant diffusion, thereby influencing the final doping profile of the device. There have been significant studies with emphasis on the material aspect covering a wide range of experimental findings and confirmations [5.1]–[5.8], as well as the atomistic calculations and physical models [5.1], [5.9]–[5.12]. Extension to the actual devices has been achieved by means of the sophisticated device/process coupled simulation, namely the technology computer-aided design (TCAD) [5.10], [5.13], [5.14]. On the other hand, the presence of the mechanical stress can also alter the band structure of the formed device, which in turn can significantly affect properties such as mobility [5.15]–[5.17], hot carrier immunity [5.18], threshold voltage [5.19], and gate direct tunneling [5.20]–[5.23]. Besides the mentioned TCAD technique [5.10], [5.13], [5.14], there have been several methods applied on the formed devices with which the magnitude of the underlying stress and its status both can be determined: 1) wafer bending jig [5.24]; 2) stress/strain simulation and modeling [5.25]; 3) Raman spectroscopy [5.26]; and 4) gate direct

tunneling [5.23].

Indeed, the ability of tracing the electrical measurements on the formed devices back to the stress related dopant diffusion in the manufacturing process is essential. Traditionally, this was done with the TCAD method [5.10], [5.13], [5.14], as mentioned above. In this paper, we present the electrical approach to the local mechanical stress around the source/drain extension corner of uniaxially stressed n-MOSFETs, which can straightforwardly determine the underlying lateral diffusion. The validity of the proposed method will be addressed in detail.

5.2 Experiment

The detail of the test devices involving the fabrication process flow, key process parameters, and schematic cross section and topside view can all be found in Chapter 3.

5.3 Corner Stress Extraction and Validation

Measurement of the subthreshold current is adopted to quantify the mechanical stress around the source/drain extension diffusion corner. The measured subthreshold current change with respect to the reference device, namely a = 10 μm, is shown in Fig. 5.1, revealing a decreasing trend with decreasing gate-to-STI spacing. The subthreshold characteristics can be expressed as

where

μ

is the mobility, Cox is the gate oxide capacitance per unit area, W and L represent the channel width and length, respectively, Vth is the threshold voltage, kT is the thermal energy,

and m is the body effect coefficient with a value between 1.3 and 1.4. Under same gate bias and large drain voltage, the difference of subthreshold current can be rearranged as follow

( ) ( ) ( )

Thus, with the measured subthreshold current change and threshold voltage shift as shown in Fig. 5.2 can the mobility variations be directly resulted. By means of piezoresistance coefficient, the corresponding corner stress can be obtained as demonstrated in Fig. 5.3. Since the subthreshold current is mainly affected by the source to channel barrier, it is inferred that the calculated stress must be located around the source/drain corner.

The extracted corner stress is found to be comparable with those of the channel as created by other electrical measurements on the same device. First, by incorporating the stress dependencies of quantized energies [5.22], [5.23], [5.27]–[5.29] into a triangular potential method [5.30] in the channel, a WKB tunneling approach [5.31] was adopted to quantify the conduction-band electron direct tunneling current. As a consequence, the uniaxial channel stress of 0, ∼0, -120, and -280 MPa was extracted for gate to STI spacing of 10, 2.4, 0.495, and 0.21 μm, respectively, each of which can reproduce experimental gate direct tunneling current versus gate voltage characteristics. The detailed extraction process can be found in Chapter 3. The corresponding gate current change is plotted in Fig. 3.4 versus extracted channel stress with gate voltage as a parameter. It was found that 2-fold subband Δ2 lies a few

kT below four-fold subband Δ

4 at high gate voltages and therefore electrons primarily populate Δ2 whereas for low gate voltages, electrons populate both Δ2 and Δ4. Hence, at low gate voltages, stress not only gives rise to a change in barrier height but also an increased population in Δ4. This effect becomes weakened for high gate voltages due to the dominating Δ2 electrons. As a result, the gate current change due to the stress increases with decreasing gate voltage (refer to [5.22] for the detailed interpretations). Second, the mobility at VD = 25

mV was characterized. The measured mobility change percentage versus extracted stress is shown in Fig. 3.5. A straight line used to fit the data points yields the slope or piezoresistance coefficient of -33.5 × 10 ^-12 dyne^-1cm², close to that (-31.5 × 10 ^-12 dyne^-1cm²) in the literature [5.2]. The inset depicts the corresponding mobility change as a function of the gate edge to STI spacing.

Finally, to testify to the validity of the layout technique, we quote existing relationship between the effective stress and the gate to STI spacing, which was derived from the stress simulation [5.25]: extracted channel stress and corner stress for a given gate to STI spacing are close to each other, indicating that the stress distribution beneath the gate oxide is considerably uniform. In addition, the corner stress follows the same trend as the channel counterpart. The resulting

V

mσ values are comparable as well: -1.05 for the channel stress and -1.02 for the corner stress.

Good fitting quality in both stress cases confirms the validity of the layout technique in

controlling the stress.

5.4 Lateral Diffusion Extraction and Confirmation

The electron direct tunneling from the accumulated poly-silicon surface down to the underlying silicon was measured versus negatively biased gate voltage with the source, drain, and substrate all tied to the ground. It can be seen in Fig. 5-5 that the resulting substrate current, which essentially is equal to the electron gate to substrate tunneling current, increases

with decreasing a. Such dependency reflects the increasing magnitude of lateral compressive stress in the poly-silicon. The confirmative evidence of this origin is that for a given gate to STI spacing, the corner stress and channel stress both are comparable and since the tunnel oxide is rather thin, the lateral compressive stress at the surface of the poly-silicon is reasonably close to that of the underlying silicon. In contrast, the simultaneously measured source/drain or edge direct tunneling (EDT) current decreases with decreasing a, as shown in Fig. 5.5. To determine the underlying gate-to-source/drain-extension overlap length where the EDT prevails, the existing edge direct tunneling models [5.33]–[5.35] on the basis of the triangular potential approximation [5.30] can readily apply with some slight modifications such as incorporating stress dependencies of the subbands in the accumulated poly-silicon surface. First of all, the oxide field Eox at the gate edge is determined through the following expression:

where

V

DG is the applied source/drain to gate voltage, VFB is the flatband voltage, tox is the gate oxide thickness, and Vpoly and VDE are the potential drops in the n⁺ poly-silicon and source/drain extension region, respectively. The accumulated electrons mainly populate in the first subband E1 due to the lowest quantized energy dominating. Then, relating the sheet charge density to the number of occupied subband states can establish the charge conservation relationship: available charge for tunnel process. The corresponding stress dependency of the quantized energy is well defined in the literature [5.22], [5.23], [5.27]–[5.29]:

52 [5.19], close to those of Ref. [5.22], were cited here. With the aforementioned parameters as input, the lowest subband level with respect to the Fermi level can be quantified. Employing the lowest subband approximation to the accumulated n⁺ poly gate and the deep depletion approximation to the source/drain extension region as drawn in Fig. 5.6, the following expressions can therefore be derived:

where NDE is the dopant concentration of source/drain extension. Here, the quantization effective masses mz = 0.98 m0 and md = 0.19 m0, and

η

= 2 were adopted to approximate the band structure for <100> oriented poly-silicon grain [5.31]. Then, it is a straightforward task to calculate the WKB tunneling probability, taking into account the corrections for reflections from the potential discontinuities [5.31]. Here the electron effective mass in the oxide for the Franz type dispersion relationship was used with mox

= 0.61 m

0. The SiO2/Si interface barrier height in the absence of stress is 3.15 eV. Consequently, the edge electron direct tunneling current density can be calculated as a function of the stress

σ

1 gate-to-source/drain-extension overlap length. The tunneling lifetime in above equation can be connected with the transmission probability T:

τ

( σ ) = π ħ/(T

σ

)E1(

σ

)).

Then with known process parameters and published deformation potential constants [5.19]

as input, the measured EDT was reproduced well as displayed in Fig. 5.7. Electron tunneling onto the forbidden silicon energy gap occurs in -0.1 V < VG < 0 V; however, an appreciable gate current was measured there. This indicates the existence of the oxide traps or interface states. Only at more negatively biased gate voltages where the EDT dominates can the effect of the traps be alleviated. In addition, it was found that the gate edge direct tunneling current is several orders of magnitude larger than the gate-to-substrate current and hence is dominant over the gate voltage range of interest. The extracted gate-to-source/drain overlap LTN spans a range of 6.1, 6.0, 5.7, and 5.0 nm for a of 10, 2.4, 0.495, and 0.21 μm, respectively as demonstrated in Fig. 5.8. The LTN

values are found to be comparable with those in the

literature [5.33]–[5.35]. The shift of around 1.1 nm, caused by dopant retarded lateral diffusion for stress change from 0 to -440 MPa, is reasonable with respective to the process simulation [5.13]. In the cited work [5.13], a device/process coupled simulation was carried out to produce the lateral doping profile from the source through the channel to the drain, with and without the strain dependencies. The resulting doping profiles reveal the diffusion retardation of about 1.8 nm as caused by a stress change from -10 to -500 MPa. It is therefore inferred that the extracted local stress and lateral diffusion shift are in satisfactory agreement with those of the process simulation published elsewhere [5.13].

The gate-to-source/drain-extension overlap length designated LTN is essentially proportional to the square root of dopant diffusivity D. The stress dependent dopant diffusivity can be expressed as [5.1], [5.4], [5.12]:

)

where Q is the strain induced activation energy and

ε

is the uniaxial strain.

ε

can be related to the uniaxial stress

σ with the Young’s modulus Y: σ =Y ε

. Then the effect of the stress on the extension overlap length can be derived as

The extracted extension overlap length is plotted in Fig. 5.9 versus the uniaxial corner stress.

Fitting of the data yields a value of –Q/kT = 129. Assuming a typical temperature of T = 1300 K for the manufacturing process, the activation energy Q of -15.7 eV results, which is reasonable relative to those (-14 eV for arsenic and -30 eV for phosphorus) of the process simulation [5.13]. Therefore, a physically oriented analytic model is reached, expressing the lateral diffusion length as a function of the corner stress.

5.5 Conclusion

With the aid of the layout technique, the source/drain extension corner stress has been for the first time extracted by using the subthreshold current measurement, and has been compared with the channel stress obtained by the additional measurements on the gate direct tunneling in inversion and mobility. The validity of the layout technique has been confirmed as well. With known process parameters and published deformation potential constants as input, fitting of the gate edge direct tunneling data has led to the value of the underlying lateral diffusion. The retarded lateral diffusion length and the strain induced activation energy both have been quantitatively consistent with those of the process simulation. A physically oriented analytic model has been reached, expressing the lateral diffusion as a function of the corner stress.

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