Lateral Diffusion Extraction and Confirmation

Chapter 5 Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain

5.4 Lateral Diffusion Extraction and Confirmation

The electron direct tunneling from the accumulated poly-silicon surface down to the underlying silicon was measured versus negatively biased gate voltage with the source, drain, and substrate all tied to the ground. It can be seen in Fig. 5-5 that the resulting substrate current, which essentially is equal to the electron gate to substrate tunneling current, increases

with decreasing a. Such dependency reflects the increasing magnitude of lateral compressive stress in the poly-silicon. The confirmative evidence of this origin is that for a given gate to STI spacing, the corner stress and channel stress both are comparable and since the tunnel oxide is rather thin, the lateral compressive stress at the surface of the poly-silicon is reasonably close to that of the underlying silicon. In contrast, the simultaneously measured source/drain or edge direct tunneling (EDT) current decreases with decreasing a, as shown in Fig. 5.5. To determine the underlying gate-to-source/drain-extension overlap length where the EDT prevails, the existing edge direct tunneling models [5.33]–[5.35] on the basis of the triangular potential approximation [5.30] can readily apply with some slight modifications such as incorporating stress dependencies of the subbands in the accumulated poly-silicon surface. First of all, the oxide field Eox at the gate edge is determined through the following expression:

where

V

DG is the applied source/drain to gate voltage, VFB is the flatband voltage, tox is the gate oxide thickness, and Vpoly and VDE are the potential drops in the n⁺ poly-silicon and source/drain extension region, respectively. The accumulated electrons mainly populate in the first subband E1 due to the lowest quantized energy dominating. Then, relating the sheet charge density to the number of occupied subband states can establish the charge conservation relationship: available charge for tunnel process. The corresponding stress dependency of the quantized energy is well defined in the literature [5.22], [5.23], [5.27]–[5.29]:

52 [5.19], close to those of Ref. [5.22], were cited here. With the aforementioned parameters as input, the lowest subband level with respect to the Fermi level can be quantified. Employing the lowest subband approximation to the accumulated n⁺ poly gate and the deep depletion approximation to the source/drain extension region as drawn in Fig. 5.6, the following expressions can therefore be derived:

where NDE is the dopant concentration of source/drain extension. Here, the quantization effective masses mz = 0.98 m0 and md = 0.19 m0, and

η

= 2 were adopted to approximate the band structure for <100> oriented poly-silicon grain [5.31]. Then, it is a straightforward task to calculate the WKB tunneling probability, taking into account the corrections for reflections from the potential discontinuities [5.31]. Here the electron effective mass in the oxide for the Franz type dispersion relationship was used with mox

= 0.61 m

0. The SiO2/Si interface barrier height in the absence of stress is 3.15 eV. Consequently, the edge electron direct tunneling current density can be calculated as a function of the stress

σ

1 gate-to-source/drain-extension overlap length. The tunneling lifetime in above equation can be connected with the transmission probability T:

τ

( σ ) = π ħ/(T

σ

)E1(

σ

)).

Then with known process parameters and published deformation potential constants [5.19]

as input, the measured EDT was reproduced well as displayed in Fig. 5.7. Electron tunneling onto the forbidden silicon energy gap occurs in -0.1 V < VG < 0 V; however, an appreciable gate current was measured there. This indicates the existence of the oxide traps or interface states. Only at more negatively biased gate voltages where the EDT dominates can the effect of the traps be alleviated. In addition, it was found that the gate edge direct tunneling current is several orders of magnitude larger than the gate-to-substrate current and hence is dominant over the gate voltage range of interest. The extracted gate-to-source/drain overlap LTN spans a range of 6.1, 6.0, 5.7, and 5.0 nm for a of 10, 2.4, 0.495, and 0.21 μm, respectively as demonstrated in Fig. 5.8. The LTN

values are found to be comparable with those in the

literature [5.33]–[5.35]. The shift of around 1.1 nm, caused by dopant retarded lateral diffusion for stress change from 0 to -440 MPa, is reasonable with respective to the process simulation [5.13]. In the cited work [5.13], a device/process coupled simulation was carried out to produce the lateral doping profile from the source through the channel to the drain, with and without the strain dependencies. The resulting doping profiles reveal the diffusion retardation of about 1.8 nm as caused by a stress change from -10 to -500 MPa. It is therefore inferred that the extracted local stress and lateral diffusion shift are in satisfactory agreement with those of the process simulation published elsewhere [5.13].

The gate-to-source/drain-extension overlap length designated LTN is essentially proportional to the square root of dopant diffusivity D. The stress dependent dopant diffusivity can be expressed as [5.1], [5.4], [5.12]:

)

where Q is the strain induced activation energy and

ε

is the uniaxial strain.

ε

can be related to the uniaxial stress

σ with the Young’s modulus Y: σ =Y ε

. Then the effect of the stress on the extension overlap length can be derived as

The extracted extension overlap length is plotted in Fig. 5.9 versus the uniaxial corner stress.

Fitting of the data yields a value of –Q/kT = 129. Assuming a typical temperature of T = 1300 K for the manufacturing process, the activation energy Q of -15.7 eV results, which is reasonable relative to those (-14 eV for arsenic and -30 eV for phosphorus) of the process simulation [5.13]. Therefore, a physically oriented analytic model is reached, expressing the lateral diffusion length as a function of the corner stress.

5.5 Conclusion

With the aid of the layout technique, the source/drain extension corner stress has been for the first time extracted by using the subthreshold current measurement, and has been compared with the channel stress obtained by the additional measurements on the gate direct tunneling in inversion and mobility. The validity of the layout technique has been confirmed as well. With known process parameters and published deformation potential constants as input, fitting of the gate edge direct tunneling data has led to the value of the underlying lateral diffusion. The retarded lateral diffusion length and the strain induced activation energy both have been quantitatively consistent with those of the process simulation. A physically oriented analytic model has been reached, expressing the lateral diffusion as a function of the corner stress.

References

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IEDM Tech. Dig., 2002, pp. 117–120.

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944–961, Feb. 1956.

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1986.

[5.30] H. H. Mueller and M. J. Schulz, “Simplified method to calculate the band bending and the subband energies in MOS capacitors,” IEEE Trans. Electron Devices, vol. 44, pp. 1539–1543, Sep. 1997.

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current in polycrystalline silicon-gate metal-oxide-semiconductor devices,” Appl.

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[5.32] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (~1.5 GPa) channel stress,” IEEE Electron Device Lett., vol. 28, pp. 58–61, Jan. 2007.

[5.33] K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, C. H. Yu, M.

S. Liang, “Edge hole direct tunneling in off-state ultrathin gate oxide p-channel MOSFETs,” in IEDM Tech. Dig., 2000, pp. 679-682.

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2001.

0 2 4 6 8 10

-40 -35 -30 -25 -20 -15 -10 -5 0 5

V

= 0 V, V

= 0.6 V

Δ I

D(sub.)

/I

D(sub.)

(% )

Gate to STI Spacing ( μ m)

Fig. 5.1 The measured subthreshold current change versus gate to STI spacing.

0 2 4 6 8 10

Δ V

(mV)

Gate to STI Spacing ( μ m)

Fig. 5.2 Measured threshold voltage shift versus gate to STI spacing.

0 2 4 6 8 10

-16 -14 -12 -10 -8 -6 -4 -2 0 2

Gate to STI Spacing ( μ m)

Δμ / μ (%)

0 -100 -200 -300 -400 -500

σ (MPa)

Fig. 5.3 The extracted mobility variations and source/drain extension corner stress versus gate to STI spacing.

0 2 4 6 8 10

0.0 0.2 0.4 0.6 0.8

1.0 Channel Stress

Corner Stress Symbols: Experiment Lines: Model fitting

σ (a)/ σ (a

min

)

Gate to STI Spacing ( μ m)

Fig. 5.4 The plot showing the extracted channel and corner stress, divided by that of the minimum a, versus the gate to STI spacing, along with fitting curves from the citation [5.25].

-1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6

10

^-10

10

^-9

10

^-8

10

^-7

Substrate Current (A)

Gate Voltage (V)

a = 10

m a = 2.4

m a = 0.495

m a = 0.21

m

Fig. 5.5 Plot of the measured substrate current versus negative gate voltage.

V

_poly

V

_GD

V

_DE

t

_ox

E

_ox

n

⁺

- Poly Gate

Source/Drain Extension

E

≈ E

_fn

Fig. 5.6 Band diagram drawn along n⁺ poly-gate/SiO2/diffusion extension.

-1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

10

^-12

10

^-11

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

Symbols: Experiment

Lines: Simulation

Edge Tunneling Curr ent (A)

Gate Voltage (V)

a = 10

m a = 2.4

m a = 0.495

m a = 0.21

m

Fig. 5.7 Comparison of calculated and measured edge direct tunneling current versus negative gate voltage.

0 2 4 6 8 10

5.0 5.2 5.4 5.6 5.8 6.0 6.2

Gate to S/D Overlap (nm)

Gate to STI Spacing ( μ m)

Fig. 5.8 The extracted gate to source/drain extension overlap length versus gate to STI spacing. The decreasing trend with decreasing a can be related to the retarded lateral diffusion under the influence of the compressive stress.

V_G< 0

n⁺-poly gate

STI

Compressive stress retards lateral diffusion.

0 -100 -200 -300 -400 -500

0.80 0.85 0.90 0.95 1.00

a = 0.21

m a = 0.495

m

a = 2.4

m a = 10

m

Symbols: Experiment

Line: Curve fitting Based on Eq. (5.11)

L

( σ )/L

(0)

Uniaxial Corner Stress (MPa)

Q = - 15.7 eV

Fig. 5.9 The extracted (symbols) extension overlap length change versus corner stress. Also shown is a fitting line from Eq. (5.11).

Chapter 6 Effect of STI Mechanical Stress on p-Channel Gate Oxide Integrity

6.1 Introduction

Strained silicon has currently been adopted in the high-performance nanotechnologies.

There have been two fundamentally different approaches used to achieve this goal: (i) strained silicon on a relaxed buffer layer; and (ii) process strained silicon through the shallow trench isolation (STI), capping layer, silicide, or an embedded source/drain stressor [6.1],[6.2].

Examination of the interfacial properties or gate oxide integrity associated with strained devices is essentially crucial. Recently, a low-frequency noise measurement on strained

n-MOSFETs has revealed underlying gate oxide integrity [6.3],[6.4]. In this work, the noise

measurement is conducted on p-channel counterparts with the varying STI mechanical stress in the channel width direction.

6.2 Experiment

Devices under test were p-MOSFETs fabricated in a state-of-the-art manufacturing process. In this process, strain engineering was implemented using the shallow trench isolation (STI) technique. The STI mechanical stress under study was applied in the width direction as drawn in Fig. 1, achieved with the channel length fixed at 0.5μm while varying channel widths (0.11, 0.24, 0.6, 1, and 10 μm). Reduction in channel width means more

tensile stress in that direction. This argument was experimentally corroborated in terms of the enhanced drain current per unit width in Fig. 6.1 versus channel width. Technique concerning delta width and STI effects can be quoted in Chapter 4 to clarify the status of stress (tensile or compressive). The threshold voltage and low-field mobility of the devices were extracted from the linear regime of operation [6.5]. The low-frequency noise measurement setup detailed elsewhere [6.6] was employed. The measurement frequency ranged from 3 Hz to 100 kHz. Noise measurements were conducted under quasi-equilibrium conditions (VD= −0.05V) with the gate overdrive (VOV) as a parameter.

6.3 Results

As seen in Fig. 6.2, it is clear that Sid/ID2∝1/(VGS-VT), indicating that the mobility fluctuations or the Coulomb scattering part cannot be ignored. Therefore, the following so-called correlated mobility-number fluctuation approach was utilized for the input-referred voltage noise power spectral density [6.7]:

( ) ( )

where

α

is the effective scattering coefficient,

μ

eff is the low-field effective mobility, CEOT is the gate oxide capacitance per unit area, q is the elementary charge, kB is Boltzmann’s constant, T is the absolute temperature,

λ

is the tunneling distance (~0.1nm), W is the channel width, L is the channel length, and Nt is the interface-state density. Based on (1) and SVg

data

in Fig. 6.3, both Nt and

α

were determined from the SVg 0.5 versus -(VGS

-V

T) characteristics.

The results are shown in Fig. 6.4 and 6.5. It can be seen that on the average, for decreasing channel widths from 10 μm down to 0.11 μm, the interface-state density decreases whereas the scattering coefficient undergoes a relatively small change.

6.4 Physical Origins

Analogous to the ESR on (100) Si/SiO2 interface[6.8], the interface defects investigated here can be attributed to the group of Pb centers as a result of the mismatch between the Si substrate and SiO2 network. The network/lattice mismatch primarily originates from the volume expansion upon oxidation of Si. Obviously, with an enhanced tensile stress to relax the intrinsic interface strain, the network/lattice mismatch is diminished, leading to a reduction in Pb centers.

Another physical interpretation can be established by directly quoting the earlier works by Deal, et al. [6.9], as illustrated in Fig. 6.6. More tensile strain produces augmented lattice spacing or equivalently reduced excess silicon density per unit area, which in turn gives rise to decreased interface-state density.

6.5 Conclusion

The noise measurement on p-MOSFETs has revealed that an enhanced tensile stress in the channel narrowing direction can improve the gate oxide integrity. Its physical origins were related to relaxed interface strain and reduced excess silicon per unit area during the oxidation.

References

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Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.

Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S.

Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy,

“A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron

Devices, vol. 51, pp. 1790–1797, Nov. 2004.

[6.2] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C.

Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., 2003, pp. 73–76.

[6.3] E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Loo, K. De Meyer, and C.

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0.1 1 10

0 10 20 30 40 50

Δ J

d,app.

( σ )/ Δ J

d,app.

( σ

ref

) (%)

Channel Width ( μ m)

V

_OV

= - 0.8 V, V

= - 1 V

ΔW = 35nm

k

= -80 MPa

Fig. 6.1 Measured drain saturation current enhancement factor versus channel width. The inset shows the schematic illustration of STI mechanical stress in the width direction.

Tox

STI Mechanical Stress

Dielectric

0.05 0.1 0.15 0.2 0.25 0.3

10

^-10

10

^-9

WLS

/I

( μ m

/H z)

-(V

_GS

-V

) (V)

W = 10

m W = 1

m W = 0.6

m W = 0.24

m W = 0.11

m

L = 0.5

m, f = 100 Hz, V

= -0.05 V

Fig. 6.2 Normalized experimental drain current noise spectral density versus gate overdrive for different channel widths.

0.00 0.05 0.10 0.15 0.20 0.25

0.0 2.0x10

^-6

4.0x10

^-6

6.0x10

^-6

8.0x10

^-6

1.0x10

^-5

L = 0.5

m, f = 100 Hz, V

= -0.05 V

S

Vg0.5

(V/H z

0.5

)

-(V

_GS

-V

) (V)

W = 10

m W = 1

m W = 0.6

m W = 0.24

m W = 0.11

m

Fig. 6.3 Square root of measured input-referred noise voltage spectral density versus gate overdrive.

0.1 1 10

10

¹⁷

10

¹⁸

L = 0.5

m, f = 100 Hz, V

= -0.05 V

Trap D ensity (cm

-3

eV

-1

)

Channel Width ( μ m)

Fig. 6.4 Extracted effective interface-state density from Fig. 6.3.

0.1 1 10

7x10

⁴

8x10

⁴

9x10

⁴

10

⁵

1.1x10

⁵

1.2x10

⁵

Scattering Coe fficient (Vs/C)

Channel Width ( μ m)

Fig. 6.5 Extracted effective scattering coefficient from Fig. 6.3.

Distance

Concent ration

SiO

₂

O

₂

Si

Excess Silicon

Excess Oxygen

Distance

Concent ration

SiO

₂

O

₂

Si

Excess Silicon

Excess Oxygen

Fig. 6.6 Schematic illustration of the distribution of the excess species in an oxide film during oxidation [6.9].

Chapter 7 Conclusions and Future Work

7.1 Conclusions

This dissertation concerns the assessment of mechanical stress and modeling of physical behaviors in strained MOSFETs. Brief summaries of this work are listed as follows:

First of all, with known process parameters and published deformation potential constants as input, fitting of gate direct tunneling current versus gate voltage data has led to the value of the underlying channel stress. A link with the mobility measurement on the same device has been conducted. The resulting piezoresistance coefficient has been in good agreement with literature values. The layout technique has also been validated.

Second, we have systematically examined the delta width and channel stress effects on gate direct tunneling current of narrow n-MOSFETs under STI compressive stress. Both effects have been decoupled using a new analytic direct tunneling model. The validity of the extracted transverse channel stress and delta width has been confirmed. The effect of varying longitudinal channel stress due to the narrowing action has also been addressed. The corroborating evidence in terms of the drain current variation has further been established.

Then, with the aid of the layout technique, the source/drain extension corner stress has been for the first time extracted by using the subthreshold current measurement, and has been compared with the channel stress obtained by the additional measurements on the gate direct

在文檔中應變金氧半場效電晶體機械應力萃取與其相關物理模型建立之研究 (頁 66-0)