Strain-induced Energy Splitting

13

The effect of stress on the resistivity of Si was first investigated by Smith [2.6]. This finding was contributed to the modification of the electronic band structure. Microscopically, stress breaks the symmetry of lattice which can then cause the energy shift and band distortion. In the following these effects are discussed in detail.

Deformation potential theory originally developed by Bardeen and Shockley [2.7] was used to investigate the interaction of electrons with acoustic phonons. It was later generalized to include different scattering modes by Herring and Vogt [2.8]. The technique was applied to strained systems by Bir and Pikus [2.9].

Within the framework of this theory, the energy shift of a band extremum l is expanded in terms of the components of the strain tensor

ε

ij.

The coefficients of this expansion are called the deformation potential tensor. This tensor is characteristic of a given non-degenerate band in the solid. The symmetry of the strain tensor is also reflected in that of the deformation potential tensor, giving

( )l ( )l

ij ji

Ξ = Ξ (2.19)

The maximum number of independent components of this tensor is six which can reduce two or three for a cubic lattice. They are usually denoted by

Ξ

u, the uniaxial deformation potential constant, and

Ξ

d, the dilatation deformation potential constant. The deformation potential constants can be calculated using theoretical techniques such as density functional theory [2.10], the non-local empirical pseudo-potential method [2.11], or ab-initio calculations.

However, a final adjustment of the potentials is obtained only after comparing the calculated values with those obtained from measurement techniques [2.12]–[2.14]. The deformation potential constants used in this work are listed in Table 2.1 [2.15].

14

The general form of the strain-induced energy shifts of the conduction band valleys for an arbitrary strain tensor can be written as

( )^{i j,} ( )^j

( )

^{( )j T}

C d u i i

E Tr ε a ε a

Δ = Ξ + Ξ ⋅ ⋅ (2.20)

where ai is a unit vector of the ith valley minimum for the jth valley type. The first term in Eq.

(2.20) shifts the energy level of all the valleys equally and is proportional to the hydrostatic strain. The difference in the energy levels of the valleys arises from the second term in Eq.

(2.20). In this method, strain effect only shifts the band edge while it does not cause the band warping. In this study, the stress along <110> direction on (001) surface can first be transformed into strain. Then, by applying Eq. (2.20), the quantities of band shift for Δ2 and Δ4 valley can be expressed as

It is noteworthy that the approximation is reasonable under moderate stress [2.16] while it may need to include the effect band warping for large stress because of the strong influence of effective mass change.

15

References

[2.1] A. P. Boresi, R. J. Schmidt, and O. M. Sidebottom, “Advanced mechanics of materials,” 5th ed., New York: John Wiley & Son, 1993.

[2.2] H. A. Rueda, “Modeling of mechanical stress in silicon isolation technology and its influence on device characteristics,” Ph.D. Dissertation, University of Florida, 1999.

[2.3] C. Kittel, “Introduction to solid state physics,” 7th ed., New York: John Wiley & Son, 1995.

[2.4] S. Dhar, “Analytical mobility modeling for strained Silicon-based devices” Ph.D.

Dissertation, Vienna University of Technology, 2007.

[2.5] Y. Kanda, “Effect of stress on Germanium and Silicon p-n junctions,” Jpn. J. Appl.

Phys., Vol. 6, No. 4, pp. 475-486, 1967.

[2.6] C. S. Smith, “Piezoresistance effect in Germanium and Silicon,” Phys. Rev., vol. 94, no. 1, pp. 42-49, Apr. 1954.

[2.7] J. Bardeen and W. Shockley, “Deformation potentials and mobilities in non-polar crystals,” Phys. Rev., vol. 80, pp. 72-80, Oct. 1950.

[2.8] C. Herring and E. Vogt, “Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering,” Phys. Rev., vol. 101, pp. 944-961, Feb.

1956.

[2.9] G. L. Bir and G. E. Pikus, “Symmetry and strain induced effects in semiconductors,'' New York: Wiley, 1974.

[2.10] C. G. Van de Walle, “Theoretical calculations of heterojunction discontinuities in the Si/Ge system,” Phys. Rev. B, vol. 34, pp. 5621-5633, Oct. 1986.

[2.11] M.V. Fischetti and S.E. Laux, “Band structure, deformation potentials, and carrier

16

mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, pp. 2234-2252, Aug. 1996.

[2.12] C. Herring and E. Vogt, “Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering,” Phys. Rev., vol. 101, pp. 944–961, Feb.

1956.

[2.13] I. Balslev, “Influence of uniaxial stress on the indirect absorption edge in silicon and germanium,” Phys. Rev., vol. 143, pp. 636–647, Mar. 1966.

[2.14] C. G. Van de Walle and R. M. Martin, “Theoretical calculations of heterojunction discontinuities in the Si/Ge system,” Phys. Rev. B, vol. 34, pp. 5621–5634, Oct.

1986.

[2.15] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs,” IEEE Electron Device

Lett., vol. 25, pp. 731–733, Nov. 2004.

[2.16] Y. Sun, S. E. Thompson, and T. Nishida, “Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 101, p.

104503, May 2007.

17

Table 2.1 Compliance and stiffness coefficients, Luttinger parameters, deformation potential constants, and split-off energy for silicon.

Stiffness Coefficients

c

11

(10

¹²

dyne/cm

²

)

1.657

c

12

(10

¹²

dyne/cm

²

)

0.639

c

44

(10

¹²

dyne/cm

²

)

0.796

Compliance Coefficients

s

11

(10

^-12

m

²

/Nt)

7.68

s

12

(10

^-12

m

²

/Nt)

-2.14

s

44

(10

^-12

m

²

/Nt)

12.6

Deformation Potential Constants

Ξ

d

(eV)

1.13

Ξ

u

(eV)

9.16

18 A

FN

FS

F

(a)

y

z

x

yy

zz

xx

yx

zy xz

zx

yz xy

(b)

Fig. 2.1 (a) Schematic of an arbitrary force

Δ F acting on an infinitesimal area Δ A, along with

the resolved components: normal

Δ F

N and shear terms

Δ F

S. (b) A cubic element located within a continuous body with stress tensor components shown.

19

Fig. 2.2 Two-dimensional geometric deformation of an infinitesimal material element.

20

Chapter 3

Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially Stressed n-MOSFETs

3.1 Introduction

It is well recognized that the mechanical stress in MOSFETs can significantly affect many electrical properties such as the mobility [3.1]–[3.3], the hot carrier immunity [3.4], the threshold voltage [3.5], and the gate direct tunneling current [3.6]–[3.8]. Thus, the ability to quantitatively determine the magnitude of the underlying mechanical stress, as well as its status (compressive or tensile), is essential. Three fundamentally different methods have been introduced in this direction: (i) wafer bending jig [3.9]; (ii) sophisticated stress simulation [3.10]; and (iii) Raman spectroscopy [3.11]. Obviously, the electrical approach to the mechanical stress was lacking to date. However, it is noteworthy that the gate direct tunneling current has been well studied under externally applied mechanical stress [3.6]–[3.8].

Particularly in the citation [3.8], the deformation potential constants [3.12]–[3.14] have been experimentally determined with the values consistent with theoretical works [3.15]. Therefore, with known deformation potential constants, it is plausible to measure mechanical stress by means of the gate direct tunneling current.

In this chapter, we show how to transform the gate direct tunneling current in stressed devices into the value of the stress, achieved without adjusting any parameters. Confirmative evidence is presented in terms of the piezoresistance coefficient electrically created on the

21

same device.

3.2 Experiment

The n⁺ poly-silicon gate n-MOSFETs were fabricated in a state-of-the-art manufacturing process. The device process flow is depicted in Fig. 3.1. Also plotted in the Fig. 3.2 are the schematic cross section and topside view of the test device. Three key process parameters were obtained by capacitance-voltage (C−V) fitting: n⁺ poly-silicon doping concentration = 1

× 10 ²⁰ cm^-3, gate oxide thickness = 1.27 nm, and substrate doping concentration = 4 × 10 ¹⁷ cm^-3. In this process, the STI induced compressive stress was applied. The gate length along the <110> direction is 1 μm large enough that the following effects can be effectively eliminated: external series resistance and short channel or drain induced barrier lowering (DIBL). The gate width is wide (10 μm), indicating that the transverse stress is relatively negligible. Layout technique was utilized to produce a variety of stress in terms of the gate edge to STI sidewall spacing, designated a, with four values of 10, 2.4, 0.495, and 0.21 μm. A decrease in a means increased magnitude of longitudinal stress. A considerable number of contacts were formed on the source/drain diffusion along the gate width direction, far away from the STI in the <110> direction. The spacing between the diffusion contact and the gate edge is fixed in this work. It has been reported that silicide can introduce stress into channel and its effect can be eliminated by well controlling the silicide formation [3.10]. Thus, the silicide process was fine tuned for the device under study to minimize its effect as compared with STI stress.

The gate direct tunneling current was measured in inversion conditions with the source, drain, and substrate all tied to ground. Also characterized was the mobility on the same device at Vd = 25 mV. The change of the conduction-band electron direct tunneling current at Vg = 1

22

V and the mobility at Vg = 0.5 V, all with respect to a = 10 μm, are plotted in Fig. 3.3 versus gate to STI spacing. It can be seen that a decrease in the gate to STI spacing can produce an increase in both the gate current while degrading the mobility.

3.3 Stress Extraction

Existing direct tunneling models [3.16], [3.17] on the basis of the triangular potential approximation [3.18] in the channel, taking into account the poly-silicon depletion, can readily apply with some slight modifications such as incorporating stress dependencies of the subbands. The electrons in inversion primarily populate the two lowest subbands [3.8]: one of the two-fold valley Δ2 and one of the four-fold valley Δ4. The corresponding stress dependencies are well defined in the literature [3.8], [3.12]–[3.14]:

, 2 32 of Ref. [3.8], were cited here. Stress along <110> direction can be resolved into two different components: normal and shear stress terms in <100> coordination. Shear terms can cause the band distortion, which in turn, influences the effective mass. This effect becomes significant when applied strain approaches 1% and beyond, whose magnitude is much greater than that in our study case. Thus, it is reasonable to assume that effective mass change can be neglected under moderate stress in the subsequent calculation. One of the expressions for the effective

23

electric field Eeff can be found elsewhere [3.8]. With the aforementioned process parameters as input, the two lowest subband levels with respect to the Fermi level Ef can be determined. The stress dependencies of the lowest subbands under different gate voltages were found to be consistent with those in earlier works [3.8]. The inversion-layer carrier density per unit area can further be calculated by N_i =(k T_B /πh²)g m_{i di}ln(1 exp((+ E_f −E_i) /k T_B )) [3.16]–[3.18], where the subscript i denotes

Δ

2 or

Δ

4, kB

T is the thermal energy, g

i is the degeneracy of the valley, and mdi is the density of state effective mass. It is then a straightforward task to calculate the WKB tunneling probability, taking into account the corrections for reflections from the potential discontinuities [3.19]. Here the electron effective mass in the oxide for the parabolic type dispersion relationship was used with mox

~ 0.50 m

0, which is equivalent to mox

= 0.61 m0

for the tunneling electrons in the oxide using the Franz type dispersion relationship

[3.20]. The oxide can be thought of as an amorphous material. The irregular arrangement of oxide atoms makes its band structure and the electron tunneling effective mass in this layer difficult to be determined, especially for the strain condition. The theoretical calculation or experimental extraction of tunneling mass considering stress effect was still lacking. Thus, in this work, we assume that the electron effective mass in the oxide remains unchanged with stress varying. This assumption works well in predicting the strain-induced gate tunneling current [3.8]. The SiO2/Si interface barrier height in the absence of stress is 3.15 eV.

Consequently, without adjusting any parameters, the conduction-band electron direct tunneling current density can be calculated as a function of the stress

σ

[3.8]:

2 4

The tunneling lifetime in Eq.(3.3) can be related to the transmission probability T:

τ

Δ2

( σ ) = π ħ/(T

Δ2(

σ

)EΔ2(

σ

)) and

τ

Δ4

( σ ) = π ħ/(T

Δ4(

σ

)EΔ4(

σ

)).

With the above approach, we found that the uniaxial channel stress of around 0, ~0, -120,

24

and -280 MPa for gate to STI spacing of 10, 2.4, 0.495, and 0.21 μm, respectively, can reproduce gate direct tunneling current versus gate voltage characteristics. The corresponding gate current change is plotted in Fig. 3.4 versus extracted channel stress with gate voltage as a parameter. It can be seen that the magnitude of the gate current change increases linearly with the stress, consistent with those published elsewhere [3.8]. Again in agreement with the citation [3.8], the slope of the straight line in Fig. 3.4 increases with decreasing gate voltage.

This trend also points out that the accuracy of the proposed method can be considerably improved by lowering gate voltages.

3.4 Confirmative Evidence

The measured mobility change percentage versus extracted stress is shown in Fig. 3.5.

The straight line through the data points yields the slope or piezoresistance coefficient of -33.5 × 10 ^-12 dyne^-1 cm², close to that (-31.5 × 10 ^-12 dyne^-1 cm²) in the literature [3.21].

To testify to the layout technique mentioned above, we quote existing relationship between the effective channel stress and the gate to STI spacing, which was derived from the stress simulation [3.10]:

( ) ( _min)(1 ^min) variations (i.e. when a → ∞) with respect to

σ (a

min

). The extracted stress can be adequately

described by Eq. (3.4) with Vmσ = -1.05, as demonstrated in Fig. 3.6. Indeed, the projected stress for a = 10 μm, the reference point mentioned above, approaches zero. Therefore, the layout technique holds true in this work.

Finally, the electrical method accompanied with the layout technique was also applied to

25

other devices (with a sample size of 10) on the same wafer. The corresponding stress-induced variations in gate direct tunneling current were found to be comparable with those in Fig. 3.4.

3.5 Conclusion

With known process parameters and published deformation potential constants as input, fitting of gate direct tunneling current versus gate voltage data has led to the value of the underlying channel stress. A link with the mobility measurement on the same device has been conducted. The resulting piezoresistance coefficient has been in good agreement with literature values. The layout technique has also been validated.

26

References

[3.1] J. Welser, J. L. Hoyt, and J. F. Gibbons, “NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures,” in IEDM Tech. Dig., 1992, pp.

1000–1002.

[3.2] S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T.

Ghani, G. Glass, T. Hoffman, C. H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.

Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S.

Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy,

“A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron

Devices, vol. 51, pp. 1790–1797, Nov. 2004.

[3.3] C. H. Ge, C. C. Lin, C. H. Ko, C. C. Huang, Y. C. Huang, B. W. Chan, B. C. Perng, C. C. Sheu, P. Y. Tsai, L. G. Yao, C. L. Wu, T. L. Lee, C. J. Chen, C. T. Wang, S. C.

Lin, Y. C. Yeo, and C. Hu, “Process-strained Si (PSS) CMOS technology featuring 3D strain engineering,” in IEDM Tech. Dig., 2003, pp. 73–76.

[3.4] A. Hamada, T. Furusawa, N. Saito, and E. Takeda, “A new aspect of mechanical stress effects in scaled MOS devices,” IEEE Trans. Electron Devices, vol. 38, pp.

895–900, Apr. 1991.

[3.5] J. S. Lim, S. E. Thompson, and J. G. Fossum, “Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs,” IEEE Electron Device

Lett., vol. 25, pp. 731–733, Nov. 2004.

[3.6] W. Zhao, A. Seabaugh, V. Adams, D. Jovanovic, and B. Winstead, “Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain,” IEEE Electron Device Lett., vol. 26, pp. 410–412, Jun. 2005.

27

[3.7] X. Yang, J. Lim, G. Sun, K. Wu, T. Nishida, and S. E. Thompson, “Strain-induced changes in the gate tunneling currents in p-channel metal–oxide–semiconductor field-effect transistors,” Appl. Phys. Lett., vol. 88, pp. 052108, Jan. 2006.

[3.8] J. S. Lim, X. Yang, T. Nishida, and S. E. Thompson, “Measurement of conduction band deformation potential constants using gate direct tunneling current in n-type metal oxide semiconductor field effect transistors under mechanical stress,” Appl.

Phys. Lett., vol. 89, pp. 073509, Aug. 2006.

[3.9] C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E.

Robilliart, C. Raynaud, and H. Dansas, “Electrical analysis of mechanical stress induced by STI in short MOSFETs using externally applied stress,” IEEE Trans.

Electron Devices, vol. 51, pp. 1254–1261, Aug. 2004.

[3.10] R. A. Bianchi, G. Bouche, and O. Roux-dit-Buisson, “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in

IEDM Tech. Dig., 2002, pp. 117–120.

[3.11] I. D. Wolf, “Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits,” Semicond. Sci. Technol., vol. 11, pp. 139–154, 1996.

[3.12] C. Herring and E. Vogt, “Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering,” Phys. Rev., vol. 101, pp.

944–961, Feb. 1956.

[3.13] I. Balslev, “Influence of uniaxial stress on the indirect absorption edge in silicon and germanium,” Phys. Rev., vol. 143, pp. 636–647, Mar. 1966.

[3.14] C. G. Van de Walle and R. M. Martin, “Theoretical calculations of heterojunction discontinuities in the Si/Ge system,” Phys. Rev. B, vol. 34, pp. 5621–5634, Oct.

1986.

28

[3.15] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys., vol. 80, pp. 2234–2252, Aug. 1996.

[3.16] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices,” IEEE Trans. Electron Devices, vol. 46, pp.

1464–1471, Jul. 1999.

[3.17] K. N. Yang, H. T. Huang, M. C. Chang, C. M. Chu, Y. S. Chen, M. J. Chen, Y. M.

Lin, M. C. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p⁺ poly-gate pMOSFETs with ultrathin gate oxides,” IEEE

Trans. Electron Devices, vol. 47, pp. 2161–2166, Nov. 2000.

[3.18] H. H. Mueller and M. J. Schulz, “Simplified method to calculate the band bending and the subband energies in MOS capacitors,” IEEE Trans. Electron Devices, vol. 44, pp. 1539–1543, Sep. 1997.

[3.19] L. F. Register, E. Rosenbaum, and K. Yang, “Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semiconductor devices,” Appl.

Phys. Lett., vol. 74, pp. 457–459, Jan. 1999.

[3.20] Z. A. Weinberg, “On tunneling in metal-oxide-silicon structures,” J. Appl. Phys., vol.

53, pp. 5052–5056, Jul. 1982.

[3.21] S. Suthram, J. C. Ziegert, T. Nishida, and S. E. Thompson, “Piezoresistance coefficients of (100) silicon nMOSFETs measured at low and high (~1.5 GPa) channel stress,” IEEE Electron Device Lett., vol. 28, pp. 58–61, Jan. 2007.

29

Wafer Starting

Shallow Trench Isolation Active Area Patterning Gate Oxidation

Poly-Si Deposition Gate Patterning

Extension Implantation Spacer Formation

S/D Implantation Silicidation

Metallization

Fig. 3.1 Device formation process flow.

30

Fig. 3.2 (a) Schematic cross section and (b) topside view of the device under study. The gate edge to STI sidewall, a, is highlighted. The stress condition is compressive due to the lower thermal expansion rate of STI oxide compared to silicon.

31

0 2 4 6 8 10

0 2 4 6 8 10 12

(I

g

( σ )-I

g

(0))/I

g

(0) @ V

g

=1V (%)

Gate to STI Spacing ( μ m)

Fig. 3.3 The relative change of the gate direct tunneling current at Vg = 1V versus gate to STI spacing. The inset shows the mobility variations versus the gate to STI spacing.

0 2 4 6 8 10

-10 -8 -6 -4 -2 0

Δμ / μ (% )

Gate to STI Spacing (μm)

32

0 -50 -100 -150 -200 -250 -300 0

5 10 15 20

(I

g

( σ )-I

g

(0))/I

g

(0) (%)

Uniaxial Channel Stress (MPa)

V

_g

=0.50V V

_g

=0.75V V

_g

=1.00V Symbol: Experiment Line: Simulation

Fig. 3.4 The relative change of the gate direct tunneling current versus extracted uniaxial compressive channel stress for Vg

= 0.5, 0.75, and 1V. The symbols are experimental data.

The fitting line is drawn only for accommodating the trend.

33

0 -50 -100 -150 -200 -250 -300 -10

-8 -6 -4 -2 0

2

Line: Constructed relationship between

mobility and stress with π = -33.5 x 10^-12 cm²/dyne

a = 10

μ

m a = 2.4

μ

m a = 0.495

μ

m a = 0.21

μ

m

Δμ/μ (% )

Uniaxial Channel Stress (MPa)

Fig. 3.5 The measured mobility change versus extracted stress. Fitting the data yields the value of piezoresistance coefficient

π

= -33.5 × 10 ^-12 dyne^-1 cm².

34

0 2 4 6 8 10

0.0 0.2 0.4 0.6 0.8

1.0 Channel Stress

Symbols: Experiment Lines: Model fitting

σ (a)/ σ (a

min

)

Gate to STI Spacing ( μ m)

Fig. 3.6 The extracted stress, divided by that of the minimum a, versus the gate to STI spacing, along with a fitting curve from Eq. (3.4).

35

Chapter 4

Distinguishing Between STI Stress and Delta Width in Gate Direct Tunneling Current of Narrow n-MOSFETs

4.1. Introduction

The significance of the shallow trench isolation (STI) induced mechanical stress in highly scaled MOSFETs has been widely recognized [4.1]. The linkage between layout design and the underlying STI stress has also been well constructed [4.2]-[4.4]. Further applications pertaining to the layout dependencies of the STI stress altered dopant diffusion [4.5],[4.6], gate direct tunneling [4.6],[4.7], threshold voltage [4.6]-[4.8], subthreshold leakage [4.6],[4.8], and mobility [4.2],[4.4],[4.6],[4.7], have all been successfully demonstrated. However, care must be taken especially in the narrowing direction. The reasons are that on the one hand, the STI channel stress can be enhanced; however, on the other hand, the delta width

Δ W due to

STI corner rounding as schematically shown in Fig. 4.1 is of increasing importance. Thus, the ability to distinguish the delta width effect from the STI stress effect is essential. Two such examples on the drain current variation have recently been published [4.9],[4.10]. However, so far, effects on the gate direct tunneling current counterpart were not yet addressed in the open literature. In this work, we elaborate on how to unambiguously elucidate the STI stress altered gate direct tunneling current measured in the presence of n-MOSFET narrowing.

36

4.2 Experiment

The n⁺ poly-silicon gate n-MOSFETs on (001) wafer were fabricated in a state-of-the-art manufacturing process. Three key process parameters were obtained by a capacitance-voltage (C−V) fitting: n⁺ poly-silicon doping concentration = 1 × 10 ²⁰ cm^-3, gate oxide thickness = 1.27 nm, and channel doping concentration = 3 × 10 ¹⁷ cm^-3. In this process, STI induced compressive stress was applied. The gate length L, the gate edge to STI spacing in source diffusion, and the gate edge to STI spacing in drain diffusion, all in the channel length direction <110>, were fixed at the same value of 0.5 μm. The gate edge to STI spacing in the source diffusion is equal to that of the drain: The cross-sectional view of the test device is schematically shown in Fig. 4.1. The gate width W spanned in a wide range of 0.11, 0.24, 0.6, 1.0 and 10 μm. The gate direct tunneling current was measured in inversion with the source, drain, and substrate all tied to the ground. The change percentage of the apparent gate current per unit width, namely the actual gate current divided by corresponding W, with respect to W

= 10 μm, is plotted in Fig. 4.2 for Vg = 1 V versus W.

4.3 Data Fitting and Parameter Extraction

As illustrated in Fig. 4.1, the actual channel width designated Weff is the drawn gate width plus the delta width: Weff = W +

Δ W. The corresponding stress altered gate tunneling current

density can be expressed as a linear function of both the average longitudinal channel stress

σ

x and the average transverse channel stress

σ

y , which was obtained via a triangular potential based quantum simulation while incorporating the longitudinal and transverse stress dependencies of the subbands [4.11]:

37 same proportionality constant value was also utilized in our previous work concerning the longitudinal channel stress [4.6],[4.7]. On the basis of the two-dimensional STI stress

37 same proportionality constant value was also utilized in our previous work concerning the longitudinal channel stress [4.6],[4.7]. On the basis of the two-dimensional STI stress

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