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Conclusions and Suggestion for Future Work

Conclusions and Suggestion for Future Work

5.1 Conclusion

We have investigated the DC, AC, high-frequency, and RF power characteristics of LDMOS transistors with different layout designs. Based on the same breakdown voltage, we found that the transconductance, on-resistance, cutoff frequency, maximum oscillation frequency, even the power performance and linearity were improved using the ring structure.

In the traditional design, the ring (also called enclosed, edgeless, or donut in other literatures) structure was used to lower the parasitic capacitances for more linear and faster devices [1-2].

For MOSFET, the conventional parasitic drain capacitance refers to the n+ drain to p-substrate junction capacitance. Hence, the drain was always surrounded by the transistor channel and source to reduce the area. In LDMOS, however, the parasitic drain capacitance refers to the deep n-well (DNW) to p-substrate junction capacitance. Therefore, drain outside or inside for ring structure has no impact on drain capacitance. Since larger area for output terminal could improve the on-resistance, ring structure with drain outside layout would be the better choice for the LDMOS. This layout design can improve the performance without altering the process flow.

In chapter 2 fishbone with various drift lengths and channel widths were investigated.

The structure with smaller LDrift has better on-resistance, fT, fmax, and linearity, but smaller breakdown voltage. Fishbone and ring structures were also compared. The higher drain current and transconductance in the LDMOS with the ring structure were due to lower drain parasitic resistance. The fT and fmax were also enhanced for the ring structure due to the lower drain parasitic resistance.

In chapter 3, we investigated the thermal effect on DC and high-frequency characteristics

of fishbone and ring structures. The result shows that the fT and fmax were degraded at high temperatures due to lower transconductance. Because the drain resistance is higher in the LDMOS than the conventional MOSFET, the fT is also affected by drain resistance. By de-embedding the effect of drain resistance, we show the real relation between the temperature-induced variation of fT and gm. we also found that the temperature dependence of fmax is affected by the drain resistance and drain-substrate junction capacitance. To study the self-heating effect, DC and high-frequency characteristics were measured under pulse condition. From the extracted RTH and CTH, the effect of self-heating was more severe in ring structure. In the pulsed-mode measurement, the ring has better drain current, fT and fmax than the fishbone structure. Although the ring structure showed lower static drain current than the fishbone structure at high gate biases due to the significant self-heating effect, its current drive capability could be improved using a pulsed-mode operation.

Capacitance characteristics were analyzed completely in chapter 4. The thermal effects on capacitances were also investigated. For having a non-uniform doping channel, CGD

exhibits a peak at the threshold voltage. For existence of the drift region, CGS+ CGB and CGD

show a peak at the onset of quasi-saturation. In the ring structure, the second peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. Because the capacitances are affected mainly by the threshold voltage, quasi-saturation current and drift depletion capacitance, the variation of the capacitances with temperature is more complicated than that in conventional MOSFET, and it depends on the bias condition. Based on the result we analyzed, we can well model the temperature-dependence capacitance by adding these parameters and also can choose a bias condition with lower temperature sensitivity in capacitances.

5.2 Suggestion for Future Work

Since the thermal effects on drain current and capacitance were investigated clearly in

our study, the temperature dependent current and capacitance equations can be derived. In the future, the drain current, substrate current, gate capacitance, and junction capacitance models can be built in terms of surface potential. Eventually, a complete large signal model for RF LDMOS can be built.

In addition, the reliability issue of RF LDMOS is another important topic. The special DC behavior of LDMOS has been under study for several years [3-5]. The substrate current shows a second peak at high gate voltage [4]. The hot hole injection in the drift region after stress results in the degradation of on-resistance and increase of breakdown voltage, while it does not affect the threshold voltage [5]. Most of the reliability issues focus on DC performance, and seldom address the high frequency and RF power characteristics. In the future, the hot carrier effects on high frequency and power characteristics can to be investigated.

References

[1] P. L´opez, M. Oberst, H. Neubauer, and J. Hauer, “Performance analysis of high-speed MOS transistors with different layout styles,” in Proc. IEEE ISCAS, 2005, pp. 3688-3691.

[2] A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, “A high-density, matched hexagonal transistor structure in standard CMOS technology for high-speed applications,” IEEE Trans. Semiconductor Manufacturing, vol. 13, no. 2, pp. 167-172, 2000.

[3] J. F. Chen, K. M. Wu, K. W. Lin, Y. K. Su, and S. L. Hsu, “ Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” in Proc. IEEE IRPS, 2005 pp.560-564.

[4] S. K. Lee, C. J. Kim, J. H. Kim, Y. C. Choi, H. S. Kang, and C. S. Song, “Optimization of safe-operating-area using two peaks of body-currentin submicron LDMOS transistors,” in Proc. of ISPSD, 2001 pp.287-290.

[5] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot-hole injection degradation model for lateral nDMOStransistors,” IEDM Tech. Dig., Dec. 2001, pp.

877–880.

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