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Pulsed I-V/RF Characteristics of RF LDMOS

Characterization of RF LDMOS with Different Layout Design

3.3 Pulsed I-V/RF Characteristics of RF LDMOS

To study the self-heating effect on the performance of an LDMOS, we measured its I-V and RF characteristics under a pulsed condition. Figure 3.10 shows the timing diagram of the pulsing sequence. The quiescent biases for gate and drain were set to 0. The typical duration of the pulses for such measurements was 5 μs with a period of 1 ms. These values allow the devices to cool sufficiently during the off time of the pulse period. The measured data was sampled for a short delay time (tp=1.5 μs) to eliminate the self-heating effect. Figure 3.11 shows typical output characteristics of an LDMOS under static- and pulsed-mode measurements. At low gate voltages (VGS<2 V), the measured static current of the LDMOS was similar to the pulsed current. However, the measured static current was lower than the pulsed current at high gate voltages due to higher thermal heating in the steady state. In an

LDMOS, the channel temperature rises because of the power dissipation, and the carrier phonon scattering rate increases, which degrades the carrier mobility [16]. At high gate biases, the self-heating effect was shown to be significant due to increased power dissipation. In the saturation region, the channel length modulation and the impact ionization at high drain biases were also compensated by the self-heating effect. In the pulsed-mode operation, the self-heating effect was eliminated by the short pulse measurement with a low duty cycle.

Figure 3.12 shows the output characteristics of LDMOS transistors with different layout structures under the pulsed condition. Unlike the results in Fig. 2.8(b), without the self-heating effect, we found that the drain current of the ring structure was higher than that of the fishbone structure under all bias conditions. This suggests that the ring structure has better performance than the fishbone structure, when the transistors are used in pulsed-mode power amplifier applications.

The influence of the self-heating effect on high-frequency characteristics was investigated by pulsed RF measurement. The dependences of the cutoff frequency and maximum oscillation frequency on the gate voltage under cw and pulsed conditions wee shown in Fig. 3.13. The drain voltage was 28 V. At low gate voltages, the influence of device self-heating was minor. This resulted in approximately equal values under cw and pulsed conditions. As the gate voltage increased, the self-heating effect became more prominent, leading to larger difference between the measured values under cw and pulsed conditions. It was observed that the self-heating effect had a noticeable impact on RF performance. The degradation of RF performance by the self-heating effect was due to the decrease in transconductance, which depends directly on the temperature-dependent carrier mobility [17].

fT and fmax under the pulsed condition were improved by eliminating the self-heating effect. In Fig. 3.13, the ring structure also showed a greater difference in measured results between cw and pulsed conditions than the fishbone structure. This indicated that the self-heating effect

By using the pulse measurement system, the thermal resistance (RTH) and thermal capacitance (CTH) can also be obtained for fishbone and ring structures. Fixing the bias at VGS=4 V and VDS=28 V, RTH was derived by estimating the power dissipation at intersect point of static (at 25oC) and pulsed IV curve (35oC -100oC) [18-19]. The temperature rise was proportional to the power dissipated in the device channel and the slope of this line was RTH. The RTH extracted by TC (Power)= 25 + RTHPower is 64.81oC/W in the fishbone and 82.14oC/W in the ring (shown in Fig. 3.14) where TC is the channel temperature. Figure 3.15 shows the thermal transient at room temperature which was measured from transient drain current using the formula:

D( ) Di

where IDi is the initial drain current and IDS is the static drain current as shown in the inset of Fig. 3.15. CTH then can be extracted by fitting the equation: [1 TH TH]

The effects of temperature on the DC and high-frequency characteristics of RF LDMOS transistors were investigated in this chapter. The transconductance, threshold voltage, and channel mobility decrease with increasing temperature. The decrease in transconductance degrades the fT and fmax at high temperatures. Owing to the higher drain resistance in the LDMOS transistors, the fT is also affected by drain resistance. After de-embedding the effect of drain resistance, the temperature-induced fT variation is almost proportional to the gm

variation. In addition, we found that the temperature dependence of fmax is also affected by the drain resistance and drain-substrate junction capacitance. The measured S-parameters at various temperatures were also discussed. Because the LDMOS transistors with the ring

structure have a lower drain resistance and a lower drain-substrate junction capacitance, the variation in S22 with temperature is smaller than that in the fishbone structure. Furthermore, the self-heating effect of LDMOS transistors was also investigated by measuring the pulsed current-voltage (I-V) and pulsed RF characteristics. Although the ring structure showed lower static drain current than the fishbone structure at high gate biases due to the significant self-heating effect, its current drive capability could be improved using a pulsed-mode operation.

References

[1] S. M. Nam, B. J. Lee, S. H. Hong, C. G. Yu, J. T. Park and H. K. Yu, “Experimental investigation of temperature dependent RF performances of RF-CMOS devices,” in Proc.

VLSI and CAD (ICVC), 1999, pp. 174-177.

[2] Y. S. Lin, “Temperature dependence of the power gain and scattering parameters S11 and S22 of an RF nMOSFET with advanced RF-CMOS technology,” Microwave Opt. Technol.

Lett., vol. 44, no. 2, pp. 180-185, 2004.

[3] J. G. Su, S. C. Woni, C. Y. Chang, K. Y. Chiu, T. Y. Huang, C. T. Ou, C. H. Kao, and C. J.

Chao, “New insights on RF CMOS stability related to bias, scaling, andtemperature,” in Proc. IEEE Hong Kong Electron Devices Meeting, 2000, pp. 40-43.

[4] M. A. Belaid, K. Ketata, K. Mourgues, M. Gares, M. Masmoudi, and J. Marcon,

“Reliability study of power RF LDMOS device under thermal stress,” Microelectronics Journal, vol. 38, no. 2, pp. 164-170, 2007.

[5] G. M. Dolny, G. E. Nostrand, and K. E. Hill, “The effect of temperature on lateral DMOS transistors in a power IC technology,” IEEE Trans. Electron Devices, vol. 39, no. 4, pp.

990-995, 1992.

[6] Z. Radivojevic, K. Andersson, J. A. Bielen, P. J. van der Wel, and J. Rantala, “Operating limits for RF power amplifiers at high junction temperatures,” Microelectronics Reliability, vol. 44, no. 6, pp. 963-972, 2004.

[7] I. M. Filanovsky, A. Allam, and S. T. Lim, “Temperature Dependence of Output Voltage Generated by Interaction of Threshold Voltage and Mobility of an NMOS Transistor,” in Proc. Analog Integrated Circuits and Signal Processing, 2001, pp.229-238.

[8] Y. S. Koo, M. S. Kang, C. Choi, and C. An, “A Study on the Temperature Characteristics of Power LDMOSFETs Having Various Drift Region Lengths,” J. of the Korean Physical Society, vol. 39, no. 12, pp. S352-S355, 2001.

[9] M. Kodama, T. Sugiyama, and T. Uesugi, “Device parameter dependence of temperature

characteristics of lateral power MOSFET formed by solid-phase epitaxy,” Electronics and Communications in Japan (Part II: Electronics), vol. 84, no. 5, pp. 55-61, 2001.

[10] D. S. Jeon and D. E. Burk, “MOSFET electron inversion layer mobilities - A physically based semi-empirical model for a wide temperature range,” IEEE Trans. Electron Devices, vol. 36, no. 8, pp. 1456-1463, 1989.

[11] H. H. Hu, K. M. Chen, G. W. Huang, C. Y. Chang, Y. C. Lu, Y. C. Yang, and E. Chen,

“Characterization of RF Lateral-Diffused Metal–Oxide–Semiconductor Field-Effect Transistors with Different Layout Structures,” Jpn. J. Appl. Phys., vol. 46, no. 4B, pp.

2032–2036, Apr. 2007.

[12] Y. S. Lin, “An Analysis of Small-Signal Source-Body Resistance Effect on RF MOSFETs for Low-Cost System-on-Chip (SoC) Applications,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1442-1451, 2005.

[13] P. J. Tasker and B. Hughes, “Importance of source and drain resistance to the maximum fT of millimeter-wave MODFETs,” IEEE Electron Device Lett., vol. 10, No. 7, pp.

291-293, Jul. 1989.

[14] T. C. Lim and G. A. Armstronga, “The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance,” Solid-State Electron., vol. 50, pp. 774-783, 2006.

[15] S. S. Lu, C. Meng, T. W. Chen, and H. C. Chen, “The origin of the kink phenomenon of transistor scattering parameter S22,” IEEE Trans. Microwave Theory and Techniques, vol.

49, no. 2, pp. 333-340, 2001.

[16] M. Liang and M. E. Law, “Influence of lattice self-heating and hot-carrier transport ondevice performance,” IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2391-2398, 1994.

[17] A. S. Royet, B. Cabon, T. Ouisse, C. Brylinsky, O. Noblanc, and C. Dua, “Microwave characterisation and modelling of silicon carbide power MESFETS: towards a nonlinear

2003.

[18] K. A. Jenkins, and K. Rim, “Measurement of the effect of self-heating in strained-silicon MOSFETs,” IEEE Electron Device Lett., vol. 23, No. 6, pp. 360-362, Jun. 2002.

[19] C. P. Baylis ΙΙ, L. P. Dunleavy, J. E. Daniel, “Direct measurement of thermal circuit parameters using pulsed IV and the normalized difference unit,” IEEE MTT-S Digest, pp.

1233-1236. 2004.

[20] D. J. Walliey, T. J. Smy, D. Marchesan, H. Tran, C. Reimer, T. C. Kleckner, M. K.

Jackson, M. Schroter, J. R. Long, “Extraction and Modelling of Thermal Behavior in Trench Isolated Bipolar Structures,” in Proc. IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1999, pp. 97-100.

0 1 2 3 4

Fig. 3.1 (a) Subthreshold and (b) output characteristics of LDMOS transistors with different layout structures at 0 and 50oC.

-60 -40 -20 0 20 40 60 80 100 120 0.45

0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85

-1.66mV/oC

-1.68mV/oC

Threshold Voltage (V)

Temperature (oC)

Fishbone Ring

Fig. 3.2 Threshold voltage variation with temperature for different layout structures.

0.1 1 10 100

1000

Fishbone Ring

Channel Mobility (cm2 / (Vs))

Temperature (K)/300

Fig. 3.3 Temperature dependence of channel mobility for different layout structures.

1.0 1.5 2.0 2.5 3.0 3.5 4.0 2

4 6 8 10 12

Fishbone

fT

Frequency (GHz)

Gate Voltage(V)

-25oC 0oC 25oC 50oC

fmax

Ring

Fig. 3.4 Cutoff frequency and maximum oscillation frequency versus gate voltage at various temperatures.

Fig. 3.5 Extrinsic and intrinsic transconductances versus gate voltage at various temperatures for different layout structures.

1.0 1.5 2.0 2.5 3.0 3.5 4.0

0.005 0.010 0.015 0.020 0.025 0.030 0.035

Extrinsic

Transconductance (A/V)

Gate Voltage (V)

-25oC 0oC 25oC 50oC VDS=28V

Intrinsic

Ring

Fishbone

-10 -5 0 5 10 15 20

Fig. 3.6 (a) Extrinsic fT and (b) intrinsic fT variations versus intrinsic transconductance variation when temperature changes from 25oC.

-10 -5 0 5 10 15 20

Fig. 3.7 Extrinsic fmax variation versus intrinsic transconductance variation when temperature changes from 25oC.

0.2 0.5 1.0 2.0 5.0

Fig. 3.8 Measured (open symbols) and simulated (solid line) S-parameters of transistors with (a) fishbone and (b) ring structures from 0.1 to 10 GHz.

108 109 1010 -6

-5 -4 -3 -2 -1 0 1

Reducing gm

Fishbone

|S 22| (dB)

Frequency (GHz)

-250C 00C 250C 500C VGS=2V VDS=28V

Ring

Reducing gm

Fig. 3.9 Measured (open symbols) and simulated (solid line) |S22| of transistors for different layout structures from 0.1 to 10 GHz.

Fig. 3.10 Timing diagram showing the relationship of the applied bias, the RF input signal, and the sample points for pulsed measurement.

900ns 600ns

tp=1.5us Port1 (Gate)

Port2 (Drain)

RF

Meas_Delay

DC

S_Parameter

(RF pulse delay)

1ms (Pulse period) 5us (Pulse width)

Quiescent bias=0V

1us

(RF trig_delay)

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