Thermal Effect on Capacitances versus Drain Voltage

Fig. 4.10(a) shows the influence of temperature on CGS+CGB and CGD with different drain voltages at VGS =1 V. The temperature coefficients of CGS+CGB and CGD were positive at VDS

>0.5 V. Because the transistors operated in the median inversion region, the capacitances were mainly affected by threshold voltage. Hence the increases of capacitances were due to the reduction of threshold voltage. At VDS <0.5 V, the transistors operated in linear region, and the source side was inverted easier at high temperatures. Therefore, the CGS+CGB increased and CGD decreased with increasing temperature. At higher VDS, CGS+CGB became independent of the drain voltage and increased with increasing temperature. This is because part of the electrons in drift contributes to the CGS+CGB as shown in Fig. 4.3 (b) and CGS+CGB also affected by the depletion width. For higher temperature, the depletion width became shorter which means large electrons can be provided to the CGS+CGB.

Fig. 4.10(b) shows the influence of temperature on CGS+CGB and CGD with different

drain voltages at VGS =2V. The transistors operated in the strong inversion region, and the variations of capacitances with temperature were different as compared to that in Fig. 4.10(a).

At VDS <0.5V, where the transistor operated in linear region, the CGS+CGB increased and CGD

decreased slightly with increasing temperature. At 0.5V< VDS <6V, for transistor was entering the quasi-saturation region, the CGS+CGB decreased with increasing temperature, which is like as the capacitance behavior in Fig. 4.8(b). For CGD, its temperature coefficient was positive at lower gate voltages and became negative at higher gate voltages, due to the combined effects of quasi-saturation and depleted drift. At VDS >6 V, where the transistor operated in saturation region, the influence of temperature on CGS+CGB became smaller. At this time, the CGD was dominated by the drift depletion capacitance, and thus the CGD increased with temperature.

For the ring structure, the temperature dependence of capacitances was similar to that of the fishbone structure (see Fig. 4.11).

4.6 Summary

In this chapter, the capacitance characteristics of RF LDMOS transistors with different temperatures and layout structures were studied. Since LDMOS transistor has a lateral non-uniform doping channel and a drift region, peaks in CGS+CGB and CGD have been observed. In addition, the variation of the capacitances with temperature is more complicated than that in conventional MOSFET, and it depends on the bias condition. In a conventional fishbone structure, the peaks in capacitances decrease with increasing temperature. For the ring structure, two peaks in a capacitance-voltage curve have been observed at high drain voltages due to the additional corner effect. Besides, peaks in CGS+CGB decrease and peaks in CGD increase with increasing temperature at high drain voltages. These observations are important for circuit design to choose a bias condition with lower temperature sensitivity in capacitances. Moreover, since the capacitances are affected mainly by the threshold voltage,

quasi-saturation current and drift depletion capacitance, temperature effects on these parameters must be considered in the LDMOS capacitance model.

References

[1] S. Frére, J. Rhayem, H. Adawe, R. Gillon, M. Tack, and A. Walton, “LDMOS capacitance analysis versus gate and drain biases, based on comparison between TCAD simulations and measurements,” in Proc. IEEE ESSDERC, Sep. 2001, pp. 219–222.

[2] C. Anghel, Y. S. Chauhan, N. Hefyene, and A. Ionescu, “A physical analysis of HV MOSFET capacitance behaviour,” in Proc. IEEE ISIE, Jun. 2005, vol. 2, pp. 473–477.

[3] K. Narasimhulu, M. P. Desai, S. G. Narendra, and V. R. Rao, “The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance,” IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1416–1423, Sep. 2004.

[4] R. Valtonen, J. Olsson, and P. De Wolf, “Channel length extraction for DMOS transistors using capacitance-voltage measurements,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1454–1459, Jul. 2001.

[5] Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A.

M. Ionescu, “Analysis and modeling of lateral non-uniform doping in high-voltage MOSFETs,” in IEDM Tech. Dig., Dec. 2006, pp. 1–4.

[6] Y. S. Chauhan, R. Gillon, M. Declercq and A. M. Ionescu, “Impact of lateral non-uniform doping and hot carrier degradation on Capacitance behavior of High Voltage MOSFETs,”

in Proc. IEEE ESSDERC, Sep. 2007, pp. 426–429.

[7] Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. J. Declercq, and A. M.

Ionescu, “Compact modeling of lateral nonuniform doping in high-voltage MOSFETs,”

IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1527–1539, Jun. 2007.

[8] J. Jang, T. Amborg, Z. Yu, and R. W. Dutton, “Circuit model for power LDMOS including quasi-saturation,” in Proc. Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 1999, pp. 15–18.

[9] C. M. Liu and J. B. Kuo, “Quasi-saturation capacitance behavior of a DMOS device,”

IEEE Trans. Electron Devices, Vol. 44, No. 7, pp.1117-1123, July 1997.

[10] A. Giraldo, A. Paccagnella, and A. Minzoni, “Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout,” Solid-State Electronics, Vol. 44, pp. 981-989, June 2000.

[11] R. Giacomini, and J. A. Martino, “A simple current model for edgeless SOI nMOSFET and a 3-D analysis,” Solid-State Electronics, Vol. 49, pp. 1255-1261, August 2005.

[12] K. M. Chen, G. W. Huang, S. C. Wang, W. K. Yeh, Y. K. Fang, and F. L. Yang,

“Characterization and modeling of SOI varactors at various temperatures,” IEEE Trans.

Electron Devices, Vol. 51, No. 3, pp. 427-433, March 2004.

-4 -2 0 2 4

Fig. 4.1 Extracted CGS+CGB, CGD and the drain current versus gate voltage at different drain biases for the fishbone structure.

-4 -2 0 2 4

(a) (b)

(c) (d)

Fig. 4.2 Simulated CGS+CGB for four test structures: (a) uniform doped channel and without drift region, (b) non-uniform doped channel and without drift region, (c) uniform doped channel and with drift region, (d) non-uniform doped channel and with drift region.

0 1 2 3 4 5 6

(a)

(b)

Fig. 4.3 Device configurations (a) without drift region and (b) with drift region when gate voltage exceed the threshold voltage and drain voltage is low.

DNW

-4 -2 0 2 4

Fig. 4.4 Extracted CGS+CGB and CGD versus gate voltage at different drain biases for the ring structure.

(a)

(b)

Fig. 4.5 Schematic view of layout structure and current distribution: (a) fishbone structure and (b) ring structure.

Drain

Source Gate

Drift region channel

L

Current

Drift region channel

Source SourceDrain

L

Gate

Source Source Drain

L

-2 0 2 4 6 8 10 12 14 16 0

2 4 6 8 10 12 14

16 Fishbone

VGS=1V V_GS=1.2V V_GS=1.5V V_GS=2V

Capacitance(x10-13 F)

Drain Voltage (V) T=25^OC

C_GS+C_GB

C_GD

Fig. 4.6 Extracted CGS+CGB and CGD versus drain voltage at different gate biases for the fishbone structure.

.

-2 0 2 4 6 8 10 12 14 16 0

2 4 6 8 10 12 14

16 Ring V_GS=1V

V_GS=1.2V V_GS=1.5V V_GS=2V

Capacitance(x10-13 F)

Drain Voltage (V) C_GS+C_GB

C_GD T=25^OC

Fig. 4.7 Extracted CGS+CGB and CGD versus drain voltage at different gate biases for the ring structure.

-4 -2 0 2 4

Fig. 4.8 Extracted CGS+CGB and CGD versus gate voltage with various temperatures at drain voltage (a) VDS=0.1 V and (b) VDS=5 V for a fishbone structure. The inset shows the drain current versus gate voltage with various temperatures.

-4 -2 0 2 4

Fig. 4.9 Extracted CGS+CGB and CGD versus gate voltage with various temperatures at drain voltage (a) VDS=0.1 V and (b) VDS=5 V for a ring structure. The inset shows the drain current versus gate voltage with various temperatures.

-2 0 2 4 6 8 10 12 14 16

Fig. 4.10 Extracted CGS+CGB and CGD versus drain voltage with various temperatures at (a) VGS=1 V and (b) VGS=2 V for a fishbone structure.

-2 0 2 4 6 8 10 12 14 16

Fig. 4.11 Extracted CGS+CGB and CGD versus drain voltage with various temperatures at (a) VGS=1 V and (b) VGS=2 V for a ring structure.

Chapter 5

Conclusions and Suggestion for Future Work

5.1 Conclusion

We have investigated the DC, AC, high-frequency, and RF power characteristics of LDMOS transistors with different layout designs. Based on the same breakdown voltage, we found that the transconductance, on-resistance, cutoff frequency, maximum oscillation frequency, even the power performance and linearity were improved using the ring structure.

In the traditional design, the ring (also called enclosed, edgeless, or donut in other literatures) structure was used to lower the parasitic capacitances for more linear and faster devices [1-2].

For MOSFET, the conventional parasitic drain capacitance refers to the n+ drain to p-substrate junction capacitance. Hence, the drain was always surrounded by the transistor channel and source to reduce the area. In LDMOS, however, the parasitic drain capacitance refers to the deep n-well (DNW) to p-substrate junction capacitance. Therefore, drain outside or inside for ring structure has no impact on drain capacitance. Since larger area for output terminal could improve the on-resistance, ring structure with drain outside layout would be the better choice for the LDMOS. This layout design can improve the performance without altering the process flow.

In chapter 2 fishbone with various drift lengths and channel widths were investigated.

The structure with smaller LDrift has better on-resistance, fT, fmax, and linearity, but smaller breakdown voltage. Fishbone and ring structures were also compared. The higher drain current and transconductance in the LDMOS with the ring structure were due to lower drain parasitic resistance. The fT and fmax were also enhanced for the ring structure due to the lower drain parasitic resistance.

In chapter 3, we investigated the thermal effect on DC and high-frequency characteristics