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Characterization of RF LDMOS with Different Layout Design

2.3 Comparison of Two Layout Design: Fishbone and Ring

2.3.3 RF Power and Linearity

As well as the high-frequency characteristics, the microwave power characteristics were also investigated using the load-pull measurement. In our study, the input was terminated to 50 ohms and the load impedances were tuning for maximum output power. For having the value of fmax in the range from 8 GHz to 11 GHz, the devices were measured at 900 MHz with gate bias VGS=2 V and drain bias VDS=28 V. Figure 2.13 shows the output power, power gain and power added efficiency (PAE) with different drift lengths. In Fig. 2.13, the power characteristics were similar among these two transistors at low input power and show discrepancy when input power was larger than 1-dB compression point (P1db). The main reason for gain compression was attributed to the clipping effect. The border of output I-V curve will cause output waveform to be clipped for MESFET, PHEMT and HBT [18-20]. The

clipping effect can also been found in LDMOS. Figure 2.14 shows the drain current versus gate voltage with input and output waveform for different drift lengths. Part of the AC-signals on the drain current would be cut off as the input power becomes larger enough. At this condition, the average drain current increased with the increasing input power (see Fig. 2.15) and the power gain has been compressed. This is because the dynamic load line exceeds the border of DC I-V. As the drift length increased, larger on-resistance decreased the drain current which makes the negative duty cycle of output waveform enter the cutoff region earlier. This indicates that the average drain current started to increase earlier (see Fig. 2.15) and the gain compression occurs prior. Consequently, the transistor with longer drift length showed lower value of output power, power gain and PAE when input power was larger than P1db. Figure 2.16 shows the RF power characteristics for different layout structures. The ring structure exhibits a better performance than the fishbone.

Since the dc behaviors were changed, the linearity would also be affected with various drift lengths. The input and output third-order intercept points (IIP3 and OIP3) for fishbone with various drift lengths are listed in Table 2-6. Also, the ring and fishbone for fixed LDrift

=3.6μm were compared. For the fishbone structures, the transistor with longer drift length showed poor linearity. With fixed LDrift, IIP3 and OIP3 was similar in the fishbone and ring structure (as shown in Fig. 2.17).

2.4 Summary

Fishbone with various layout designs for RF applications were investigated. The structure with smaller LDrift has better on-resistance, fT, fmax, and linearity, but smaller breakdown voltage. It shows a trade-off between the on-resistance and the breakdown voltage in the conventional LDMOS. Fishbone and ring structures for RF applications were also compared. The ring structure had a better performance than the fishbone structure, without

altering the process flow. The higher drain current and transconductance in the LDMOS with the ring structure were due to lower drain parasitic resistance. In addition, the fT and fmax were also enhanced for the ring structure due to the lower drain parasitic resistance. Our results suggested that, using a ring structure, a higher breakdown voltage can be achieved using a longer LDrift without degrading DC and RF characteristics.

References

[1] S. P. Voinigescu, S. W. Tarasewicz, T. MacElwee, and J. Ilowski, “An assessment of the state-of-the-art 0.5 μm bulk CMOS technology for RF applications,” IEDM Tech. Dig., Dec. 1995, pp. 721–724.

[2] C. S. Kim, H. K. Yu, H. Cho, S. Lee, and K. S. Nam, “CMOS layout and bias optimization for RF IC design applications,” IEEE MTT-S Digest, pp. 945-948. 1997.

[3] H. Lee, J. H. Lee, Y. J. Park, and H. S. Min, “Characterization issues of gate geometry in multifinger structure for RF-SOI MOSFETs,” IEEE Electron Device Lett., vol. 23, No. 5, pp. 288-290, May 2002.

[4] M. M. De Souza, G. Cao, E. M. Sankara Narayanan, F. Youming, S. K. Manhas, J. Luo, and N. Moguilnaia, “Progress in silicon RF Power MOS technologies - current and future trends,” in Proc. International Caracas Conf. Devices, Circuits and Systems (ICCDCS), 2002, pp. D047 (1 – 7).

[5] R. Yang, J. F. Li, H. Qian, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “A Short-Channel SOI RF Power LDMOS Technology With TiSi2 Salicide on Dual Sidewalls With Cutoff Frequency fT ~19.3GHz,” IEEE Electron Device Lett., vol. 27, No. 11, pp.

917-919, Nov. 2006.

[6] P. L. Hower and M. J. Geisler, “Comparison of various source-gate geometries for power MOSFET's,” IEEE Trans. Electron Devices, vol. 28, no. 9, pp. 1098-1101, 1981.

[7] P. L. Hower, T. M. S. Heng, and C. Huang, “Optimum design of power MOSFETs,”

IEDM Tech. Dig., Dec. 1983, pp. 87–90.

[8] C. Hu, M. H. Chi, and V. M. Patel, “Optimum design of power MOSFETs,” IEEE Trans.

Electron Devices, vol. 31, no. 12, pp. 1693-1700, 1984.

[9] K. Board, D. J. Byrne, and M. S. Towers, “The optimization of on-resistance in vertical DMOS power devices with linear and hexagonal surface geometries,” IEEE Trans.

[10] J. Fernandez, S. Hidalgo, J. Paredes, F. Berta, J. Rebollo, J. Millan, and F. S. Mestres,

“An ON-resistance closed form for VDMOS devices,” IEEE Electron Device Lett., vol. 10, No. 5, pp. 212-215, May 1989.

[11] F. M. Rotella, G. Ma, Z. Yu, and R. W. Dutton, “Modeling, analysis, and design of RF LDMOS devices using harmonic-balance device simulation,” IEEE Trans. Microwave Theory Tech., vol. 48, No. 6, pp. 991-999, Jun 2000.

[12] S. C. Wang, G. W. Huang, K. M. Chen, A. S. Peng, H. C. Tseng, and T. L. Hsu, “A Practical Method to Extract Extrinsic Parameters for the Silicon MOSFET Small-Signal Model,” in Proc. NSTI Nanotechnology Conference & Trade Show (Nanotech 2004), 2004 p. 151-154.

[13] J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Banerjee, Z. Yu, and R. W. Dutton, “RF LDMOS characterization and its compact modeling,” IEEE MTT-S Digest, pp. 967-970.

2001.

[14] T. C. Lim and G. A. Armstronga, “The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance,” Solid-State Electron., vol. 50, pp. 774-783, 2006.

[15] C. S. Kim, H. K. Yu, H. Cho, S. Lee, and K. S. Nam, “CMOS layout and bias optimization for RF IC design applications,” IEEE MTT-S Digest, pp. 945-948. 1997.

[16] W. Wu, S. Lan, P. K. Ko, and M. Chan, “Characterization and modeling of waffle MOSFETs for high frequency applications,” in Proc. IEEE Solid-State and Integrated Circuits Tech. Conf., 2004, pp. 163-166.

[17] M. A. Belaid, K. Ketata, H. Maanane, M. Gares, K. Mourgues, and J. Marcon, “Analysis and simulation of self-heating effects on RF LDMOS devices,” in Proc. IEEE SISPAD, 2005, pp. 231-234.

[18] C. C. Meng, A. S. Peng, S. Y. Wen and G. W. Huang, “Direct Observation of Gain Compression Mechanisms in PHEMT by RF Gate and Drain Currents,” in Proc.

European Gallium Arsenide and Other Semiconductors Application Symp. (GaAs 2002),

Sep. 2002, pp. 241- 244.

[19] C. C. Meng, C. H. Chang, J. E Kuan and G. W. Huang, “Direct Observation of Loadlines in MESFET by Using Average RF Gate and Drain Currents,” IEEE MTT-S Digest, pp.

2161-2164. 2002.

[20] A. S. Peng, K. M. Chen, G. W. Huang, M. H. Cho, S. C. Wang, Y. M. Deng, H. C. Tseng, and T. L. Hsu, “Temperature Effect on Power Characteristics of SiGe HBTs,” IEEE MTT-S Digest, pp. 1955-1958. 2004.

Table 2-1 The extracted on-resistances for three samples with various drift lengths.

Table 2-2 Cut-off frequency and maximum oscillation frequency for three samples with various drift lengths.

Table 2-3 Extracted gm, Rd, Cgd, and Cgs for fishbone structure with various drift lengths. The fT and fmax differences between the LDrift=3.6μm and 3.0μm due to the change of model parameters are also listed.

gm (A/V) Rd (Ω) Cgd (F) Cgs (F) Fishbone

LDrift=3.6μm 29.69m 16.05 133.5f 877.2f

Fishbone

LDrift=3.0μm 27.08m 18.06 130.0f 951.0f

fT Difference 8.87% 0.68% -0.48% 6.77%

fmax Difference 6.88% 2.78% -0.86% 5.4%

Table 2-4 Extracted gm, Rd, Cgd, Cgs, and Cjdb for different layout structures. The fT differences between the fishbone and ring structures due to the change of model parameters are also listed.

gm (A/V) Rd (Ω) Cgd (F) Cgs (F) Cjdb (F) Fishbone

LDrift=3.6μm 27.08m 18.06 130.0f 951.0f 244f

Ring

LDrift=3.6μm 27.11m 7.789 119.0f 985.0f 149f

fT Difference 0.11% 3.56% 1.57% -2.8% 0.1%

Table 2-5 Extracted Rd, Cjdb, and Rg for different layout structures. The fmax differences between the fishbone and ring structures due to the change of model parameters are also listed.

Rd (Ω) Cjdb (F) Rg (Ω) Fishbone

LDrift=3.6μm 18.06 244f 1.997

Ring

LDrift=3.6μm 7.789 149f 4.489

fmax Difference 21.5% 14.28% -10.52%

Table 2-6 IIP3 and OIP3 for different layout structures with various drift length

IIP3 (dBm) OIP3 (dBm)

Fishbone

LDrift=3.0μm 29.18 41.60

Fishbone

LDrift=3.6μm 21.84 34.31

Ring

LDrift=3.6μm 21.51 34.29

(a) (b)

Fig. 2.1 LDMOS layout structures: (a) fishbone and (b) ring.

Fig. 2.2 Schematic cross section of an LDMOS transistor.

(a)

(b)

Fig. 2.3 Fishbone layout structures: (a) Sample 1 and (b) Sample 3.

Total channel width=120μm

Sample 1

Gate Drain

Source

Finger Width

Sample 3

Drain

Total channel width=240μm

Source

Finger Width

Gate

0 1 2 3 4 5

Fig. 2.4 (a) Subthreshold and (b) output characteristics of LDMOS transistors with different drift lengths.

(a)

(b)

Fig. 2.5 Dependence of (a) |h21| and (b) MSG/MAG on frequency obtained from S-parameter measurements.

Fig. 2.6 A simple equivalent circuit model of the LDMOS.

R

g

R

d

R

s

C

gs

R

i

R

sub

R

ds

=1/g

ds

C

sub

C

gd

C

ds

C

jdb

g

m

V

gs

G D

S

0

exp( )

m m

g = gj ωτ

Vgs

+ _

(a)

(b)

Fig. 2.7 (a) Intrinsic transconductance and (b) Cgs and Cgd versus drift length with different samples.

0 1 2 3 4 5

Fig. 2.8 (a) Subthreshold and (b) output characteristics of LDMOS transistors with different layout structures.

Drift Length (μm)

2 3 4 5

On-resistance (Ω-mm)

10 15 20 25 30 35 40

Fishbone Ring

Fig. 2.9 Ron versus LDrift for different layout structures.

2.8 3.0 3.2 3.4 3.6 3.8 0

2 4 6 8 10 12 14

fmax

LCH=0.5μm W=360μm

Frequency (GHz)

Drift Length (μm)

Fishbone Ring

VDS=28V, VGS=2V

fT

Fig. 2.10 Cut-off frequency and maximum oscillation frequency versus the drift length.

-50 -40 -30 -20 -10 0 10 20 30 40 50 -20

-15 -10 -5 0 5 10 15 20

gm

Changes in f T (%)

Changes in parameter value (%) Cjdb

Cgs

Rd Cgd

Fig. 2.11 (a) Effects of small-signal model parameters on fT.

-50 -40 -30 -20 -10 0 10 20 30 40 50 -20

-15 -10 -5 0 5 10 15 20

Rd

Cgd Cjdb

Cgs

Rg

Csub

Changes in f MAX (%)

Changes in parameter value (%) Rsub

Fig. 2.11 (b) Effects of small-signal model parameters on fmax.

2.4 2.8 3.2 3.6 4.0 4.4 4.8

Fig. 2.12 Rd versus LDrift for LDMOS with different layout structures. The inset shows that the drain region of the ring structure had extra areas (the shaded regions) compared with the fishbone structure.

-20 -10 0 10 20

Power Gain (dB), Output Power (dBm)

Input Power (dBm)

Fig. 2.13 Output power, power gain and PAE versus input power with different drift lengths.

Fig. 2.14 Drain current versus gate voltage with different drift lengths. The input signal was bias at VGS=2V and the negative duty cycle of output signal was clipped by the cutoff region.

Cutoff Condition

0 1 2 3 4

0 10 20 30 40 50 60 70

IDS (A)

VGS (V)

LDrift=3.0μm LDrift=3.6μm VDS=28V

P

in increase Output drain

current waveform

-20 -10 0 10 20 18

20 22 24 26 28 30 32 34 36

38 LDrift=3.0μm

LDrift=3.6μm

Average Drain Current (mA)

Input Power (dBm) Fishbone

VGS=2V, VDS=28V freq= 900MHz

Fig. 2.15 Average drain current as a function of the input power with different drift lengths.

-20 -10 0 10 20

Power Gain (dB), Output Power (dBm)

Input Power (dBm)

Fig. 2.16 Output power, power gain and PAE versus input power with different layout structures.

-10 -5 0 5 10 15 20 25

Output Power & IM3 (dBm)

Input Power (dBm)

Fig. 2.17 Output power and third-order intermodulation power versus input power with different layout structures.

Chapter 3

Thermal Effects on DC and RF Performances of RF LDMOS

3.1 Introduction

For high-power applications, temperature is an important issue. The cutoff frequency (fT) and maximum oscillation frequency (fmax) are critical figures of merit for evaluating the performance of RF transistors. For conventional MOS transistors in RF applications, the temperature effect was investigated by studying the temperature dependence of fT, which is proportional to the transconductance [1]. With an increase in temperature, the fT and fmax have been shown to decrease. According to its structure, the parasitic drain resistance of the LDMOS becomes more important than that of the conventional MOSFET for the present drift region. However, in most of the studies, the effect of the parasitic resistance was not considered when analyzing the temperature effect on the device characteristics [1-3]. By de-embedding the effect of the parasitic source and drain resistors from the measured S-parameters, the temperature dependence of the intrinsic fT can be analyzed. Several researchers have investigated the effects of temperature on the reliability and dc performances of LDMOS transistors [4-6]. However, the temperature effects on the high-frequency characteristics of LDMOS have seldom been addressed.

In this chapter, the DC and high-frequency characteristics of LDMOS transistors with different layout structures were studied at various temperatures. To study the self-heating effect, the pulsed current-voltage (I-V) and RF characteristics of LDMOS transistors are also discussed. The differences between the cw- and pulsed-mode measurements on drain current, cutoff frequency and maximum oscillation frequency are compared.

3.2.1 DC Characteristics

The DC characteristics of the LDMOS transistor with different layout structures at 0 and 50oC are compared in Fig. 3.1. At low gate voltages (VGS<1 V), the transconductance (gm) and drain current at 50oC were higher those that at 0oC owing to the decrease in the threshold voltage. At high gate voltages, because the channel mobility decreased with increasing temperature, the gm and drain current at 50oC became lower than that at 0oC. In low- and medium-bias regions, the ring structure showed a higher drain current and gm than the fishbone structure. For a high drain bias (VDS=28 V), the drain current and extrinsic gm had zero-temperature-coefficient biases near VGS=1.3 V and VGS=1 V, respectively. The zero-temperature-coefficient bias point results from the negative temperature coefficients of both the effective mobility and threshold voltage [5].

Figure 3.2 shows the threshold voltage plotted against temperature. The threshold voltage variations were -1.66 and -1.68 mV/0C for the fishbone and ring structures, respectively. The values in the literature varied from −1 to −4 mV/K with the most frequently noted value of −2 mV/K for the conventional CMOS [7]. For the LDMOS transistors, the threshold voltage variation in our study was smaller than the proposed values of -5.2 mV/0C [5], -3.2 mV/K [8], and -2.8 mV/0C [9]. This results from the lighter doping in the double-diffused channel.

The extracted channel mobility for different temperatures is shown in Fig. 3.3. The LDMOS channel mobility was deducted from the first-order one-dimensional model in the linear mode [5]:

This method is applicable for low drain voltages. The temperature dependence of the channel mobility can be modeled as μ=μ0 *(T/T0)-m, where m=1.35 for the fishbone structure and 1.36 for the ring structure. For intermediate inversion layer concentrations (N=0.5-5×1012

cm-3) at room temperature, the phonon-scattering-limited channel mobility has been observed to be dependent on N and T (μphTnN1/γ ), where γ=3-6 and n=1-1.5 [10]. Therefore, the mobility in our devices was dominated by the phonon scattering.

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