Design Concepts

From previous chapter, the specifications of dual-gain LNA are defined. The goal of this work is to design an LNA which can satisfy defined specifications. The LNA circuit has to be low noise figure, high gain and high linearity performance for wide dynamic range demand. Well matching networks can help to keep high power transfer efficiency between blocks. Moreover, for trend of minimizing size and power consumption in designing consumer electronic products nowadays, IC layout area and power consumption are more important issues than before.

It is a great challenge to balance effects of these issues, due to tradeoffs or conflicts between some of them. If LNA circuit has to be with high gain to reduce

noise, raise g_m is an effective way, but power consumption is raised, too. On the other hand, high gain LNA is suitable for small input signal, but when input signal is large, blocking problem will become seriously. The specifications in previous chapter declare that the requirement of gain and linearity is very severe. Even the dual-gain mode method will be used to release trade-off between gain and linearity specifications, design of proposed LNA is still not easy. There are some popular techniques which can solve gain, linearity and noise problems respectively, and they will be discussed below.

2.1.1 Gain Issue

Figure 2.1: A basic cascode CMOS LNA circuit

In the specification, the LNA power gain shall be more than 17dB in high gain mode. The common-source configuration is suitable for high gain, due to large effective load resistance as r_o of transistor [12]. The cascode configuration, with much larger load than common-source one, can enlarge gain more efficiently and easily.

Figure 2.1 depicts a basic cascode CMOS LNA circuit. The capacitor C_out is usually

very large as a DC block, and it can be ignored for load calculation. The effective load equals to parallel impedances Z2 and ZL. ZL is impedance of resonator which is formed by load inductor L_D and parasitic capacitance C_p. Z₂ is impedance seen from the drain of M2, and it can be derived by following formula:

(

)

2 r_o 1 g_m r_o r_o

Z = + + ⋅ ⋅ (6)

As mentioned before, the load is much larger than that of common-source only. But recently, for low power requirement in mobile devices, V_DD is getting smaller, and it gives restrict of using cascode structure. Folded structure or multiple stages can avoid the voltage room restrict, but they have to consume more power.

2.1.2 Linearity Issue

The LNA input IP3 specification in low gain mode is 5.5dBm. Such high linearity requirement is not easy to conquer, and so linearity enhancement technique shall be introduced to proposed LNA. The multiple gated transistor technique [13] is simple to use. The technique comes from the drain current i_DS versus v_gs equation of a common-source amplifier:

The v_gs³ term in (7) plays an important role in the third order intermodulation distortion [13][14]. Thus we can use two or more paralleled transistors with different bias voltage (as multiple gated transistors) to cancel g_m’’ term, and so the linearity of LNA can be enhanced. The concept of this technique is illustrated in Figure 2.2.

In this technique, V_bias2 is lower than V_bias1 with a constant offset. M₂ works in the sub-threshold region for positive gm’’ value by Vbias2, and so as to cancel gm’’ of M1.

Figure 2.2: Schematic and g_m’’ curve of multiple gated transistors technique

Because M₂ works in sub-threshold region, the current of M₂ is very small, and it gives no impact of power consumption. The gain will degrade in this technique, but it is not serious.

The linearity improvement is not quite obvious in the first paper of this technique (3dB OIP3 improvement in [13]). A formula of small signal circuit derived in [15]

gives a reason about the limit of original multiple gated transistors technique, where L is an inductor of source degeneration, and Z₁ is input impedance:

ε

In the last term of (9), the contribution of nonlinearity is not only comes from gm’’.

The original technique works only in low frequency operation, due to the last term is near to zero in low frequency. A modified technique which improves IIP3 near 20dB is presented in [16]. It uses a single tapped inductor for different source degeneration inductor values of two transistors. The circuit is depicted in Fig. 2.3.

Because the inductor value seen from the source of M₁ and M₃ are different, they can be adjusted to cancel the last term of (9) (as gm second-order distortion). M1

M₁

V_in M₃

V_bias3 V_bias1 C_B3

C_B1 L₂

L1

V_bias2

M₂ L₄

V_out C_B2

R3 R1

V_DD

Figure 2.3: Schematic of modified derivative superposition LNA (Bias circuit and input matching network are not shown)

works in active region, and M3 works in sub-threshold region. M2 forms the circuit as a cascode structure. The gain performance is good in this LNA, and gain degradation of using this techinique is smaller than 1dB. This technique is very useful for conquering requirements of proposed LNA.

2.1.3 Noise Issue

To be the first stage of receiver circuit, the noise problem is the most important issue in designing LNA circuit. Full integrated IC is popular for the system-on-chip design, but the low Q factor of on-chip inductor gives a challenge to it. The source degeneration technique is widely used for input matching (Figure 2.4). In this technique, the input signal is directly through the inductor Lin. If the Q factor of Lin is small, there will be a parasitic resistance on it, and it generates noise. Because the

inductor is just after the input port, it gives serious impact to LNA noise performance.

Thus the input inductor shall be carefully designed.

Figure 2.4: The source degeneration technique

The size selection of common-gate transistor is also an issue of noise performance.

The cascode stage has a smaller impact on the overall NF than input stage [17], but it plays an important role when the input stage is optimized. The [17] paper gives an reference of selecting the size of common-gate transistor.

The specification decided the same NF requirement for dual gain modes. Thus the degradation of NF performance in low gain mode has to be avoided. In the [9] circuit which is introduced in previous chapter, the noise variation between different gain modes is smaller. This technique can be an important design reference for the noise issue.